{"name":"marlin-verilog-macro-builder","vers":"0.1.0","deps":[{"name":"marlin-verilator","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"1ae4d4e33fa2266b25b221e400f1a3415e5553a84c7b124d951cb5fc1767e98d","features":{},"yanked":false,"rust_version":"1.83","pubtime":"2025-02-09T02:06:22Z"} {"name":"marlin-verilog-macro-builder","vers":"0.2.0","deps":[{"name":"marlin-verilator","req":"^0.2.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"c0cf2074abc673ee2d0ae76a8fe2555d164bb49e8abd02fc91eb22aeacc244ec","features":{},"yanked":false,"rust_version":"1.83","pubtime":"2025-02-21T10:45:20Z"} {"name":"marlin-verilog-macro-builder","vers":"0.2.1","deps":[{"name":"marlin-verilator","req":"^0.2.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"01baaea963d60eb61977606e863e02170cb9eb9fb0afd5fbf8c70d6939fa3938","features":{},"yanked":false,"rust_version":"1.83","pubtime":"2025-02-24T11:46:46Z"} {"name":"marlin-verilog-macro-builder","vers":"0.3.0","deps":[{"name":"marlin-verilator","req":"^0.3.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"3ce340efe6e750888f15a1ed5ece57e929f36710bfd4ba74d5e02d34ee97ad04","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-07T23:01:20Z"} {"name":"marlin-verilog-macro-builder","vers":"0.3.1","deps":[{"name":"marlin-verilator","req":"^0.3.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"c4657413b14dd4652bb39cc5e15d2ffc2480c69efec97ac87134d923adb07c07","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-08T02:24:49Z"} {"name":"marlin-verilog-macro-builder","vers":"0.3.2","deps":[{"name":"marlin-verilator","req":"^0.3.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"ef8bc1b0a235de53517613b76f19972516547cf79684726e9be45b15d8666244","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-08T04:30:38Z"} {"name":"marlin-verilog-macro-builder","vers":"0.3.3","deps":[{"name":"marlin-verilator","req":"^0.3.3","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"eb6bf62ebab0053ed6f4518d9393edf6a36d565b32ca3ddc3a7eedc5916087c5","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-11T02:02:18Z"} {"name":"marlin-verilog-macro-builder","vers":"0.3.4","deps":[{"name":"marlin-verilator","req":"^0.3.4","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"b129ee29a2680389a352cc9c6568fb52333705848420603cc16fc574609a6278","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-11T05:37:14Z"} {"name":"marlin-verilog-macro-builder","vers":"0.4.0","deps":[{"name":"marlin-verilator","req":"^0.4.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"862ac9f482f46ade81a26c6d789f8456eeb988e4dd95736437dbc4f47f0730a0","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-18T07:14:21Z"} {"name":"marlin-verilog-macro-builder","vers":"0.5.0","deps":[{"name":"marlin-verilator","req":"^0.5.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"8243f5a65e279ca0dce3e1f9fabb580e130af25a0b28c5fb95857eb10db07857","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-24T11:55:51Z"} {"name":"marlin-verilog-macro-builder","vers":"0.6.0","deps":[{"name":"marlin-verilator","req":"^0.6.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"68adfc825470f6bc0289b8e7d2b87e2b3c5f7b487e511781915798dca9fa8aec","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-27T21:57:31Z"} {"name":"marlin-verilog-macro-builder","vers":"0.6.1","deps":[{"name":"marlin-verilator","req":"^0.6.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"b7c974264e89c9dd07a1f8fd847c4362a01666e9ed7f6a766b9e14d4730bc6aa","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-30T21:56:43Z"} {"name":"marlin-verilog-macro-builder","vers":"0.6.2","deps":[{"name":"marlin-verilator","req":"^0.6.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"318ad63e4795709e9138f62055730eb39a2d3c034c419f6c5a410f4b5ef2df1f","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-04-05T02:41:25Z"} {"name":"marlin-verilog-macro-builder","vers":"0.7.0","deps":[{"name":"marlin-verilator","req":"^0.7.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"6f8e83ab7d65e3a290e6bf3954037186a3d5f15121b9393c007b073e1f8d0d80","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-06-06T11:22:57Z"} {"name":"marlin-verilog-macro-builder","vers":"0.7.1","deps":[{"name":"marlin-verilator","req":"^0.7.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"af6a85c76415e200054d2cc465d8e23b10c44e3ebd55aab5e2fa62e86c3be56b","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-06-07T00:22:11Z"} {"name":"marlin-verilog-macro-builder","vers":"0.7.2","deps":[{"name":"marlin-verilator","req":"^0.7.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"5e04c34006a389222ee6f55747aac2f2b010bb97672f0069e434fc34e388c2ce","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-08-20T04:47:18Z"} {"name":"marlin-verilog-macro-builder","vers":"0.8.0","deps":[{"name":"marlin-verilator","req":"^0.8.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"26e1f29752ce24ceebb346e38deea8f3509df88ec0efdb452c5f2a440b9ecae7","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-10-14T15:36:35Z"} {"name":"marlin-verilog-macro-builder","vers":"0.9.0","deps":[{"name":"marlin-verilator","req":"^0.9.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"5960956293f0cf8fc91c71a77ba51cc8b0a9ada59a13a1014e3a39a5d3a29c71","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-10-25T12:02:23Z"} {"name":"marlin-verilog-macro-builder","vers":"0.9.1","deps":[{"name":"marlin-verilator","req":"^0.9.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"fbdac215ef214206c94abba56065f64d8cc2503732c46ca906bb68834ad1175a","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-10-25T12:44:46Z"} {"name":"marlin-verilog-macro-builder","vers":"0.10.0","deps":[{"name":"marlin-verilator","req":"^0.10.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"9262fb8685f09046dec89f0d2e1bf6a9dd32db63f36ee14d59c7905746f7a6b0","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-12-12T11:21:35Z"} {"name":"marlin-verilog-macro-builder","vers":"0.10.1","deps":[{"name":"marlin-verilator","req":"^0.10.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.4","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"5c15921980b2d8f539c90fcd8e5e596a3b35b4b429400b6795ffde3cacab28ca","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T09:11:51Z"} {"name":"marlin-verilog-macro-builder","vers":"0.11.0","deps":[{"name":"marlin-verilator","req":"^0.11.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.4","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"1099be0fb008887283a2b4416b4c04f437abee1d382bc8d23e9553c091a8b4bb","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T09:36:37Z"} {"name":"marlin-verilog-macro-builder","vers":"0.11.1","deps":[{"name":"marlin-verilator","req":"^0.11.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.4","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"43e8bf9b545f8c8fe230e78af43e7b201e94f23d3cbcc7b13cc8833de2fa0c6d","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T10:44:30Z"} {"name":"marlin-verilog-macro-builder","vers":"0.11.2","deps":[{"name":"marlin-verilator","req":"^0.11.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.5","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"4ce74903487f81592d9b6be7912860d0bc646be55d0fff5bee043b58c3d3d5ca","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-05-01T07:30:39Z"} {"name":"marlin-verilog-macro-builder","vers":"0.11.3","deps":[{"name":"marlin-verilator","req":"^0.11.3","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.5","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"9b8d2fb0b51612fc6488e205a732d4cac759c96faa25569e42fe461b8d3509ec","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-05-01T07:39:46Z"} {"name":"marlin-verilog-macro-builder","vers":"0.12.0","deps":[{"name":"marlin-verilator","req":"^0.12.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.5","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"446cb83a99b82daa228a88d14251ecd1b35f14893ae6ca011bb112c8f002d7ba","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-05-01T20:59:09Z"} {"name":"marlin-verilog-macro-builder","vers":"0.13.0","deps":[{"name":"marlin-verilator","req":"^0.13.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.5","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"770a06d95e523b0b35e4504ac64e7a09dd15273ce4b794944410b89dfe84a2c2","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-05-02T02:25:06Z"} {"name":"marlin-verilog-macro-builder","vers":"0.14.0","deps":[{"name":"marlin-verilator","req":"^0.14.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.5","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"8b166cd54785f555535c2043fa8a555629d12994b74b8e296612cdc89ba7ff94","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-05-02T05:42:48Z"} {"name":"marlin-verilog-macro-builder","vers":"0.15.0","deps":[{"name":"marlin-verilator","req":"^0.15.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.5","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"57468c466bc4c5c6ef98afcefe8a7efcba6d00ceae85cd2af3b46382210062b9","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-05-03T02:56:27Z"} {"name":"marlin-verilog-macro-builder","vers":"0.16.0","deps":[{"name":"marlin-verilator","req":"^0.16.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.5","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"b120be92d5e23730d4a0f143616f32ad140557e939a32001ba1a9c4a219caca9","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-05-03T18:21:50Z"}