{"name":"sim-lib-lang-prolog","vers":"0.1.0-rc.1","deps":[{"name":"sim-codec","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-codec-lisp","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-kernel","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-control","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-core","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-lang-genconf","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-logic","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-arith","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-f64","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-i64","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-sequence","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-standard-core","req":"^0.1.0-rc.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"76510486956dff7d0c22e1cd4299c88deae5b49f7097ff1423b9231b4974e0ac","features":{},"yanked":false,"pubtime":"2026-07-03T01:48:39Z"} {"name":"sim-lib-lang-prolog","vers":"0.1.0","deps":[{"name":"sim-codec","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-codec-lisp","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-kernel","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-control","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-core","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-lang-genconf","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-logic","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-arith","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-f64","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-i64","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-sequence","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-standard-core","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"ec54a48f96e150b30cb281c65488309b3d515098ae415389f3936f0a93968ee0","features":{},"yanked":false,"pubtime":"2026-07-03T16:49:16Z"} {"name":"sim-lib-lang-prolog","vers":"0.1.1","deps":[{"name":"sim-codec","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-codec-lisp","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-kernel","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-kernel","req":"^0.1.0","features":["test-support"],"optional":false,"default_features":true,"target":null,"kind":"dev"},{"name":"sim-lib-control","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-core","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-lang-genconf","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-logic","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-arith","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-f64","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-numbers-i64","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-sequence","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sim-lib-standard-core","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"af8ffc7676424bda96b409577d7f13e8a4c9d4e175e3a345fb0b776c43e511cb","features":{},"yanked":false,"pubtime":"2026-07-06T09:37:01Z"}