   Compiling arithmetic-nonmax v0.4.0 (/home/naut3/arithmetic-nonmax)
    Finished `bench` profile [optimized] target(s) in 0.31s
     Running benches/iai_comparison.rs (target/release/deps/iai_comparison-bac8f18c8b00953a)
bench_new_nonmax_nonmaxu32
  Instructions:                  19 (No change)
  L1 Accesses:                   27 (+8.000000%)
  L2 Accesses:                    1 (-50.00000%)
  RAM Accesses:                   2 (-33.33333%)
  Estimated Cycles:             102 (-27.14286%)

bench_new_primitive_nonmaxu32
  Instructions:                  20 (No change)
  L1 Accesses:                   28 (+3.703704%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (-33.33333%)
  Estimated Cycles:             108 (-23.94366%)

bench_new_raw_nonmaxu32
  Instructions:                  18 (No change)
  L1 Accesses:                   25 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (No change)
  Estimated Cycles:             105 (No change)

bench_get_nonmax_nonmaxu32
  Instructions:                  19 (No change)
  L1 Accesses:                   26 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (No change)
  Estimated Cycles:             106 (No change)

bench_get_primitive_nonmaxu32
  Instructions:                  24 (No change)
  L1 Accesses:                   32 (+3.225806%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (-33.33333%)
  Estimated Cycles:             112 (-23.28767%)

bench_get_raw_nonmaxu32
  Instructions:                  18 (No change)
  L1 Accesses:                   25 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (No change)
  Estimated Cycles:             105 (No change)

bench_add_nonmax_nonmaxu32
  Instructions:                  25 (No change)
  L1 Accesses:                   33 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   3 (No change)
  Estimated Cycles:             148 (No change)

bench_add_primitive_nonmaxu32
  Instructions:                  36 (No change)
  L1 Accesses:                   47 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   3 (No change)
  Estimated Cycles:             162 (No change)

bench_add_raw_nonmaxu32
  Instructions:                  20 (No change)
  L1 Accesses:                   30 (+3.448276%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   1 (-50.00000%)
  Estimated Cycles:              75 (-31.19266%)

bench_cmp_nonmax_nonmaxu32
  Instructions:                  25 (No change)
  L1 Accesses:                   34 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (No change)
  Estimated Cycles:             114 (No change)

bench_cmp_primitive_nonmaxu32
  Instructions:                  32 (No change)
  L1 Accesses:                   41 (-2.380952%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   3 (+50.00000%)
  Estimated Cycles:             156 (+27.86885%)

bench_cmp_raw_nonmaxu32
  Instructions:                  26 (No change)
  L1 Accesses:                   34 (-5.555556%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   3 (+200.0000%)
  Estimated Cycles:             149 (+83.95062%)

bench_new_nonmax_nonmaxi32
  Instructions:                  24 (No change)
  L1 Accesses:                   31 (-3.125000%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (+100.0000%)
  Estimated Cycles:             111 (+44.15584%)

bench_new_primitive_nonmaxi32
  Instructions:                  25 (No change)
  L1 Accesses:                   33 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (No change)
  Estimated Cycles:             113 (No change)

bench_new_raw_nonmaxi32
  Instructions:                  23 (No change)
  L1 Accesses:                   30 (-3.225806%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (+100.0000%)
  Estimated Cycles:             110 (+44.73684%)

bench_get_nonmax_nonmaxi32
  Instructions:                  24 (No change)
  L1 Accesses:                   31 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (No change)
  Estimated Cycles:             111 (No change)

bench_get_primitive_nonmaxi32
  Instructions:                  29 (No change)
  L1 Accesses:                   37 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (No change)
  Estimated Cycles:             117 (No change)

bench_get_raw_nonmaxi32
  Instructions:                  23 (No change)
  L1 Accesses:                   30 (-3.225806%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (+100.0000%)
  Estimated Cycles:             110 (+44.73684%)

bench_add_nonmax_nonmaxi32
  Instructions:                  32 (No change)
  L1 Accesses:                   40 (-2.439024%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   3 (+50.00000%)
  Estimated Cycles:             155 (+28.09917%)

bench_add_primitive_nonmaxi32
  Instructions:                  41 (No change)
  L1 Accesses:                   51 (No change)
  L2 Accesses:                    2 (-33.33333%)
  RAM Accesses:                   4 (+33.33333%)
  Estimated Cycles:             201 (+17.54386%)

bench_add_raw_nonmaxi32
  Instructions:                  25 (No change)
  L1 Accesses:                   35 (No change)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   1 (No change)
  Estimated Cycles:              80 (No change)

bench_cmp_nonmax_nonmaxi32
  Instructions:                  30 (No change)
  L1 Accesses:                   38 (-5.000000%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   3 (+200.0000%)
  Estimated Cycles:             153 (+80.00000%)

bench_cmp_primitive_nonmaxi32
  Instructions:                  32 (No change)
  L1 Accesses:                   41 (-2.380952%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   3 (+50.00000%)
  Estimated Cycles:             156 (+27.86885%)

bench_cmp_raw_nonmaxi32
  Instructions:                  26 (No change)
  L1 Accesses:                   35 (-2.777778%)
  L2 Accesses:                    2 (No change)
  RAM Accesses:                   2 (+100.0000%)
  Estimated Cycles:             115 (+41.97531%)

bench_new_nonmax_nonmaxusize
  Instructions:                  24 (-99.43249%)
  L1 Accesses:                   31 (-99.42229%)
  L2 Accesses:                    2 (-100.0000%)
  RAM Accesses:                   2 (-98.87006%)
  Estimated Cycles:             111 (-99.03654%)

bench_new_primitive_nonmaxusize
  Instructions:                  25
  L1 Accesses:                   33
  L2 Accesses:                    2
  RAM Accesses:                   2
  Estimated Cycles:             113

bench_new_raw_nonmaxusize
  Instructions:                  23
  L1 Accesses:                   30
  L2 Accesses:                    2
  RAM Accesses:                   2
  Estimated Cycles:             110

bench_get_nonmax_nonmaxusize
  Instructions:                  24 (-99.43316%)
  L1 Accesses:                   31 (-99.42283%)
  L2 Accesses:                    2 (-100.0000%)
  RAM Accesses:                   2 (-98.87006%)
  Estimated Cycles:             111 (-99.03696%)

bench_get_primitive_nonmaxusize
  Instructions:                  29
  L1 Accesses:                   37
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             152

bench_get_raw_nonmaxusize
  Instructions:                  23
  L1 Accesses:                   29
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             144

bench_add_nonmax_nonmaxusize
  Instructions:                  30 (-99.29245%)
  L1 Accesses:                   38 (-99.29342%)
  L2 Accesses:                    2 (-100.0000%)
  RAM Accesses:                   3 (-98.30508%)
  Estimated Cycles:             153 (-98.67395%)

bench_add_primitive_nonmaxusize
  Instructions:                  41
  L1 Accesses:                   54
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             169

bench_add_raw_nonmaxusize
  Instructions:                  25
  L1 Accesses:                   33
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             148

bench_cmp_nonmax_nonmaxusize
  Instructions:                  30 (-99.29775%)
  L1 Accesses:                   38 (-99.29812%)
  L2 Accesses:                    2 (-100.0000%)
  RAM Accesses:                   3 (-98.31461%)
  Estimated Cycles:             153 (-98.68262%)

bench_cmp_primitive_nonmaxusize
  Instructions:                  32
  L1 Accesses:                   42
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             157

bench_cmp_raw_nonmaxusize
  Instructions:                  26
  L1 Accesses:                   35
  L2 Accesses:                    2
  RAM Accesses:                   2
  Estimated Cycles:             115

bench_new_nonmax_nonmaxisize
  Instructions:                  24 (-99.43316%)
  L1 Accesses:                   30 (-99.44144%)
  L2 Accesses:                    2 (-100.0000%)
  RAM Accesses:                   3 (-98.30508%)
  Estimated Cycles:             145 (-98.74197%)

bench_new_primitive_nonmaxisize
  Instructions:                  25
  L1 Accesses:                   33
  L2 Accesses:                    2
  RAM Accesses:                   2
  Estimated Cycles:             113

bench_new_raw_nonmaxisize
  Instructions:                  23
  L1 Accesses:                   30
  L2 Accesses:                    2
  RAM Accesses:                   2
  Estimated Cycles:             110

bench_get_nonmax_nonmaxisize
  Instructions:                  25 (-99.40968%)
  L1 Accesses:                   32 (-99.40432%)
  L2 Accesses:                    2 (-100.0000%)
  RAM Accesses:                   2 (-98.86364%)
  Estimated Cycles:             112 (-99.02583%)

bench_get_primitive_nonmaxisize
  Instructions:                  29
  L1 Accesses:                   37
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             152

bench_get_raw_nonmaxisize
  Instructions:                  23
  L1 Accesses:                   29
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             144

bench_add_nonmax_nonmaxisize
  Instructions:                  35 (-99.17550%)
  L1 Accesses:                   43 (-99.20134%)
  L2 Accesses:                    2 (-100.0000%)
  RAM Accesses:                   3 (-98.30508%)
  Estimated Cycles:             158 (-98.63073%)

bench_add_primitive_nonmaxisize
  Instructions:                  41
  L1 Accesses:                   54
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             169

bench_add_raw_nonmaxisize
  Instructions:                  25
  L1 Accesses:                   32
  L2 Accesses:                    3
  RAM Accesses:                   3
  Estimated Cycles:             152

bench_cmp_nonmax_nonmaxisize
  Instructions:                  32 (-99.25164%)
  L1 Accesses:                   39 (-99.28018%)
  L2 Accesses:                    3 (-100.0000%)
  RAM Accesses:                   3 (-98.31461%)
  Estimated Cycles:             159 (-98.63143%)

bench_cmp_primitive_nonmaxisize
  Instructions:                  32
  L1 Accesses:                   42
  L2 Accesses:                    2
  RAM Accesses:                   3
  Estimated Cycles:             157

bench_cmp_raw_nonmaxisize
  Instructions:                  27
  L1 Accesses:                   36
  L2 Accesses:                    2
  RAM Accesses:                   2
  Estimated Cycles:             116

