#![allow(dead_code)]

// AS7341 register addresses and constants.
//
// The AS7341 uses a banked register architecture. Registers 0x60–0x74
// are accessible only when CFG0.REG_BANK = 1 (low bank). All other
// registers are always accessible in the default bank (REG_BANK = 0).

// ── Always-accessible registers (REG_BANK = 0, default) ─────────────

pub const ENABLE: u8 = 0x80;
pub const ATIME: u8 = 0x81;
pub const WTIME: u8 = 0x83;
pub const SP_LOW_TH_L: u8 = 0x84;
pub const SP_LOW_TH_H: u8 = 0x85;
pub const SP_HIGH_TH_L: u8 = 0x86;
pub const SP_HIGH_TH_H: u8 = 0x87;
pub const AUXID: u8 = 0x90;
pub const REVID: u8 = 0x91;
pub const ID: u8 = 0x92;
pub const STATUS: u8 = 0x93;
pub const ASTATUS: u8 = 0x94;
pub const CH0_DATA_L: u8 = 0x95;
pub const CH0_DATA_H: u8 = 0x96;
pub const CH1_DATA_L: u8 = 0x97;
pub const CH1_DATA_H: u8 = 0x98;
pub const CH2_DATA_L: u8 = 0x99;
pub const CH2_DATA_H: u8 = 0x9A;
pub const CH3_DATA_L: u8 = 0x9B;
pub const CH3_DATA_H: u8 = 0x9C;
pub const CH4_DATA_L: u8 = 0x9D;
pub const CH4_DATA_H: u8 = 0x9E;
pub const CH5_DATA_L: u8 = 0x9F;
pub const CH5_DATA_H: u8 = 0xA0;
pub const STATUS2: u8 = 0xA3;
pub const STATUS3: u8 = 0xA4;
pub const STATUS5: u8 = 0xA6;
pub const STATUS6: u8 = 0xA7;
pub const CFG0: u8 = 0xA9;
pub const CFG1: u8 = 0xAA;
pub const CFG3: u8 = 0xAC;
pub const CFG6: u8 = 0xAF;
pub const CFG8: u8 = 0xB1;
pub const CFG9: u8 = 0xB2;
pub const CFG10: u8 = 0xB3;
pub const CFG12: u8 = 0xB5;
pub const PERS: u8 = 0xBD;
pub const GPIO2: u8 = 0xBE;
pub const ASTEP_L: u8 = 0xCA;
pub const ASTEP_H: u8 = 0xCB;
pub const AGC_GAIN_MAX: u8 = 0xCF;
pub const AZ_CONFIG: u8 = 0xD6;
pub const FD_CFG0: u8 = 0xD7;
pub const FD_TIME1: u8 = 0xD8;
pub const FD_TIME2: u8 = 0xDA;
pub const FD_STATUS: u8 = 0xDB;
pub const INTENAB: u8 = 0xF9;
pub const CONTROL: u8 = 0xFA;
pub const FIFO_MAP: u8 = 0xFC;
pub const FIFO_LVL: u8 = 0xFD;
pub const FDATA_L: u8 = 0xFE;
pub const FDATA_H: u8 = 0xFF;

// ── Low-bank registers (accessible when CFG0.REG_BANK = 1) ──────────

pub const CONFIG: u8 = 0x70;
pub const STAT: u8 = 0x71;
pub const EDGE: u8 = 0x72;
pub const GPIO: u8 = 0x73;
pub const LED: u8 = 0x74;

// ── ENABLE register bits ─────────────────────────────────────────────

pub const ENABLE_PON: u8 = 1 << 0;
pub const ENABLE_SP_EN: u8 = 1 << 1;
pub const ENABLE_WEN: u8 = 1 << 3;
pub const ENABLE_SMUXEN: u8 = 1 << 4;
pub const ENABLE_FDEN: u8 = 1 << 6;

// ── STATUS2 bits ─────────────────────────────────────────────────────

pub const STATUS2_AVALID: u8 = 1 << 6;

// ── CFG0 bits ────────────────────────────────────────────────────────

pub const CFG0_REG_BANK: u8 = 1 << 4;

// ── CONFIG (0x70, low bank) bits ─────────────────────────────────────

pub const CONFIG_LED_SEL: u8 = 1 << 3;

// ── LED (0x74, low bank) bits ────────────────────────────────────────

pub const LED_EN: u8 = 1 << 7;

// ── CFG6: SMUX command (bits [4:3]) ──────────────────────────────────

/// Write SMUX configuration from RAM.
pub const CFG6_SMUX_CMD_WRITE: u8 = 0x10;

// ── Device identification ────────────────────────────────────────────

/// Expected value of `ID` register (0x92) masked with 0xFC.
pub const CHIP_ID: u8 = 0x24;

// ── SMUX configurations ─────────────────────────────────────────────
//
// Each configuration is 20 bytes written to addresses 0x00–0x13.
// They route the 11 photodiodes to the 6 ADC channels.

/// SMUX config: ADC0=F1, ADC1=F2, ADC2=F3, ADC3=F4, ADC4=Clear, ADC5=NIR.
pub const SMUX_F1_F4_CLEAR_NIR: [u8; 20] = [
    0x30, // 0x00: F3 left → ADC2
    0x01, // 0x01: F1 left → ADC0
    0x00, // 0x02: reserved
    0x00, // 0x03: F8 left disabled
    0x00, // 0x04: F6 left disabled
    0x42, // 0x05: F4 left → ADC3, F2 left → ADC1
    0x00, // 0x06: F5 left disabled
    0x00, // 0x07: F7 left disabled
    0x50, // 0x08: Clear → ADC4
    0x00, // 0x09: F5 right disabled
    0x00, // 0x0A: F7 right disabled
    0x00, // 0x0B: reserved
    0x20, // 0x0C: F2 right → ADC1
    0x04, // 0x0D: F4 right → ADC3
    0x00, // 0x0E: F6/F8 right disabled
    0x30, // 0x0F: F3 right → ADC2
    0x01, // 0x10: F1 right → ADC0
    0x50, // 0x11: Clear right → ADC4
    0x00, // 0x12: reserved
    0x06, // 0x13: NIR → ADC5
];

/// SMUX config: ADC0=F5, ADC1=F6, ADC2=F7, ADC3=F8, ADC4=Clear, ADC5=NIR.
pub const SMUX_F5_F8_CLEAR_NIR: [u8; 20] = [
    0x00, // 0x00: F3 left disabled
    0x00, // 0x01: F1 left disabled
    0x00, // 0x02: reserved
    0x40, // 0x03: F8 left → ADC3
    0x02, // 0x04: F6 left → ADC1
    0x00, // 0x05: F4/F2 left disabled
    0x10, // 0x06: F5 left → ADC0
    0x03, // 0x07: F7 left → ADC2
    0x50, // 0x08: Clear → ADC4
    0x10, // 0x09: F5 right → ADC0
    0x03, // 0x0A: F7 right → ADC2
    0x00, // 0x0B: reserved
    0x00, // 0x0C: F2 right disabled
    0x00, // 0x0D: F4 right disabled
    0x24, // 0x0E: F8 right → ADC3, F6 right → ADC1
    0x00, // 0x0F: F3 right disabled
    0x00, // 0x10: F1 right disabled
    0x50, // 0x11: Clear right → ADC4
    0x00, // 0x12: reserved
    0x06, // 0x13: NIR → ADC5
];

/// SMUX config for flicker detection.
pub const SMUX_FLICKER: [u8; 20] = [
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
];
