use super::super::opcodes::*;
use crate::core::emitter::*;
use crate::core::operand::*;
use crate::x86::assembler::*;
use crate::x86::operands::*;

/// A dummy operand that represents no register. Here just for simplicity.
const NOREG: Operand = Operand::new();

/// `KANDNW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------------+
/// | # | Operands         |
/// +---+------------------+
/// | 1 | KReg, KReg, KReg |
/// +---+------------------+
/// ```
pub trait KandnwEmitter<A, B, C> {
    fn kandnw(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> KandnwEmitter<KReg, KReg, KReg> for Assembler<'a> {
    fn kandnw(&mut self, op0: KReg, op1: KReg, op2: KReg) {
        self.emit(
            KANDNWKKK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `KANDW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------------+
/// | # | Operands         |
/// +---+------------------+
/// | 1 | KReg, KReg, KReg |
/// +---+------------------+
/// ```
pub trait KandwEmitter<A, B, C> {
    fn kandw(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> KandwEmitter<KReg, KReg, KReg> for Assembler<'a> {
    fn kandw(&mut self, op0: KReg, op1: KReg, op2: KReg) {
        self.emit(
            KANDWKKK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `KMOVW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------+
/// | # | Operands   |
/// +---+------------+
/// | 1 | Gpd, KReg  |
/// | 2 | KReg, Gpd  |
/// | 3 | KReg, KReg |
/// | 4 | KReg, Mem  |
/// | 5 | Mem, KReg  |
/// +---+------------+
/// ```
pub trait KmovwEmitter<A, B> {
    fn kmovw(&mut self, op0: A, op1: B);
}

impl<'a> KmovwEmitter<KReg, KReg> for Assembler<'a> {
    fn kmovw(&mut self, op0: KReg, op1: KReg) {
        self.emit(KMOVWKK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

impl<'a> KmovwEmitter<KReg, Mem> for Assembler<'a> {
    fn kmovw(&mut self, op0: KReg, op1: Mem) {
        self.emit(KMOVWKM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

impl<'a> KmovwEmitter<Mem, KReg> for Assembler<'a> {
    fn kmovw(&mut self, op0: Mem, op1: KReg) {
        self.emit(KMOVWMK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

impl<'a> KmovwEmitter<KReg, Gpd> for Assembler<'a> {
    fn kmovw(&mut self, op0: KReg, op1: Gpd) {
        self.emit(KMOVWKR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

impl<'a> KmovwEmitter<Gpd, KReg> for Assembler<'a> {
    fn kmovw(&mut self, op0: Gpd, op1: KReg) {
        self.emit(KMOVWRK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

/// `KNOTW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------+
/// | # | Operands   |
/// +---+------------+
/// | 1 | KReg, KReg |
/// +---+------------+
/// ```
pub trait KnotwEmitter<A, B> {
    fn knotw(&mut self, op0: A, op1: B);
}

impl<'a> KnotwEmitter<KReg, KReg> for Assembler<'a> {
    fn knotw(&mut self, op0: KReg, op1: KReg) {
        self.emit(KNOTWKK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

/// `KORTESTW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------+
/// | # | Operands   |
/// +---+------------+
/// | 1 | KReg, KReg |
/// +---+------------+
/// ```
pub trait KortestwEmitter<A, B> {
    fn kortestw(&mut self, op0: A, op1: B);
}

impl<'a> KortestwEmitter<KReg, KReg> for Assembler<'a> {
    fn kortestw(&mut self, op0: KReg, op1: KReg) {
        self.emit(
            KORTESTWKK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `KORW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------------+
/// | # | Operands         |
/// +---+------------------+
/// | 1 | KReg, KReg, KReg |
/// +---+------------------+
/// ```
pub trait KorwEmitter<A, B, C> {
    fn korw(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> KorwEmitter<KReg, KReg, KReg> for Assembler<'a> {
    fn korw(&mut self, op0: KReg, op1: KReg, op2: KReg) {
        self.emit(
            KORWKKK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `KSHIFTLW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+-----------------+
/// | # | Operands        |
/// +---+-----------------+
/// | 1 | KReg, KReg, Imm |
/// +---+-----------------+
/// ```
pub trait KshiftlwEmitter<A, B, C> {
    fn kshiftlw(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> KshiftlwEmitter<KReg, KReg, Imm> for Assembler<'a> {
    fn kshiftlw(&mut self, op0: KReg, op1: KReg, op2: Imm) {
        self.emit(
            KSHIFTLWKKI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `KSHIFTRW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+-----------------+
/// | # | Operands        |
/// +---+-----------------+
/// | 1 | KReg, KReg, Imm |
/// +---+-----------------+
/// ```
pub trait KshiftrwEmitter<A, B, C> {
    fn kshiftrw(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> KshiftrwEmitter<KReg, KReg, Imm> for Assembler<'a> {
    fn kshiftrw(&mut self, op0: KReg, op1: KReg, op2: Imm) {
        self.emit(
            KSHIFTRWKKI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `KUNPCKBW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------------+
/// | # | Operands         |
/// +---+------------------+
/// | 1 | KReg, KReg, KReg |
/// +---+------------------+
/// ```
pub trait KunpckbwEmitter<A, B, C> {
    fn kunpckbw(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> KunpckbwEmitter<KReg, KReg, KReg> for Assembler<'a> {
    fn kunpckbw(&mut self, op0: KReg, op1: KReg, op2: KReg) {
        self.emit(
            KUNPCKBWKKK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `KXNORW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------------+
/// | # | Operands         |
/// +---+------------------+
/// | 1 | KReg, KReg, KReg |
/// +---+------------------+
/// ```
pub trait KxnorwEmitter<A, B, C> {
    fn kxnorw(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> KxnorwEmitter<KReg, KReg, KReg> for Assembler<'a> {
    fn kxnorw(&mut self, op0: KReg, op1: KReg, op2: KReg) {
        self.emit(
            KXNORWKKK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `KXORW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+------------------+
/// | # | Operands         |
/// +---+------------------+
/// | 1 | KReg, KReg, KReg |
/// +---+------------------+
/// ```
pub trait KxorwEmitter<A, B, C> {
    fn kxorw(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> KxorwEmitter<KReg, KReg, KReg> for Assembler<'a> {
    fn kxorw(&mut self, op0: KReg, op1: KReg, op2: KReg) {
        self.emit(
            KXORWKKK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpdEmitter<A, B, C> {
    fn vaddpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vaddpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VADDPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vaddpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VADDPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vaddpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VADDPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpdErEmitter<A, B, C> {
    fn vaddpd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddpd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpdMaskEmitter<A, B, C> {
    fn vaddpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vaddpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VADDPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vaddpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VADDPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vaddpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VADDPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpdMaskErEmitter<A, B, C> {
    fn vaddpd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddpd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpdMaskzEmitter<A, B, C> {
    fn vaddpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vaddpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VADDPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vaddpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VADDPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vaddpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VADDPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpdMaskzErEmitter<A, B, C> {
    fn vaddpd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddpd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpsEmitter<A, B, C> {
    fn vaddps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vaddps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VADDPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vaddps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VADDPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vaddps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VADDPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpsErEmitter<A, B, C> {
    fn vaddps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpsErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpsMaskEmitter<A, B, C> {
    fn vaddps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vaddps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VADDPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vaddps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VADDPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vaddps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VADDPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpsMaskErEmitter<A, B, C> {
    fn vaddps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpsMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpsMaskzEmitter<A, B, C> {
    fn vaddps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vaddps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VADDPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vaddps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VADDPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vaddps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VADDPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDPS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VaddpsMaskzErEmitter<A, B, C> {
    fn vaddps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddpsMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vaddps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VADDPS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddsdEmitter<A, B, C> {
    fn vaddsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddsdErEmitter<A, B, C> {
    fn vaddsd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddsdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddsd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddsdMaskEmitter<A, B, C> {
    fn vaddsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddsdMaskErEmitter<A, B, C> {
    fn vaddsd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddsdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddsd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddsdMaskzEmitter<A, B, C> {
    fn vaddsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddsdMaskzErEmitter<A, B, C> {
    fn vaddsd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddsdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddsd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddssEmitter<A, B, C> {
    fn vaddss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddssErEmitter<A, B, C> {
    fn vaddss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddssMaskEmitter<A, B, C> {
    fn vaddss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddssMaskErEmitter<A, B, C> {
    fn vaddss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddssMaskzEmitter<A, B, C> {
    fn vaddss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VaddssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vaddss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VADDSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VADDSS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VaddssMaskzErEmitter<A, B, C> {
    fn vaddss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VaddssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vaddss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VADDSSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VALIGND`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait ValigndEmitter<A, B, C, D> {
    fn valignd(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> ValigndEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn valignd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VALIGND128RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn valignd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND128RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn valignd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VALIGND256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn valignd(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn valignd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VALIGND512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn valignd(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VALIGND_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait ValigndMaskEmitter<A, B, C, D> {
    fn valignd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> ValigndMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn valignd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VALIGND128RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn valignd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND128RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn valignd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VALIGND256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn valignd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn valignd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VALIGND512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn valignd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VALIGND_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait ValigndMaskzEmitter<A, B, C, D> {
    fn valignd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> ValigndMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn valignd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VALIGND128RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn valignd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND128RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn valignd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VALIGND256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn valignd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn valignd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VALIGND512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValigndMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn valignd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGND512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VALIGNQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait ValignqEmitter<A, B, C, D> {
    fn valignq(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> ValignqEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn valignq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VALIGNQ128RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn valignq(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ128RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn valignq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VALIGNQ256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn valignq(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn valignq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VALIGNQ512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn valignq(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VALIGNQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait ValignqMaskEmitter<A, B, C, D> {
    fn valignq_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> ValignqMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn valignq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VALIGNQ128RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn valignq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ128RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn valignq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VALIGNQ256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn valignq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn valignq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VALIGNQ512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn valignq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VALIGNQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait ValignqMaskzEmitter<A, B, C, D> {
    fn valignq_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> ValignqMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn valignq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VALIGNQ128RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn valignq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ128RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn valignq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VALIGNQ256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn valignq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn valignq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VALIGNQ512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> ValignqMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn valignq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VALIGNQ512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VBLENDMPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VblendmpdEmitter<A, B, C> {
    fn vblendmpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VblendmpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vblendmpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VBLENDMPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vblendmpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VBLENDMPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vblendmpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VBLENDMPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vblendmpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VBLENDMPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vblendmpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VBLENDMPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vblendmpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VBLENDMPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VBLENDMPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VblendmpdMaskEmitter<A, B, C> {
    fn vblendmpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VblendmpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vblendmpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VBLENDMPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vblendmpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VBLENDMPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vblendmpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VBLENDMPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vblendmpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VBLENDMPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vblendmpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VBLENDMPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vblendmpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VBLENDMPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VBLENDMPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VblendmpdMaskzEmitter<A, B, C> {
    fn vblendmpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VblendmpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vblendmpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VBLENDMPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vblendmpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VBLENDMPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vblendmpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VBLENDMPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vblendmpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VBLENDMPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vblendmpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VBLENDMPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vblendmpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VBLENDMPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VBLENDMPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VblendmpsEmitter<A, B, C> {
    fn vblendmps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VblendmpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vblendmps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VBLENDMPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vblendmps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VBLENDMPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vblendmps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VBLENDMPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vblendmps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VBLENDMPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vblendmps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VBLENDMPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vblendmps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VBLENDMPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VBLENDMPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VblendmpsMaskEmitter<A, B, C> {
    fn vblendmps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VblendmpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vblendmps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VBLENDMPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vblendmps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VBLENDMPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vblendmps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VBLENDMPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vblendmps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VBLENDMPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vblendmps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VBLENDMPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vblendmps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VBLENDMPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VBLENDMPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VblendmpsMaskzEmitter<A, B, C> {
    fn vblendmps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VblendmpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vblendmps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VBLENDMPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vblendmps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VBLENDMPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vblendmps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VBLENDMPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vblendmps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VBLENDMPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vblendmps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VBLENDMPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VblendmpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vblendmps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VBLENDMPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VBROADCASTF32X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Mem |
/// | 2 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcastf32x4Emitter<A, B> {
    fn vbroadcastf32x4(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcastf32x4Emitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastf32x4(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTF32X4_256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vbroadcastf32x4Emitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastf32x4(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTF32X4_512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTF32X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Mem |
/// | 2 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcastf32x4MaskEmitter<A, B> {
    fn vbroadcastf32x4_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcastf32x4MaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastf32x4_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTF32X4_256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vbroadcastf32x4MaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastf32x4_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTF32X4_512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTF32X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Mem |
/// | 2 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcastf32x4MaskzEmitter<A, B> {
    fn vbroadcastf32x4_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcastf32x4MaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastf32x4_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTF32X4_256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vbroadcastf32x4MaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastf32x4_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTF32X4_512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTF64X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcastf64x4Emitter<A, B> {
    fn vbroadcastf64x4(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcastf64x4Emitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastf64x4(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTF64X4_512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTF64X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcastf64x4MaskEmitter<A, B> {
    fn vbroadcastf64x4_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcastf64x4MaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastf64x4_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTF64X4_512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTF64X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcastf64x4MaskzEmitter<A, B> {
    fn vbroadcastf64x4_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcastf64x4MaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastf64x4_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTF64X4_512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTI64X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcasti64x4Emitter<A, B> {
    fn vbroadcasti64x4(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcasti64x4Emitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcasti64x4(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTI64X4_512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTI64X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcasti64x4MaskEmitter<A, B> {
    fn vbroadcasti64x4_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcasti64x4MaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcasti64x4_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTI64X4_512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTI64X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait Vbroadcasti64x4MaskzEmitter<A, B> {
    fn vbroadcasti64x4_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vbroadcasti64x4MaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcasti64x4_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTI64X4_512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Mem |
/// | 2 | Ymm, Xmm |
/// | 3 | Zmm, Mem |
/// | 4 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VbroadcastsdEmitter<A, B> {
    fn vbroadcastsd(&mut self, op0: A, op1: B);
}

impl<'a> VbroadcastsdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vbroadcastsd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VBROADCASTSD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastsd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTSD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vbroadcastsd(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VBROADCASTSD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastsd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTSD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Mem |
/// | 2 | Ymm, Xmm |
/// | 3 | Zmm, Mem |
/// | 4 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VbroadcastsdMaskEmitter<A, B> {
    fn vbroadcastsd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VbroadcastsdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vbroadcastsd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VBROADCASTSD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastsd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTSD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vbroadcastsd_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VBROADCASTSD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastsd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTSD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Mem |
/// | 2 | Ymm, Xmm |
/// | 3 | Zmm, Mem |
/// | 4 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VbroadcastsdMaskzEmitter<A, B> {
    fn vbroadcastsd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VbroadcastsdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vbroadcastsd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VBROADCASTSD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastsd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTSD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vbroadcastsd_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VBROADCASTSD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastsdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastsd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTSD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VbroadcastssEmitter<A, B> {
    fn vbroadcastss(&mut self, op0: A, op1: B);
}

impl<'a> VbroadcastssEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vbroadcastss(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VBROADCASTSS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssEmitter<Xmm, Mem> for Assembler<'a> {
    fn vbroadcastss(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VBROADCASTSS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vbroadcastss(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VBROADCASTSS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssEmitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastss(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTSS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vbroadcastss(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VBROADCASTSS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastss(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTSS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VbroadcastssMaskEmitter<A, B> {
    fn vbroadcastss_mask(&mut self, op0: A, op1: B);
}

impl<'a> VbroadcastssMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vbroadcastss_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VBROADCASTSS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vbroadcastss_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VBROADCASTSS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vbroadcastss_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VBROADCASTSS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastss_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTSS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vbroadcastss_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VBROADCASTSS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastss_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTSS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VBROADCASTSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VbroadcastssMaskzEmitter<A, B> {
    fn vbroadcastss_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VbroadcastssMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vbroadcastss_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VBROADCASTSS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vbroadcastss_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VBROADCASTSS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vbroadcastss_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VBROADCASTSS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vbroadcastss_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VBROADCASTSS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vbroadcastss_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VBROADCASTSS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VbroadcastssMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vbroadcastss_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VBROADCASTSS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCMPPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmppdMaskEmitter<A, B, C, D> {
    fn vcmppd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmppdMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcmppd_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VCMPPD128KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppdMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vcmppd_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VCMPPD128KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppdMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vcmppd_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VCMPPD256KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppdMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vcmppd_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VCMPPD256KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppdMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vcmppd_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VCMPPD512KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppdMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vcmppd_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VCMPPD512KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPPD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmppdMaskSaeEmitter<A, B, C, D> {
    fn vcmppd_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmppdMaskSaeEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vcmppd_mask_sae(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VCMPPD512KRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPPD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmppdSaeEmitter<A, B, C, D> {
    fn vcmppd_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmppdSaeEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vcmppd_sae(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VCMPPD512KRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmppsMaskEmitter<A, B, C, D> {
    fn vcmpps_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmppsMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcmpps_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VCMPPS128KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppsMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vcmpps_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VCMPPS128KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppsMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vcmpps_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VCMPPS256KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppsMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vcmpps_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VCMPPS256KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppsMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vcmpps_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VCMPPS512KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmppsMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vcmpps_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VCMPPS512KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPPS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmppsMaskSaeEmitter<A, B, C, D> {
    fn vcmpps_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmppsMaskSaeEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vcmpps_mask_sae(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VCMPPS512KRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPPS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmppsSaeEmitter<A, B, C, D> {
    fn vcmpps_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmppsSaeEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vcmpps_sae(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VCMPPS512KRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmpsdMaskEmitter<A, B, C, D> {
    fn vcmpsd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmpsdMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcmpsd_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VCMPSDKRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmpsdMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vcmpsd_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VCMPSDKRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPSD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Xmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmpsdMaskSaeEmitter<A, B, C, D> {
    fn vcmpsd_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmpsdMaskSaeEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcmpsd_mask_sae(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VCMPSDKRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPSD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Xmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmpsdSaeEmitter<A, B, C, D> {
    fn vcmpsd_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmpsdSaeEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcmpsd_sae(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VCMPSDKRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmpssMaskEmitter<A, B, C, D> {
    fn vcmpss_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmpssMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcmpss_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VCMPSSKRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VcmpssMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vcmpss_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VCMPSSKRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPSS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Xmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmpssMaskSaeEmitter<A, B, C, D> {
    fn vcmpss_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmpssMaskSaeEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcmpss_mask_sae(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VCMPSSKRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCMPSS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Xmm, Imm |
/// +---+---------------------+
/// ```
pub trait VcmpssSaeEmitter<A, B, C, D> {
    fn vcmpss_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VcmpssSaeEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcmpss_sae(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VCMPSSKRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VCOMISD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VcomisdEmitter<A, B> {
    fn vcomisd(&mut self, op0: A, op1: B);
}

impl<'a> VcomisdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcomisd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMISDRR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcomisdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcomisd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCOMISDRM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMISD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VcomisdSaeEmitter<A, B> {
    fn vcomisd_sae(&mut self, op0: A, op1: B);
}

impl<'a> VcomisdSaeEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcomisd_sae(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMISDRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMISS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VcomissEmitter<A, B> {
    fn vcomiss(&mut self, op0: A, op1: B);
}

impl<'a> VcomissEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcomiss(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMISSRR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcomissEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcomiss(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCOMISSRM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMISS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VcomissSaeEmitter<A, B> {
    fn vcomiss_sae(&mut self, op0: A, op1: B);
}

impl<'a> VcomissSaeEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcomiss_sae(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMISSRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMPRESSPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Ymm, Ymm |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VcompresspdEmitter<A, B> {
    fn vcompresspd(&mut self, op0: A, op1: B);
}

impl<'a> VcompresspdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vcompresspd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VCOMPRESSPD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vcompresspd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VCOMPRESSPD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vcompresspd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VCOMPRESSPD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcompresspd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMPRESSPD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcompresspd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCOMPRESSPD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcompresspd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCOMPRESSPD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMPRESSPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Ymm, Ymm |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VcompresspdMaskEmitter<A, B> {
    fn vcompresspd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VcompresspdMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vcompresspd_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VCOMPRESSPD128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vcompresspd_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VCOMPRESSPD256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vcompresspd_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VCOMPRESSPD512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcompresspd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMPRESSPD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcompresspd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCOMPRESSPD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcompresspd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCOMPRESSPD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMPRESSPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Ymm, Ymm |
/// | 3 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VcompresspdMaskzEmitter<A, B> {
    fn vcompresspd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VcompresspdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcompresspd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMPRESSPD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcompresspd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCOMPRESSPD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcompresspd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCOMPRESSPD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMPRESSPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Ymm, Ymm |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VcompresspsEmitter<A, B> {
    fn vcompressps(&mut self, op0: A, op1: B);
}

impl<'a> VcompresspsEmitter<Mem, Xmm> for Assembler<'a> {
    fn vcompressps(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VCOMPRESSPS128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsEmitter<Mem, Ymm> for Assembler<'a> {
    fn vcompressps(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VCOMPRESSPS256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsEmitter<Mem, Zmm> for Assembler<'a> {
    fn vcompressps(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VCOMPRESSPS512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcompressps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMPRESSPS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcompressps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCOMPRESSPS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcompressps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCOMPRESSPS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMPRESSPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Ymm, Ymm |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VcompresspsMaskEmitter<A, B> {
    fn vcompressps_mask(&mut self, op0: A, op1: B);
}

impl<'a> VcompresspsMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vcompressps_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VCOMPRESSPS128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vcompressps_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VCOMPRESSPS256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vcompressps_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VCOMPRESSPS512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcompressps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMPRESSPS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcompressps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCOMPRESSPS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcompressps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCOMPRESSPS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCOMPRESSPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Ymm, Ymm |
/// | 3 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VcompresspsMaskzEmitter<A, B> {
    fn vcompressps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VcompresspsMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcompressps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCOMPRESSPS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcompressps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCOMPRESSPS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VcompresspsMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcompressps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCOMPRESSPS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtdq2pdEmitter<A, B> {
    fn vcvtdq2pd(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2pdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtdq2pd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTDQ2PD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtdq2pd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTDQ2PD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtdq2pd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTDQ2PD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtdq2pd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTDQ2PD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtdq2pd(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTDQ2PD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtdq2pd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTDQ2PD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtdq2pdMaskEmitter<A, B> {
    fn vcvtdq2pd_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2pdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtdq2pd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTDQ2PD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtdq2pd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTDQ2PD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtdq2pd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTDQ2PD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtdq2pd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTDQ2PD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtdq2pd_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTDQ2PD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtdq2pd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTDQ2PD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtdq2pdMaskSaeEmitter<A, B> {
    fn vcvtdq2pd_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2pdMaskSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtdq2pd_mask_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTDQ2PD512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtdq2pdMaskzEmitter<A, B> {
    fn vcvtdq2pd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2pdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtdq2pd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTDQ2PD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtdq2pd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTDQ2PD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtdq2pd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTDQ2PD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtdq2pd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTDQ2PD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtdq2pd_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTDQ2PD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2pdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtdq2pd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTDQ2PD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtdq2pdMaskzSaeEmitter<A, B> {
    fn vcvtdq2pd_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2pdMaskzSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtdq2pd_maskz_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTDQ2PD512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtdq2pdSaeEmitter<A, B> {
    fn vcvtdq2pd_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2pdSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtdq2pd_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTDQ2PD512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtdq2psEmitter<A, B> {
    fn vcvtdq2ps(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2psEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtdq2ps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTDQ2PS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtdq2ps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTDQ2PS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtdq2ps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTDQ2PS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtdq2ps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTDQ2PS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtdq2ps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTDQ2PS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtdq2ps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTDQ2PS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtdq2psErEmitter<A, B> {
    fn vcvtdq2ps_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2psErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtdq2ps_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTDQ2PS512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtdq2psMaskEmitter<A, B> {
    fn vcvtdq2ps_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2psMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtdq2ps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTDQ2PS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtdq2ps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTDQ2PS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtdq2ps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTDQ2PS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtdq2ps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTDQ2PS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtdq2ps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTDQ2PS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtdq2ps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTDQ2PS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtdq2psMaskErEmitter<A, B> {
    fn vcvtdq2ps_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2psMaskErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtdq2ps_mask_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTDQ2PS512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtdq2psMaskzEmitter<A, B> {
    fn vcvtdq2ps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2psMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtdq2ps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTDQ2PS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtdq2ps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTDQ2PS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtdq2ps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTDQ2PS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtdq2ps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTDQ2PS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtdq2ps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTDQ2PS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtdq2psMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtdq2ps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTDQ2PS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTDQ2PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtdq2psMaskzErEmitter<A, B> {
    fn vcvtdq2ps_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtdq2psMaskzErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtdq2ps_maskz_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTDQ2PS512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2DQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2dqEmitter<A, B> {
    fn vcvtpd2dq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2dqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2dq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2DQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2dq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2DQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2dq(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2DQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2dq(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2DQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2dq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2DQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2DQ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2dqErEmitter<A, B> {
    fn vcvtpd2dq_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2dqErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2dq_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2DQ512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2DQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2dqMaskEmitter<A, B> {
    fn vcvtpd2dq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2dqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2dq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2DQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2dq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2DQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2dq_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2DQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2dq_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2DQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2dq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2DQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2DQ_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2dqMaskErEmitter<A, B> {
    fn vcvtpd2dq_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2dqMaskErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2dq_mask_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2DQ512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2DQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2dqMaskzEmitter<A, B> {
    fn vcvtpd2dq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2dqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2dq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2DQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2dq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2DQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2dq_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2DQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2dq_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2DQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2dqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2dq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2DQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2DQ_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2dqMaskzErEmitter<A, B> {
    fn vcvtpd2dq_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2dqMaskzErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2dq_maskz_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2DQ512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2psEmitter<A, B> {
    fn vcvtpd2ps(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2psEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2ps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2PS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2ps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2PS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2ps(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2PS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2ps(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2PS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2ps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2PS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2psErEmitter<A, B> {
    fn vcvtpd2ps_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2psErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2ps_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2PS512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2psMaskEmitter<A, B> {
    fn vcvtpd2ps_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2psMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2ps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2PS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2ps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2PS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2ps_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2PS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2ps_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2PS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2ps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2PS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2psMaskErEmitter<A, B> {
    fn vcvtpd2ps_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2psMaskErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2ps_mask_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2PS512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2psMaskzEmitter<A, B> {
    fn vcvtpd2ps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2psMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2ps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2PS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2ps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2PS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2ps_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2PS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2ps_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2PS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2psMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2ps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2PS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2psMaskzErEmitter<A, B> {
    fn vcvtpd2ps_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2psMaskzErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2ps_maskz_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2PS512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2udqEmitter<A, B> {
    fn vcvtpd2udq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2udqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2udq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2UDQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2udq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2UDQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2udq(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2UDQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2udq(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2UDQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2udq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2UDQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UDQ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2udqErEmitter<A, B> {
    fn vcvtpd2udq_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2udqErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2udq_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2UDQ512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2udqMaskEmitter<A, B> {
    fn vcvtpd2udq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2udqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2udq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2UDQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2udq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2UDQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2udq_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2UDQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2udq_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2UDQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2udq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2UDQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UDQ_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2udqMaskErEmitter<A, B> {
    fn vcvtpd2udq_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2udqMaskErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2udq_mask_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2UDQ512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2udqMaskzEmitter<A, B> {
    fn vcvtpd2udq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2udqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2udq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2UDQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2udq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2UDQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtpd2udq_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTPD2UDQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2udq_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2UDQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2udqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2udq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2UDQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UDQ_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2udqMaskzErEmitter<A, B> {
    fn vcvtpd2udq_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2udqMaskzErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtpd2udq_maskz_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTPD2UDQ512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UQQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2uqqEmitter<A, B> {
    fn vcvtpd2uqq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2uqqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2uqq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2UQQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtpd2uqq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPD2UQQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtpd2uqq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPD2UQQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UQQ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2uqqErEmitter<A, B> {
    fn vcvtpd2uqq_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2uqqErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtpd2uqq_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPD2UQQ512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UQQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2uqqMaskEmitter<A, B> {
    fn vcvtpd2uqq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2uqqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2uqq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2UQQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtpd2uqq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPD2UQQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtpd2uqq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPD2UQQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UQQ_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2uqqMaskErEmitter<A, B> {
    fn vcvtpd2uqq_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2uqqMaskErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtpd2uqq_mask_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPD2UQQ512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UQQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2uqqMaskzEmitter<A, B> {
    fn vcvtpd2uqq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2uqqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtpd2uqq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPD2UQQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtpd2uqq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPD2UQQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtpd2uqq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPD2UQQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtpd2uqqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtpd2uqq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPD2UQQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPD2UQQ_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtpd2uqqMaskzErEmitter<A, B> {
    fn vcvtpd2uqq_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtpd2uqqMaskzErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtpd2uqq_maskz_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPD2UQQ512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPH2PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtph2psEmitter<A, B> {
    fn vcvtph2ps(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtph2psEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtph2ps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPH2PS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtph2ps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPH2PS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtph2ps(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPH2PS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtph2ps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPH2PS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtph2ps(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPH2PS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtph2ps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPH2PS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPH2PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtph2psMaskEmitter<A, B> {
    fn vcvtph2ps_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtph2psMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtph2ps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPH2PS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtph2ps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPH2PS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtph2ps_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPH2PS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtph2ps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPH2PS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtph2ps_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPH2PS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtph2ps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPH2PS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPH2PS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtph2psMaskSaeEmitter<A, B> {
    fn vcvtph2ps_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtph2psMaskSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtph2ps_mask_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPH2PS512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPH2PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtph2psMaskzEmitter<A, B> {
    fn vcvtph2ps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtph2psMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtph2ps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPH2PS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtph2ps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPH2PS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtph2ps_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPH2PS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtph2ps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPH2PS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtph2ps_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPH2PS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtph2psMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtph2ps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPH2PS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPH2PS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtph2psMaskzSaeEmitter<A, B> {
    fn vcvtph2ps_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtph2psMaskzSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtph2ps_maskz_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPH2PS512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPH2PS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtph2psSaeEmitter<A, B> {
    fn vcvtph2ps_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtph2psSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtph2ps_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPH2PS512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2DQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2dqEmitter<A, B> {
    fn vcvtps2dq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2dqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2dq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2DQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2dq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2DQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtps2dq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPS2DQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2dq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2DQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2dq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2DQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2dq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2DQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2DQ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2dqErEmitter<A, B> {
    fn vcvtps2dq_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2dqErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2dq_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2DQ512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2DQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2dqMaskEmitter<A, B> {
    fn vcvtps2dq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2dqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2dq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2DQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2dq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2DQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtps2dq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPS2DQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2dq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2DQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2dq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2DQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2dq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2DQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2DQ_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2dqMaskErEmitter<A, B> {
    fn vcvtps2dq_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2dqMaskErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2dq_mask_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2DQ512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2DQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2dqMaskzEmitter<A, B> {
    fn vcvtps2dq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2dqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2dq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2DQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2dq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2DQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtps2dq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPS2DQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2dq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2DQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2dq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2DQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2dqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2dq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2DQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2DQ_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2dqMaskzErEmitter<A, B> {
    fn vcvtps2dq_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2dqMaskzErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2dq_maskz_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2DQ512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2pdEmitter<A, B> {
    fn vcvtps2pd(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2pdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2pd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2PD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2pd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2PD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtps2pd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPS2PD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2pd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2PD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2pd(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2PD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2pd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2PD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2pdMaskEmitter<A, B> {
    fn vcvtps2pd_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2pdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2pd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2PD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2pd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2PD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtps2pd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPS2PD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2pd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2PD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2pd_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2PD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2pd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2PD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2PD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2pdMaskSaeEmitter<A, B> {
    fn vcvtps2pd_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2pdMaskSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2pd_mask_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2PD512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2pdMaskzEmitter<A, B> {
    fn vcvtps2pd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2pdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2pd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2PD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2pd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2PD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtps2pd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPS2PD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2pd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2PD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2pd_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2PD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2pdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2pd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2PD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2PD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2pdMaskzSaeEmitter<A, B> {
    fn vcvtps2pd_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2pdMaskzSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2pd_maskz_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2PD512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2PD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2pdSaeEmitter<A, B> {
    fn vcvtps2pd_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2pdSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2pd_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2PD512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2PH`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Xmm, Imm |
/// | 2 | Mem, Ymm, Imm |
/// | 3 | Mem, Zmm, Imm |
/// | 4 | Xmm, Xmm, Imm |
/// | 5 | Xmm, Ymm, Imm |
/// | 6 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vcvtps2phEmitter<A, B, C> {
    fn vcvtps2ph(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtps2phEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcvtps2ph(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VCVTPS2PH128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phEmitter<Mem, Xmm, Imm> for Assembler<'a> {
    fn vcvtps2ph(&mut self, op0: Mem, op1: Xmm, op2: Imm) {
        self.emit(
            VCVTPS2PH128MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vcvtps2ph(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VCVTPS2PH256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phEmitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vcvtps2ph(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VCVTPS2PH256MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vcvtps2ph(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VCVTPS2PH512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vcvtps2ph(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VCVTPS2PH512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTPS2PH_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Xmm, Imm |
/// | 2 | Mem, Ymm, Imm |
/// | 3 | Mem, Zmm, Imm |
/// | 4 | Xmm, Xmm, Imm |
/// | 5 | Xmm, Ymm, Imm |
/// | 6 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vcvtps2phMaskEmitter<A, B, C> {
    fn vcvtps2ph_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtps2phMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VCVTPS2PH128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phMaskEmitter<Mem, Xmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_mask(&mut self, op0: Mem, op1: Xmm, op2: Imm) {
        self.emit(
            VCVTPS2PH128MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phMaskEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vcvtps2ph_mask(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VCVTPS2PH256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phMaskEmitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vcvtps2ph_mask(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VCVTPS2PH256MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phMaskEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_mask(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VCVTPS2PH512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phMaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VCVTPS2PH512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTPS2PH_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vcvtps2phMaskSaeEmitter<A, B, C> {
    fn vcvtps2ph_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtps2phMaskSaeEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_mask_sae(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VCVTPS2PH512RRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTPS2PH_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Imm |
/// | 2 | Xmm, Ymm, Imm |
/// | 3 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vcvtps2phMaskzEmitter<A, B, C> {
    fn vcvtps2ph_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtps2phMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VCVTPS2PH128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phMaskzEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vcvtps2ph_maskz(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VCVTPS2PH256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2phMaskzEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_maskz(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VCVTPS2PH512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTPS2PH_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vcvtps2phMaskzSaeEmitter<A, B, C> {
    fn vcvtps2ph_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtps2phMaskzSaeEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_maskz_sae(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VCVTPS2PH512RRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTPS2PH_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vcvtps2phSaeEmitter<A, B, C> {
    fn vcvtps2ph_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtps2phSaeEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vcvtps2ph_sae(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VCVTPS2PH512RRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTPS2UDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2udqEmitter<A, B> {
    fn vcvtps2udq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2udqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2udq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2UDQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2udq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtps2udq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPS2UDQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2udq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2udq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2UDQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2udq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UDQ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2udqErEmitter<A, B> {
    fn vcvtps2udq_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2udqErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2udq_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2UDQ512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2udqMaskEmitter<A, B> {
    fn vcvtps2udq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2udqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2udq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2UDQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2udq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtps2udq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPS2UDQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2udq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2udq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2UDQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2udq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UDQ_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2udqMaskErEmitter<A, B> {
    fn vcvtps2udq_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2udqMaskErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2udq_mask_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2UDQ512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2udqMaskzEmitter<A, B> {
    fn vcvtps2udq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2udqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2udq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2UDQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2udq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtps2udq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTPS2UDQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2udq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2udq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2UDQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2udqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2udq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2UDQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UDQ_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtps2udqMaskzErEmitter<A, B> {
    fn vcvtps2udq_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2udqMaskzErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtps2udq_maskz_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTPS2UDQ512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UQQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2uqqEmitter<A, B> {
    fn vcvtps2uqq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2uqqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2uqq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2UQQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2uqq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtps2uqq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPS2UQQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2uqq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2uqq(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2UQQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2uqq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UQQ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2uqqErEmitter<A, B> {
    fn vcvtps2uqq_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2uqqErEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2uqq_er(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2UQQ512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UQQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2uqqMaskEmitter<A, B> {
    fn vcvtps2uqq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2uqqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2uqq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2UQQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2uqq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtps2uqq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPS2UQQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2uqq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2uqq_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2UQQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2uqq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UQQ_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2uqqMaskErEmitter<A, B> {
    fn vcvtps2uqq_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2uqqMaskErEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2uqq_mask_er(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2UQQ512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UQQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2uqqMaskzEmitter<A, B> {
    fn vcvtps2uqq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2uqqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtps2uqq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTPS2UQQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtps2uqq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtps2uqq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTPS2UQQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtps2uqq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2uqq_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2UQQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtps2uqqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtps2uqq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTPS2UQQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTPS2UQQ_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtps2uqqMaskzErEmitter<A, B> {
    fn vcvtps2uqq_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtps2uqqMaskzErEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtps2uqq_maskz_er(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTPS2UQQ512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTSD2SI`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Mem |
/// | 2 | Gpd, Xmm |
/// | 3 | Gpq, Mem |
/// | 4 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvtsd2siEmitter<A, B> {
    fn vcvtsd2si(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtsd2siEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvtsd2si(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTSD2SI32RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2siEmitter<Gpd, Mem> for Assembler<'a> {
    fn vcvtsd2si(&mut self, op0: Gpd, op1: Mem) {
        self.emit(
            VCVTSD2SI32RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2siEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvtsd2si(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTSD2SI64RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2siEmitter<Gpq, Mem> for Assembler<'a> {
    fn vcvtsd2si(&mut self, op0: Gpq, op1: Mem) {
        self.emit(
            VCVTSD2SI64RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTSD2SI_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Xmm |
/// | 2 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvtsd2siErEmitter<A, B> {
    fn vcvtsd2si_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtsd2siErEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvtsd2si_er(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTSD2SI32RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2siErEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvtsd2si_er(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTSD2SI64RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTSD2SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtsd2ssEmitter<A, B, C> {
    fn vcvtsd2ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsd2ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtsd2ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSD2SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtsd2ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTSD2SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSD2SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtsd2ssErEmitter<A, B, C> {
    fn vcvtsd2ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsd2ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtsd2ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSD2SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSD2SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtsd2ssMaskEmitter<A, B, C> {
    fn vcvtsd2ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsd2ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtsd2ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSD2SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtsd2ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTSD2SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSD2SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtsd2ssMaskErEmitter<A, B, C> {
    fn vcvtsd2ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsd2ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtsd2ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSD2SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSD2SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtsd2ssMaskzEmitter<A, B, C> {
    fn vcvtsd2ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsd2ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtsd2ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSD2SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtsd2ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTSD2SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSD2SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtsd2ssMaskzErEmitter<A, B, C> {
    fn vcvtsd2ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsd2ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtsd2ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSD2SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSD2USI`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Mem |
/// | 2 | Gpd, Xmm |
/// | 3 | Gpq, Mem |
/// | 4 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvtsd2usiEmitter<A, B> {
    fn vcvtsd2usi(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtsd2usiEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvtsd2usi(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTSD2USI32RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2usiEmitter<Gpd, Mem> for Assembler<'a> {
    fn vcvtsd2usi(&mut self, op0: Gpd, op1: Mem) {
        self.emit(
            VCVTSD2USI32RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2usiEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvtsd2usi(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTSD2USI64RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2usiEmitter<Gpq, Mem> for Assembler<'a> {
    fn vcvtsd2usi(&mut self, op0: Gpq, op1: Mem) {
        self.emit(
            VCVTSD2USI64RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTSD2USI_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Xmm |
/// | 2 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvtsd2usiErEmitter<A, B> {
    fn vcvtsd2usi_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtsd2usiErEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvtsd2usi_er(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTSD2USI32RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtsd2usiErEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvtsd2usi_er(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTSD2USI64RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTSI2SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Gpd |
/// | 2 | Xmm, Xmm, Gpq |
/// | 3 | Xmm, Xmm, Mem |
/// +---+---------------+
/// ```
pub trait Vcvtsi2sdEmitter<A, B, C> {
    fn vcvtsi2sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsi2sdEmitter<Xmm, Xmm, Gpd> for Assembler<'a> {
    fn vcvtsi2sd(&mut self, op0: Xmm, op1: Xmm, op2: Gpd) {
        self.emit(
            VCVTSI2SD32RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsi2sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtsi2sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTSI2SD32RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsi2sdEmitter<Xmm, Xmm, Gpq> for Assembler<'a> {
    fn vcvtsi2sd(&mut self, op0: Xmm, op1: Xmm, op2: Gpq) {
        self.emit(
            VCVTSI2SD64RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSI2SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Gpd |
/// | 2 | Xmm, Xmm, Gpq |
/// +---+---------------+
/// ```
pub trait Vcvtsi2sdErEmitter<A, B, C> {
    fn vcvtsi2sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsi2sdErEmitter<Xmm, Xmm, Gpd> for Assembler<'a> {
    fn vcvtsi2sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Gpd) {
        self.emit(
            VCVTSI2SD32RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsi2sdErEmitter<Xmm, Xmm, Gpq> for Assembler<'a> {
    fn vcvtsi2sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Gpq) {
        self.emit(
            VCVTSI2SD64RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSI2SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Gpd |
/// | 2 | Xmm, Xmm, Gpq |
/// | 3 | Xmm, Xmm, Mem |
/// +---+---------------+
/// ```
pub trait Vcvtsi2ssEmitter<A, B, C> {
    fn vcvtsi2ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsi2ssEmitter<Xmm, Xmm, Gpd> for Assembler<'a> {
    fn vcvtsi2ss(&mut self, op0: Xmm, op1: Xmm, op2: Gpd) {
        self.emit(
            VCVTSI2SS32RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsi2ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtsi2ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTSI2SS32RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsi2ssEmitter<Xmm, Xmm, Gpq> for Assembler<'a> {
    fn vcvtsi2ss(&mut self, op0: Xmm, op1: Xmm, op2: Gpq) {
        self.emit(
            VCVTSI2SS64RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSI2SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Gpd |
/// | 2 | Xmm, Xmm, Gpq |
/// +---+---------------+
/// ```
pub trait Vcvtsi2ssErEmitter<A, B, C> {
    fn vcvtsi2ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtsi2ssErEmitter<Xmm, Xmm, Gpd> for Assembler<'a> {
    fn vcvtsi2ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Gpd) {
        self.emit(
            VCVTSI2SS32RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtsi2ssErEmitter<Xmm, Xmm, Gpq> for Assembler<'a> {
    fn vcvtsi2ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Gpq) {
        self.emit(
            VCVTSI2SS64RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSS2SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtss2sdEmitter<A, B, C> {
    fn vcvtss2sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtss2sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtss2sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSS2SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtss2sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTSS2SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSS2SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtss2sdMaskEmitter<A, B, C> {
    fn vcvtss2sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtss2sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtss2sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSS2SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtss2sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTSS2SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSS2SD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtss2sdMaskSaeEmitter<A, B, C> {
    fn vcvtss2sd_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtss2sdMaskSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtss2sd_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSS2SDRRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSS2SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtss2sdMaskzEmitter<A, B, C> {
    fn vcvtss2sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtss2sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtss2sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSS2SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtss2sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTSS2SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSS2SD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtss2sdMaskzSaeEmitter<A, B, C> {
    fn vcvtss2sd_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtss2sdMaskzSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtss2sd_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSS2SDRRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSS2SD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vcvtss2sdSaeEmitter<A, B, C> {
    fn vcvtss2sd_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtss2sdSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vcvtss2sd_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VCVTSS2SDRRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTSS2SI`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Mem |
/// | 2 | Gpd, Xmm |
/// | 3 | Gpq, Mem |
/// | 4 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvtss2siEmitter<A, B> {
    fn vcvtss2si(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtss2siEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvtss2si(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTSS2SI32RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2siEmitter<Gpd, Mem> for Assembler<'a> {
    fn vcvtss2si(&mut self, op0: Gpd, op1: Mem) {
        self.emit(
            VCVTSS2SI32RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2siEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvtss2si(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTSS2SI64RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2siEmitter<Gpq, Mem> for Assembler<'a> {
    fn vcvtss2si(&mut self, op0: Gpq, op1: Mem) {
        self.emit(
            VCVTSS2SI64RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTSS2SI_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Xmm |
/// | 2 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvtss2siErEmitter<A, B> {
    fn vcvtss2si_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtss2siErEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvtss2si_er(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTSS2SI32RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2siErEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvtss2si_er(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTSS2SI64RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTSS2USI`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Mem |
/// | 2 | Gpd, Xmm |
/// | 3 | Gpq, Mem |
/// | 4 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvtss2usiEmitter<A, B> {
    fn vcvtss2usi(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtss2usiEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvtss2usi(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTSS2USI32RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2usiEmitter<Gpd, Mem> for Assembler<'a> {
    fn vcvtss2usi(&mut self, op0: Gpd, op1: Mem) {
        self.emit(
            VCVTSS2USI32RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2usiEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvtss2usi(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTSS2USI64RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2usiEmitter<Gpq, Mem> for Assembler<'a> {
    fn vcvtss2usi(&mut self, op0: Gpq, op1: Mem) {
        self.emit(
            VCVTSS2USI64RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTSS2USI_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Xmm |
/// | 2 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvtss2usiErEmitter<A, B> {
    fn vcvtss2usi_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtss2usiErEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvtss2usi_er(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTSS2USI32RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtss2usiErEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvtss2usi_er(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTSS2USI64RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2DQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2dqEmitter<A, B> {
    fn vcvttpd2dq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2dqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2dq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2DQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2dq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2DQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvttpd2dq(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTTPD2DQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2dq(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2DQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2dq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2DQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2DQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2dqMaskEmitter<A, B> {
    fn vcvttpd2dq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2dqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2dq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2DQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2dq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2DQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvttpd2dq_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTTPD2DQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2dq_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2DQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2dq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2DQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2DQ_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2dqMaskSaeEmitter<A, B> {
    fn vcvttpd2dq_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2dqMaskSaeEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2dq_mask_sae(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2DQ512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2DQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2dqMaskzEmitter<A, B> {
    fn vcvttpd2dq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2dqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2dq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2DQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2dq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2DQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvttpd2dq_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTTPD2DQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2dq_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2DQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2dqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2dq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2DQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2DQ_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2dqMaskzSaeEmitter<A, B> {
    fn vcvttpd2dq_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2dqMaskzSaeEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2dq_maskz_sae(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2DQ512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2DQ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2dqSaeEmitter<A, B> {
    fn vcvttpd2dq_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2dqSaeEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2dq_sae(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2DQ512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2udqEmitter<A, B> {
    fn vcvttpd2udq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2udqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2udq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2UDQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2udq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2UDQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvttpd2udq(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTTPD2UDQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2udq(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2UDQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2udq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2UDQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2udqMaskEmitter<A, B> {
    fn vcvttpd2udq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2udqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2udq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2UDQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2udq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2UDQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvttpd2udq_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTTPD2UDQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2udq_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2UDQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2udq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2UDQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UDQ_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2udqMaskSaeEmitter<A, B> {
    fn vcvttpd2udq_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2udqMaskSaeEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2udq_mask_sae(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2UDQ512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2udqMaskzEmitter<A, B> {
    fn vcvttpd2udq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2udqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2udq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2UDQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2udq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2UDQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvttpd2udq_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTTPD2UDQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2udq_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2UDQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2udqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2udq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2UDQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UDQ_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2udqMaskzSaeEmitter<A, B> {
    fn vcvttpd2udq_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2udqMaskzSaeEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2udq_maskz_sae(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2UDQ512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UDQ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2udqSaeEmitter<A, B> {
    fn vcvttpd2udq_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2udqSaeEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvttpd2udq_sae(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTTPD2UDQ512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UQQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2uqqEmitter<A, B> {
    fn vcvttpd2uqq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2uqqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2uqq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2UQQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttpd2uqq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPD2UQQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttpd2uqq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPD2UQQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UQQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2uqqMaskEmitter<A, B> {
    fn vcvttpd2uqq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2uqqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2uqq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2UQQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttpd2uqq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPD2UQQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttpd2uqq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPD2UQQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UQQ_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2uqqMaskSaeEmitter<A, B> {
    fn vcvttpd2uqq_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2uqqMaskSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttpd2uqq_mask_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPD2UQQ512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UQQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2uqqMaskzEmitter<A, B> {
    fn vcvttpd2uqq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2uqqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttpd2uqq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPD2UQQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttpd2uqq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPD2UQQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttpd2uqq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPD2UQQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttpd2uqqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttpd2uqq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPD2UQQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UQQ_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2uqqMaskzSaeEmitter<A, B> {
    fn vcvttpd2uqq_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2uqqMaskzSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttpd2uqq_maskz_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPD2UQQ512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPD2UQQ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttpd2uqqSaeEmitter<A, B> {
    fn vcvttpd2uqq_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttpd2uqqSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttpd2uqq_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPD2UQQ512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2DQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2dqEmitter<A, B> {
    fn vcvttps2dq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2dqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2dq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2DQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2dq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttps2dq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPS2DQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2dq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2dq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2DQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2dq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2DQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2dqMaskEmitter<A, B> {
    fn vcvttps2dq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2dqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2dq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2DQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2dq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttps2dq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPS2DQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2dq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2dq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2DQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2dq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2DQ_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2dqMaskSaeEmitter<A, B> {
    fn vcvttps2dq_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2dqMaskSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2dq_mask_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2DQ512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2DQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2dqMaskzEmitter<A, B> {
    fn vcvttps2dq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2dqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2dq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2DQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2dq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttps2dq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPS2DQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2dq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2dq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2DQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2dqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2dq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2DQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2DQ_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2dqMaskzSaeEmitter<A, B> {
    fn vcvttps2dq_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2dqMaskzSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2dq_maskz_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2DQ512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2DQ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2dqSaeEmitter<A, B> {
    fn vcvttps2dq_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2dqSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2dq_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2DQ512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2udqEmitter<A, B> {
    fn vcvttps2udq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2udqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2udq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2UDQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2udq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttps2udq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPS2UDQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2udq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2udq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2UDQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2udq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2udqMaskEmitter<A, B> {
    fn vcvttps2udq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2udqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2udq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2UDQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2udq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttps2udq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPS2UDQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2udq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2udq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2UDQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2udq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UDQ_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2udqMaskSaeEmitter<A, B> {
    fn vcvttps2udq_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2udqMaskSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2udq_mask_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2UDQ512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2udqMaskzEmitter<A, B> {
    fn vcvttps2udq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2udqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2udq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2UDQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2udq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvttps2udq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTTPS2UDQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2udq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2udq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2UDQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2udqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2udq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2UDQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UDQ_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2udqMaskzSaeEmitter<A, B> {
    fn vcvttps2udq_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2udqMaskzSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2udq_maskz_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2UDQ512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UDQ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvttps2udqSaeEmitter<A, B> {
    fn vcvttps2udq_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2udqSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvttps2udq_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTTPS2UDQ512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UQQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvttps2uqqEmitter<A, B> {
    fn vcvttps2uqq(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2uqqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2uqq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2UQQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2uqq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvttps2uqq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTTPS2UQQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2uqq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvttps2uqq(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTTPS2UQQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2uqq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UQQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvttps2uqqMaskEmitter<A, B> {
    fn vcvttps2uqq_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2uqqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2uqq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2UQQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2uqq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvttps2uqq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTTPS2UQQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2uqq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvttps2uqq_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTTPS2UQQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2uqq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UQQ_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvttps2uqqMaskSaeEmitter<A, B> {
    fn vcvttps2uqq_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2uqqMaskSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvttps2uqq_mask_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTTPS2UQQ512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UQQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvttps2uqqMaskzEmitter<A, B> {
    fn vcvttps2uqq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2uqqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvttps2uqq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTTPS2UQQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvttps2uqq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvttps2uqq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTTPS2UQQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvttps2uqq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvttps2uqq_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTTPS2UQQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttps2uqqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvttps2uqq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTTPS2UQQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UQQ_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvttps2uqqMaskzSaeEmitter<A, B> {
    fn vcvttps2uqq_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2uqqMaskzSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvttps2uqq_maskz_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTTPS2UQQ512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTPS2UQQ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvttps2uqqSaeEmitter<A, B> {
    fn vcvttps2uqq_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttps2uqqSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvttps2uqq_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTTPS2UQQ512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTSD2SI`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Mem |
/// | 2 | Gpd, Xmm |
/// | 3 | Gpq, Mem |
/// | 4 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvttsd2siEmitter<A, B> {
    fn vcvttsd2si(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttsd2siEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvttsd2si(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTTSD2SI32RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttsd2siEmitter<Gpd, Mem> for Assembler<'a> {
    fn vcvttsd2si(&mut self, op0: Gpd, op1: Mem) {
        self.emit(
            VCVTTSD2SI32RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttsd2siEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvttsd2si(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTTSD2SI64RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttsd2siEmitter<Gpq, Mem> for Assembler<'a> {
    fn vcvttsd2si(&mut self, op0: Gpq, op1: Mem) {
        self.emit(
            VCVTTSD2SI64RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTSD2SI_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Xmm |
/// | 2 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvttsd2siSaeEmitter<A, B> {
    fn vcvttsd2si_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttsd2siSaeEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvttsd2si_sae(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTTSD2SI32RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttsd2siSaeEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvttsd2si_sae(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTTSD2SI64RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTSD2USI`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Mem |
/// | 2 | Gpd, Xmm |
/// | 3 | Gpq, Mem |
/// | 4 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvttsd2usiEmitter<A, B> {
    fn vcvttsd2usi(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttsd2usiEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvttsd2usi(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTTSD2USI32RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttsd2usiEmitter<Gpd, Mem> for Assembler<'a> {
    fn vcvttsd2usi(&mut self, op0: Gpd, op1: Mem) {
        self.emit(
            VCVTTSD2USI32RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttsd2usiEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvttsd2usi(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTTSD2USI64RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttsd2usiEmitter<Gpq, Mem> for Assembler<'a> {
    fn vcvttsd2usi(&mut self, op0: Gpq, op1: Mem) {
        self.emit(
            VCVTTSD2USI64RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTSD2USI_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Xmm |
/// | 2 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvttsd2usiSaeEmitter<A, B> {
    fn vcvttsd2usi_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttsd2usiSaeEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvttsd2usi_sae(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTTSD2USI32RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttsd2usiSaeEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvttsd2usi_sae(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTTSD2USI64RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTSS2SI`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Mem |
/// | 2 | Gpd, Xmm |
/// | 3 | Gpq, Mem |
/// | 4 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvttss2siEmitter<A, B> {
    fn vcvttss2si(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttss2siEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvttss2si(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTTSS2SI32RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttss2siEmitter<Gpd, Mem> for Assembler<'a> {
    fn vcvttss2si(&mut self, op0: Gpd, op1: Mem) {
        self.emit(
            VCVTTSS2SI32RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttss2siEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvttss2si(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTTSS2SI64RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttss2siEmitter<Gpq, Mem> for Assembler<'a> {
    fn vcvttss2si(&mut self, op0: Gpq, op1: Mem) {
        self.emit(
            VCVTTSS2SI64RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTSS2SI_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Xmm |
/// | 2 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvttss2siSaeEmitter<A, B> {
    fn vcvttss2si_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttss2siSaeEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvttss2si_sae(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTTSS2SI32RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttss2siSaeEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvttss2si_sae(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTTSS2SI64RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTSS2USI`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Mem |
/// | 2 | Gpd, Xmm |
/// | 3 | Gpq, Mem |
/// | 4 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvttss2usiEmitter<A, B> {
    fn vcvttss2usi(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttss2usiEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvttss2usi(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTTSS2USI32RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttss2usiEmitter<Gpd, Mem> for Assembler<'a> {
    fn vcvttss2usi(&mut self, op0: Gpd, op1: Mem) {
        self.emit(
            VCVTTSS2USI32RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttss2usiEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvttss2usi(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTTSS2USI64RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttss2usiEmitter<Gpq, Mem> for Assembler<'a> {
    fn vcvttss2usi(&mut self, op0: Gpq, op1: Mem) {
        self.emit(
            VCVTTSS2USI64RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTTSS2USI_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Gpd, Xmm |
/// | 2 | Gpq, Xmm |
/// +---+----------+
/// ```
pub trait Vcvttss2usiSaeEmitter<A, B> {
    fn vcvttss2usi_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvttss2usiSaeEmitter<Gpd, Xmm> for Assembler<'a> {
    fn vcvttss2usi_sae(&mut self, op0: Gpd, op1: Xmm) {
        self.emit(
            VCVTTSS2USI32RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvttss2usiSaeEmitter<Gpq, Xmm> for Assembler<'a> {
    fn vcvttss2usi_sae(&mut self, op0: Gpq, op1: Xmm) {
        self.emit(
            VCVTTSS2USI64RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtudq2pdEmitter<A, B> {
    fn vcvtudq2pd(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2pdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtudq2pd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtudq2pd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtudq2pd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtudq2pd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtudq2pd(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtudq2pd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtudq2pdMaskEmitter<A, B> {
    fn vcvtudq2pd_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2pdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtudq2pd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtudq2pd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtudq2pd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtudq2pd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtudq2pd_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtudq2pd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtudq2pdMaskSaeEmitter<A, B> {
    fn vcvtudq2pd_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2pdMaskSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtudq2pd_mask_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PD512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtudq2pdMaskzEmitter<A, B> {
    fn vcvtudq2pd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2pdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtudq2pd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtudq2pd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vcvtudq2pd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtudq2pd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtudq2pd_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2pdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtudq2pd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtudq2pdMaskzSaeEmitter<A, B> {
    fn vcvtudq2pd_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2pdMaskzSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtudq2pd_maskz_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PD512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait Vcvtudq2pdSaeEmitter<A, B> {
    fn vcvtudq2pd_sae(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2pdSaeEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vcvtudq2pd_sae(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PD512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtudq2psEmitter<A, B> {
    fn vcvtudq2ps(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2psEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtudq2ps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtudq2ps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtudq2ps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtudq2ps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtudq2ps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUDQ2PS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtudq2ps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtudq2psErEmitter<A, B> {
    fn vcvtudq2ps_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2psErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtudq2ps_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUDQ2PS512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtudq2psMaskEmitter<A, B> {
    fn vcvtudq2ps_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2psMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtudq2ps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtudq2ps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtudq2ps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtudq2ps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtudq2ps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUDQ2PS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtudq2ps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtudq2psMaskErEmitter<A, B> {
    fn vcvtudq2ps_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2psMaskErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtudq2ps_mask_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUDQ2PS512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtudq2psMaskzEmitter<A, B> {
    fn vcvtudq2ps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2psMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtudq2ps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUDQ2PS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtudq2ps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtudq2ps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTUDQ2PS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtudq2ps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtudq2ps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUDQ2PS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtudq2psMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtudq2ps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUDQ2PS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUDQ2PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtudq2psMaskzErEmitter<A, B> {
    fn vcvtudq2ps_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtudq2psMaskzErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtudq2ps_maskz_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUDQ2PS512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2pdEmitter<A, B> {
    fn vcvtuqq2pd(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2pdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtuqq2pd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUQQ2PD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtuqq2pd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTUQQ2PD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtuqq2pd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2pdErEmitter<A, B> {
    fn vcvtuqq2pd_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2pdErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtuqq2pd_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PD512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2pdMaskEmitter<A, B> {
    fn vcvtuqq2pd_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2pdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtuqq2pd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUQQ2PD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtuqq2pd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTUQQ2PD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtuqq2pd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2pdMaskErEmitter<A, B> {
    fn vcvtuqq2pd_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2pdMaskErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtuqq2pd_mask_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PD512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2pdMaskzEmitter<A, B> {
    fn vcvtuqq2pd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2pdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtuqq2pd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUQQ2PD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vcvtuqq2pd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VCVTUQQ2PD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtuqq2pd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2pdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vcvtuqq2pd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2pdMaskzErEmitter<A, B> {
    fn vcvtuqq2pd_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2pdMaskzErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vcvtuqq2pd_maskz_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PD512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2psEmitter<A, B> {
    fn vcvtuqq2ps(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2psEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtuqq2ps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUQQ2PS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtuqq2ps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtuqq2ps(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTUQQ2PS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtuqq2ps(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtuqq2ps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUQQ2PS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2psErEmitter<A, B> {
    fn vcvtuqq2ps_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2psErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtuqq2ps_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PS512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2psMaskEmitter<A, B> {
    fn vcvtuqq2ps_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2psMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtuqq2ps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUQQ2PS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtuqq2ps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtuqq2ps_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTUQQ2PS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtuqq2ps_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtuqq2ps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUQQ2PS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2psMaskErEmitter<A, B> {
    fn vcvtuqq2ps_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2psMaskErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtuqq2ps_mask_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PS512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Xmm, Ymm |
/// | 4 | Ymm, Mem |
/// | 5 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2psMaskzEmitter<A, B> {
    fn vcvtuqq2ps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2psMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vcvtuqq2ps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VCVTUQQ2PS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vcvtuqq2ps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VCVTUQQ2PS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vcvtuqq2ps_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VCVTUQQ2PS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtuqq2ps_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vcvtuqq2psMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vcvtuqq2ps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VCVTUQQ2PS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUQQ2PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait Vcvtuqq2psMaskzErEmitter<A, B> {
    fn vcvtuqq2ps_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> Vcvtuqq2psMaskzErEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vcvtuqq2ps_maskz_er(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VCVTUQQ2PS512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VCVTUSI2SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Gpd |
/// | 2 | Xmm, Xmm, Gpq |
/// | 3 | Xmm, Xmm, Mem |
/// +---+---------------+
/// ```
pub trait Vcvtusi2sdEmitter<A, B, C> {
    fn vcvtusi2sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtusi2sdEmitter<Xmm, Xmm, Gpd> for Assembler<'a> {
    fn vcvtusi2sd(&mut self, op0: Xmm, op1: Xmm, op2: Gpd) {
        self.emit(
            VCVTUSI2SD32RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtusi2sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtusi2sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTUSI2SD32RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtusi2sdEmitter<Xmm, Xmm, Gpq> for Assembler<'a> {
    fn vcvtusi2sd(&mut self, op0: Xmm, op1: Xmm, op2: Gpq) {
        self.emit(
            VCVTUSI2SD64RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTUSI2SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Gpd |
/// | 2 | Xmm, Xmm, Gpq |
/// +---+---------------+
/// ```
pub trait Vcvtusi2sdErEmitter<A, B, C> {
    fn vcvtusi2sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtusi2sdErEmitter<Xmm, Xmm, Gpd> for Assembler<'a> {
    fn vcvtusi2sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Gpd) {
        self.emit(
            VCVTUSI2SD32RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtusi2sdErEmitter<Xmm, Xmm, Gpq> for Assembler<'a> {
    fn vcvtusi2sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Gpq) {
        self.emit(
            VCVTUSI2SD64RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTUSI2SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Gpd |
/// | 2 | Xmm, Xmm, Gpq |
/// | 3 | Xmm, Xmm, Mem |
/// +---+---------------+
/// ```
pub trait Vcvtusi2ssEmitter<A, B, C> {
    fn vcvtusi2ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtusi2ssEmitter<Xmm, Xmm, Gpd> for Assembler<'a> {
    fn vcvtusi2ss(&mut self, op0: Xmm, op1: Xmm, op2: Gpd) {
        self.emit(
            VCVTUSI2SS32RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtusi2ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vcvtusi2ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VCVTUSI2SS32RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtusi2ssEmitter<Xmm, Xmm, Gpq> for Assembler<'a> {
    fn vcvtusi2ss(&mut self, op0: Xmm, op1: Xmm, op2: Gpq) {
        self.emit(
            VCVTUSI2SS64RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VCVTUSI2SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Gpd |
/// | 2 | Xmm, Xmm, Gpq |
/// +---+---------------+
/// ```
pub trait Vcvtusi2ssErEmitter<A, B, C> {
    fn vcvtusi2ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vcvtusi2ssErEmitter<Xmm, Xmm, Gpd> for Assembler<'a> {
    fn vcvtusi2ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Gpd) {
        self.emit(
            VCVTUSI2SS32RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vcvtusi2ssErEmitter<Xmm, Xmm, Gpq> for Assembler<'a> {
    fn vcvtusi2ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Gpq) {
        self.emit(
            VCVTUSI2SS64RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpdEmitter<A, B, C> {
    fn vdivpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vdivpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VDIVPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vdivpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VDIVPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vdivpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VDIVPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpdErEmitter<A, B, C> {
    fn vdivpd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivpd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpdMaskEmitter<A, B, C> {
    fn vdivpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vdivpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VDIVPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vdivpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VDIVPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vdivpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VDIVPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpdMaskErEmitter<A, B, C> {
    fn vdivpd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivpd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpdMaskzEmitter<A, B, C> {
    fn vdivpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vdivpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VDIVPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vdivpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VDIVPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vdivpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VDIVPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpdMaskzErEmitter<A, B, C> {
    fn vdivpd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivpd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpsEmitter<A, B, C> {
    fn vdivps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vdivps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VDIVPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vdivps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VDIVPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vdivps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VDIVPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpsErEmitter<A, B, C> {
    fn vdivps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpsErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpsMaskEmitter<A, B, C> {
    fn vdivps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vdivps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VDIVPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vdivps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VDIVPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vdivps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VDIVPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpsMaskErEmitter<A, B, C> {
    fn vdivps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpsMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpsMaskzEmitter<A, B, C> {
    fn vdivps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vdivps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VDIVPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vdivps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VDIVPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vdivps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VDIVPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVPS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VdivpsMaskzErEmitter<A, B, C> {
    fn vdivps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivpsMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vdivps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VDIVPS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivsdEmitter<A, B, C> {
    fn vdivsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivsdErEmitter<A, B, C> {
    fn vdivsd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivsdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivsd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivsdMaskEmitter<A, B, C> {
    fn vdivsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivsdMaskErEmitter<A, B, C> {
    fn vdivsd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivsdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivsd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivsdMaskzEmitter<A, B, C> {
    fn vdivsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivsdMaskzErEmitter<A, B, C> {
    fn vdivsd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivsdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivsd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivssEmitter<A, B, C> {
    fn vdivss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivssErEmitter<A, B, C> {
    fn vdivss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivssMaskEmitter<A, B, C> {
    fn vdivss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivssMaskErEmitter<A, B, C> {
    fn vdivss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivssMaskzEmitter<A, B, C> {
    fn vdivss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VdivssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vdivss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VDIVSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VDIVSS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VdivssMaskzErEmitter<A, B, C> {
    fn vdivss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VdivssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vdivss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VDIVSSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXPANDPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VexpandpdEmitter<A, B> {
    fn vexpandpd(&mut self, op0: A, op1: B);
}

impl<'a> VexpandpdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vexpandpd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VEXPANDPD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vexpandpd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VEXPANDPD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vexpandpd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VEXPANDPD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vexpandpd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VEXPANDPD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vexpandpd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VEXPANDPD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vexpandpd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VEXPANDPD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VEXPANDPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VexpandpdMaskEmitter<A, B> {
    fn vexpandpd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VexpandpdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vexpandpd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VEXPANDPD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vexpandpd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VEXPANDPD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vexpandpd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VEXPANDPD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vexpandpd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VEXPANDPD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vexpandpd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VEXPANDPD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vexpandpd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VEXPANDPD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VEXPANDPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VexpandpdMaskzEmitter<A, B> {
    fn vexpandpd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VexpandpdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vexpandpd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VEXPANDPD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vexpandpd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VEXPANDPD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vexpandpd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VEXPANDPD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vexpandpd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VEXPANDPD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vexpandpd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VEXPANDPD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vexpandpd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VEXPANDPD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VEXPANDPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VexpandpsEmitter<A, B> {
    fn vexpandps(&mut self, op0: A, op1: B);
}

impl<'a> VexpandpsEmitter<Xmm, Mem> for Assembler<'a> {
    fn vexpandps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VEXPANDPS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsEmitter<Ymm, Mem> for Assembler<'a> {
    fn vexpandps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VEXPANDPS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsEmitter<Zmm, Mem> for Assembler<'a> {
    fn vexpandps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VEXPANDPS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vexpandps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VEXPANDPS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vexpandps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VEXPANDPS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vexpandps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VEXPANDPS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VEXPANDPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VexpandpsMaskEmitter<A, B> {
    fn vexpandps_mask(&mut self, op0: A, op1: B);
}

impl<'a> VexpandpsMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vexpandps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VEXPANDPS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vexpandps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VEXPANDPS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vexpandps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VEXPANDPS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vexpandps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VEXPANDPS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vexpandps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VEXPANDPS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vexpandps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VEXPANDPS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VEXPANDPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VexpandpsMaskzEmitter<A, B> {
    fn vexpandps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VexpandpsMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vexpandps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VEXPANDPS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vexpandps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VEXPANDPS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vexpandps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VEXPANDPS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vexpandps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VEXPANDPS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vexpandps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VEXPANDPS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VexpandpsMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vexpandps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VEXPANDPS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VEXTRACTF32X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Ymm, Imm |
/// | 2 | Mem, Zmm, Imm |
/// | 3 | Xmm, Ymm, Imm |
/// | 4 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf32x4Emitter<A, B, C> {
    fn vextractf32x4(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf32x4Emitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextractf32x4(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x4Emitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vextractf32x4(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_256MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x4Emitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x4(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x4Emitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x4(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF32X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Ymm, Imm |
/// | 2 | Mem, Zmm, Imm |
/// | 3 | Xmm, Ymm, Imm |
/// | 4 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf32x4MaskEmitter<A, B, C> {
    fn vextractf32x4_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf32x4MaskEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextractf32x4_mask(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x4MaskEmitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vextractf32x4_mask(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_256MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x4MaskEmitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x4_mask(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x4MaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x4_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF32X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Ymm, Imm |
/// | 2 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf32x4MaskzEmitter<A, B, C> {
    fn vextractf32x4_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf32x4MaskzEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextractf32x4_maskz(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x4MaskzEmitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x4_maskz(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X4_512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF32X8`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Zmm, Imm |
/// | 2 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf32x8Emitter<A, B, C> {
    fn vextractf32x8(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf32x8Emitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x8(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X8_512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x8Emitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x8(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X8_512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF32X8_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Zmm, Imm |
/// | 2 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf32x8MaskEmitter<A, B, C> {
    fn vextractf32x8_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf32x8MaskEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x8_mask(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X8_512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf32x8MaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x8_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X8_512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF32X8_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf32x8MaskzEmitter<A, B, C> {
    fn vextractf32x8_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf32x8MaskzEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextractf32x8_maskz(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF32X8_512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF64X2`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Ymm, Imm |
/// | 2 | Mem, Zmm, Imm |
/// | 3 | Xmm, Ymm, Imm |
/// | 4 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf64x2Emitter<A, B, C> {
    fn vextractf64x2(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf64x2Emitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextractf64x2(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x2Emitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vextractf64x2(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_256MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x2Emitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x2(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x2Emitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x2(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF64X2_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Ymm, Imm |
/// | 2 | Mem, Zmm, Imm |
/// | 3 | Xmm, Ymm, Imm |
/// | 4 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf64x2MaskEmitter<A, B, C> {
    fn vextractf64x2_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf64x2MaskEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextractf64x2_mask(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x2MaskEmitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vextractf64x2_mask(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_256MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x2MaskEmitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x2_mask(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x2MaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x2_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF64X2_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Ymm, Imm |
/// | 2 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf64x2MaskzEmitter<A, B, C> {
    fn vextractf64x2_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf64x2MaskzEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextractf64x2_maskz(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x2MaskzEmitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x2_maskz(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X2_512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF64X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Zmm, Imm |
/// | 2 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf64x4Emitter<A, B, C> {
    fn vextractf64x4(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf64x4Emitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x4(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X4_512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x4Emitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x4(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X4_512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF64X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Zmm, Imm |
/// | 2 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf64x4MaskEmitter<A, B, C> {
    fn vextractf64x4_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf64x4MaskEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x4_mask(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X4_512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextractf64x4MaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x4_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X4_512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTF64X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextractf64x4MaskzEmitter<A, B, C> {
    fn vextractf64x4_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextractf64x4MaskzEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextractf64x4_maskz(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTF64X4_512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI32X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Ymm, Imm |
/// | 2 | Mem, Zmm, Imm |
/// | 3 | Xmm, Ymm, Imm |
/// | 4 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti32x4Emitter<A, B, C> {
    fn vextracti32x4(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti32x4Emitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextracti32x4(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x4Emitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vextracti32x4(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_256MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x4Emitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x4(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x4Emitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x4(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI32X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Ymm, Imm |
/// | 2 | Mem, Zmm, Imm |
/// | 3 | Xmm, Ymm, Imm |
/// | 4 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti32x4MaskEmitter<A, B, C> {
    fn vextracti32x4_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti32x4MaskEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextracti32x4_mask(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x4MaskEmitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vextracti32x4_mask(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_256MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x4MaskEmitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x4_mask(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x4MaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x4_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI32X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Ymm, Imm |
/// | 2 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti32x4MaskzEmitter<A, B, C> {
    fn vextracti32x4_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti32x4MaskzEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextracti32x4_maskz(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x4MaskzEmitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x4_maskz(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X4_512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI32X8`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Zmm, Imm |
/// | 2 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti32x8Emitter<A, B, C> {
    fn vextracti32x8(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti32x8Emitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x8(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X8_512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x8Emitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x8(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X8_512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI32X8_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Zmm, Imm |
/// | 2 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti32x8MaskEmitter<A, B, C> {
    fn vextracti32x8_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti32x8MaskEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x8_mask(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X8_512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti32x8MaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x8_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X8_512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI32X8_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti32x8MaskzEmitter<A, B, C> {
    fn vextracti32x8_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti32x8MaskzEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextracti32x8_maskz(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI32X8_512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI64X2`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Ymm, Imm |
/// | 2 | Mem, Zmm, Imm |
/// | 3 | Xmm, Ymm, Imm |
/// | 4 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti64x2Emitter<A, B, C> {
    fn vextracti64x2(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti64x2Emitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextracti64x2(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x2Emitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vextracti64x2(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_256MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x2Emitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x2(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x2Emitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x2(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI64X2_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Ymm, Imm |
/// | 2 | Mem, Zmm, Imm |
/// | 3 | Xmm, Ymm, Imm |
/// | 4 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti64x2MaskEmitter<A, B, C> {
    fn vextracti64x2_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti64x2MaskEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextracti64x2_mask(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x2MaskEmitter<Mem, Ymm, Imm> for Assembler<'a> {
    fn vextracti64x2_mask(&mut self, op0: Mem, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_256MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x2MaskEmitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x2_mask(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x2MaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x2_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI64X2_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Ymm, Imm |
/// | 2 | Xmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti64x2MaskzEmitter<A, B, C> {
    fn vextracti64x2_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti64x2MaskzEmitter<Xmm, Ymm, Imm> for Assembler<'a> {
    fn vextracti64x2_maskz(&mut self, op0: Xmm, op1: Ymm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x2MaskzEmitter<Xmm, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x2_maskz(&mut self, op0: Xmm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X2_512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI64X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Zmm, Imm |
/// | 2 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti64x4Emitter<A, B, C> {
    fn vextracti64x4(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti64x4Emitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x4(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X4_512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x4Emitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x4(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X4_512MRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI64X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Mem, Zmm, Imm |
/// | 2 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti64x4MaskEmitter<A, B, C> {
    fn vextracti64x4_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti64x4MaskEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x4_mask(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X4_512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vextracti64x4MaskEmitter<Mem, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x4_mask(&mut self, op0: Mem, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X4_512MRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTI64X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait Vextracti64x4MaskzEmitter<A, B, C> {
    fn vextracti64x4_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vextracti64x4MaskzEmitter<Ymm, Zmm, Imm> for Assembler<'a> {
    fn vextracti64x4_maskz(&mut self, op0: Ymm, op1: Zmm, op2: Imm) {
        self.emit(
            VEXTRACTI64X4_512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VEXTRACTPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Gpd, Xmm, Imm |
/// | 2 | Mem, Xmm, Imm |
/// +---+---------------+
/// ```
pub trait VextractpsEmitter<A, B, C> {
    fn vextractps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VextractpsEmitter<Gpd, Xmm, Imm> for Assembler<'a> {
    fn vextractps(&mut self, op0: Gpd, op1: Xmm, op2: Imm) {
        self.emit(
            VEXTRACTPSRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VextractpsEmitter<Mem, Xmm, Imm> for Assembler<'a> {
    fn vextractps(&mut self, op0: Mem, op1: Xmm, op2: Imm) {
        self.emit(
            VEXTRACTPSMRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFIXUPIMMPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpdEmitter<A, B, C, D> {
    fn vfixupimmpd(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpdEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD128RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD128RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vfixupimmpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpdMaskEmitter<A, B, C, D> {
    fn vfixupimmpd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpdMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD128RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD128RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vfixupimmpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpdMaskSaeEmitter<A, B, C, D> {
    fn vfixupimmpd_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpdMaskSaeEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmpd_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpdMaskzEmitter<A, B, C, D> {
    fn vfixupimmpd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpdMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD128RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD128RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vfixupimmpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpdMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpdMaskzSaeEmitter<A, B, C, D> {
    fn vfixupimmpd_maskz_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpdMaskzSaeEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmpd_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpdSaeEmitter<A, B, C, D> {
    fn vfixupimmpd_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpdSaeEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmpd_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPD512RRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpsEmitter<A, B, C, D> {
    fn vfixupimmps(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpsEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS128RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS128RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vfixupimmps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpsMaskEmitter<A, B, C, D> {
    fn vfixupimmps_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpsMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS128RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS128RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vfixupimmps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpsMaskSaeEmitter<A, B, C, D> {
    fn vfixupimmps_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpsMaskSaeEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmps_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpsMaskzEmitter<A, B, C, D> {
    fn vfixupimmps_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpsMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS128RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS128RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vfixupimmps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmpsMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpsMaskzSaeEmitter<A, B, C, D> {
    fn vfixupimmps_maskz_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpsMaskzSaeEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmps_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMPS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmpsSaeEmitter<A, B, C, D> {
    fn vfixupimmps_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmpsSaeEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vfixupimmps_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VFIXUPIMMPS512RRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmsdEmitter<A, B, C, D> {
    fn vfixupimmsd(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmsdEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmsdEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmsdMaskEmitter<A, B, C, D> {
    fn vfixupimmsd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmsdMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmsdMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmsdMaskSaeEmitter<A, B, C, D> {
    fn vfixupimmsd_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmsdMaskSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmsd_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmsdMaskzEmitter<A, B, C, D> {
    fn vfixupimmsd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmsdMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmsdMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmsdMaskzSaeEmitter<A, B, C, D> {
    fn vfixupimmsd_maskz_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmsdMaskzSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmsd_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmsdSaeEmitter<A, B, C, D> {
    fn vfixupimmsd_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmsdSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmsd_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSDRRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmssEmitter<A, B, C, D> {
    fn vfixupimmss(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmssEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmssEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmss(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmssMaskEmitter<A, B, C, D> {
    fn vfixupimmss_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmssMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmssMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmssMaskSaeEmitter<A, B, C, D> {
    fn vfixupimmss_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmssMaskSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmss_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmssMaskzEmitter<A, B, C, D> {
    fn vfixupimmss_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmssMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VfixupimmssMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vfixupimmss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmssMaskzSaeEmitter<A, B, C, D> {
    fn vfixupimmss_maskz_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmssMaskzSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmss_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFIXUPIMMSS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VfixupimmssSaeEmitter<A, B, C, D> {
    fn vfixupimmss_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VfixupimmssSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vfixupimmss_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VFIXUPIMMSSRRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VFMADD132PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132pdEmitter<A, B, C> {
    fn vfmadd132pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd132pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD132PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd132pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD132PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd132pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD132PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132pdErEmitter<A, B, C> {
    fn vfmadd132pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132pdMaskEmitter<A, B, C> {
    fn vfmadd132pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD132PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD132PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD132PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132pdMaskErEmitter<A, B, C> {
    fn vfmadd132pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132pdMaskzEmitter<A, B, C> {
    fn vfmadd132pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD132PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD132PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD132PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132pdMaskzErEmitter<A, B, C> {
    fn vfmadd132pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132psEmitter<A, B, C> {
    fn vfmadd132ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd132ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD132PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd132ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD132PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd132ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD132PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132psErEmitter<A, B, C> {
    fn vfmadd132ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132psMaskEmitter<A, B, C> {
    fn vfmadd132ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD132PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD132PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD132PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132psMaskErEmitter<A, B, C> {
    fn vfmadd132ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132psMaskzEmitter<A, B, C> {
    fn vfmadd132ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD132PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD132PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD132PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132psMaskzErEmitter<A, B, C> {
    fn vfmadd132ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd132ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD132PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132sdEmitter<A, B, C> {
    fn vfmadd132sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132sdErEmitter<A, B, C> {
    fn vfmadd132sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132sdMaskEmitter<A, B, C> {
    fn vfmadd132sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132sdMaskErEmitter<A, B, C> {
    fn vfmadd132sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132sdMaskzEmitter<A, B, C> {
    fn vfmadd132sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132sdMaskzErEmitter<A, B, C> {
    fn vfmadd132sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132ssEmitter<A, B, C> {
    fn vfmadd132ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132ssErEmitter<A, B, C> {
    fn vfmadd132ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132ssMaskEmitter<A, B, C> {
    fn vfmadd132ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132ssMaskErEmitter<A, B, C> {
    fn vfmadd132ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132ssMaskzEmitter<A, B, C> {
    fn vfmadd132ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd132ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd132ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD132SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD132SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd132ssMaskzErEmitter<A, B, C> {
    fn vfmadd132ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd132ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd132ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD132SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213pdEmitter<A, B, C> {
    fn vfmadd213pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd213pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD213PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd213pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD213PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd213pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD213PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213pdErEmitter<A, B, C> {
    fn vfmadd213pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213pdMaskEmitter<A, B, C> {
    fn vfmadd213pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD213PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD213PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD213PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213pdMaskErEmitter<A, B, C> {
    fn vfmadd213pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213pdMaskzEmitter<A, B, C> {
    fn vfmadd213pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD213PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD213PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD213PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213pdMaskzErEmitter<A, B, C> {
    fn vfmadd213pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213psEmitter<A, B, C> {
    fn vfmadd213ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd213ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD213PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd213ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD213PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd213ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD213PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213psErEmitter<A, B, C> {
    fn vfmadd213ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213psMaskEmitter<A, B, C> {
    fn vfmadd213ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD213PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD213PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD213PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213psMaskErEmitter<A, B, C> {
    fn vfmadd213ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213psMaskzEmitter<A, B, C> {
    fn vfmadd213ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD213PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD213PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD213PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213psMaskzErEmitter<A, B, C> {
    fn vfmadd213ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd213ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD213PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213sdEmitter<A, B, C> {
    fn vfmadd213sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213sdErEmitter<A, B, C> {
    fn vfmadd213sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213sdMaskEmitter<A, B, C> {
    fn vfmadd213sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213sdMaskErEmitter<A, B, C> {
    fn vfmadd213sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213sdMaskzEmitter<A, B, C> {
    fn vfmadd213sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213sdMaskzErEmitter<A, B, C> {
    fn vfmadd213sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213ssEmitter<A, B, C> {
    fn vfmadd213ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213ssErEmitter<A, B, C> {
    fn vfmadd213ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213ssMaskEmitter<A, B, C> {
    fn vfmadd213ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213ssMaskErEmitter<A, B, C> {
    fn vfmadd213ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213ssMaskzEmitter<A, B, C> {
    fn vfmadd213ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd213ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd213ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD213SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD213SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd213ssMaskzErEmitter<A, B, C> {
    fn vfmadd213ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd213ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd213ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD213SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231pdEmitter<A, B, C> {
    fn vfmadd231pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd231pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD231PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd231pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD231PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd231pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD231PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231pdErEmitter<A, B, C> {
    fn vfmadd231pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231pdMaskEmitter<A, B, C> {
    fn vfmadd231pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD231PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD231PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD231PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231pdMaskErEmitter<A, B, C> {
    fn vfmadd231pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231pdMaskzEmitter<A, B, C> {
    fn vfmadd231pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD231PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD231PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD231PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231pdMaskzErEmitter<A, B, C> {
    fn vfmadd231pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231psEmitter<A, B, C> {
    fn vfmadd231ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd231ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD231PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd231ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD231PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd231ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD231PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231psErEmitter<A, B, C> {
    fn vfmadd231ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231psMaskEmitter<A, B, C> {
    fn vfmadd231ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD231PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD231PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD231PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231psMaskErEmitter<A, B, C> {
    fn vfmadd231ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231psMaskzEmitter<A, B, C> {
    fn vfmadd231ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmadd231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADD231PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmadd231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADD231PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmadd231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADD231PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231psMaskzErEmitter<A, B, C> {
    fn vfmadd231ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmadd231ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADD231PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231sdEmitter<A, B, C> {
    fn vfmadd231sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231sdErEmitter<A, B, C> {
    fn vfmadd231sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231sdMaskEmitter<A, B, C> {
    fn vfmadd231sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231sdMaskErEmitter<A, B, C> {
    fn vfmadd231sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231sdMaskzEmitter<A, B, C> {
    fn vfmadd231sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231sdMaskzErEmitter<A, B, C> {
    fn vfmadd231sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231ssEmitter<A, B, C> {
    fn vfmadd231ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231ssErEmitter<A, B, C> {
    fn vfmadd231ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231ssMaskEmitter<A, B, C> {
    fn vfmadd231ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231ssMaskErEmitter<A, B, C> {
    fn vfmadd231ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231ssMaskzEmitter<A, B, C> {
    fn vfmadd231ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmadd231ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmadd231ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADD231SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADD231SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmadd231ssMaskzErEmitter<A, B, C> {
    fn vfmadd231ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmadd231ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmadd231ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADD231SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132pdEmitter<A, B, C> {
    fn vfmaddsub132pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub132pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB132PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub132pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB132PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132pdErEmitter<A, B, C> {
    fn vfmaddsub132pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132pdMaskEmitter<A, B, C> {
    fn vfmaddsub132pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB132PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB132PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132pdMaskErEmitter<A, B, C> {
    fn vfmaddsub132pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132pdMaskzEmitter<A, B, C> {
    fn vfmaddsub132pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB132PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB132PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132pdMaskzErEmitter<A, B, C> {
    fn vfmaddsub132pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132psEmitter<A, B, C> {
    fn vfmaddsub132ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub132ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB132PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub132ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB132PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132psErEmitter<A, B, C> {
    fn vfmaddsub132ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132psMaskEmitter<A, B, C> {
    fn vfmaddsub132ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB132PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB132PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132psMaskErEmitter<A, B, C> {
    fn vfmaddsub132ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132psMaskzEmitter<A, B, C> {
    fn vfmaddsub132ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB132PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB132PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub132psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB132PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB132PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub132psMaskzErEmitter<A, B, C> {
    fn vfmaddsub132ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub132psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub132ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB132PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213pdEmitter<A, B, C> {
    fn vfmaddsub213pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub213pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB213PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub213pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB213PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213pdErEmitter<A, B, C> {
    fn vfmaddsub213pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213pdMaskEmitter<A, B, C> {
    fn vfmaddsub213pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB213PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB213PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213pdMaskErEmitter<A, B, C> {
    fn vfmaddsub213pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213pdMaskzEmitter<A, B, C> {
    fn vfmaddsub213pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB213PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB213PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213pdMaskzErEmitter<A, B, C> {
    fn vfmaddsub213pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213psEmitter<A, B, C> {
    fn vfmaddsub213ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub213ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB213PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub213ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB213PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213psErEmitter<A, B, C> {
    fn vfmaddsub213ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213psMaskEmitter<A, B, C> {
    fn vfmaddsub213ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB213PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB213PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213psMaskErEmitter<A, B, C> {
    fn vfmaddsub213ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213psMaskzEmitter<A, B, C> {
    fn vfmaddsub213ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB213PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB213PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub213psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB213PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB213PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub213psMaskzErEmitter<A, B, C> {
    fn vfmaddsub213ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub213psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub213ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB213PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231pdEmitter<A, B, C> {
    fn vfmaddsub231pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub231pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB231PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub231pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB231PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231pdErEmitter<A, B, C> {
    fn vfmaddsub231pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231pdMaskEmitter<A, B, C> {
    fn vfmaddsub231pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB231PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB231PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231pdMaskErEmitter<A, B, C> {
    fn vfmaddsub231pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231pdMaskzEmitter<A, B, C> {
    fn vfmaddsub231pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB231PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB231PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231pdMaskzErEmitter<A, B, C> {
    fn vfmaddsub231pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231psEmitter<A, B, C> {
    fn vfmaddsub231ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub231ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB231PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub231ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB231PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231psErEmitter<A, B, C> {
    fn vfmaddsub231ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231psMaskEmitter<A, B, C> {
    fn vfmaddsub231ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB231PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB231PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231psMaskErEmitter<A, B, C> {
    fn vfmaddsub231ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231psMaskzEmitter<A, B, C> {
    fn vfmaddsub231ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmaddsub231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMADDSUB231PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmaddsub231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMADDSUB231PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmaddsub231psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmaddsub231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMADDSUB231PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMADDSUB231PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmaddsub231psMaskzErEmitter<A, B, C> {
    fn vfmaddsub231ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmaddsub231psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmaddsub231ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMADDSUB231PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132pdEmitter<A, B, C> {
    fn vfmsub132pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub132pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB132PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub132pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB132PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub132pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB132PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132pdErEmitter<A, B, C> {
    fn vfmsub132pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132pdMaskEmitter<A, B, C> {
    fn vfmsub132pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB132PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB132PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB132PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132pdMaskErEmitter<A, B, C> {
    fn vfmsub132pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132pdMaskzEmitter<A, B, C> {
    fn vfmsub132pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB132PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB132PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB132PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132pdMaskzErEmitter<A, B, C> {
    fn vfmsub132pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132psEmitter<A, B, C> {
    fn vfmsub132ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub132ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB132PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub132ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB132PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub132ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB132PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132psErEmitter<A, B, C> {
    fn vfmsub132ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132psMaskEmitter<A, B, C> {
    fn vfmsub132ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB132PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB132PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB132PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132psMaskErEmitter<A, B, C> {
    fn vfmsub132ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132psMaskzEmitter<A, B, C> {
    fn vfmsub132ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB132PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB132PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB132PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132psMaskzErEmitter<A, B, C> {
    fn vfmsub132ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub132ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB132PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132sdEmitter<A, B, C> {
    fn vfmsub132sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132sdErEmitter<A, B, C> {
    fn vfmsub132sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132sdMaskEmitter<A, B, C> {
    fn vfmsub132sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132sdMaskErEmitter<A, B, C> {
    fn vfmsub132sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132sdMaskzEmitter<A, B, C> {
    fn vfmsub132sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132sdMaskzErEmitter<A, B, C> {
    fn vfmsub132sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132ssEmitter<A, B, C> {
    fn vfmsub132ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132ssErEmitter<A, B, C> {
    fn vfmsub132ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132ssMaskEmitter<A, B, C> {
    fn vfmsub132ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132ssMaskErEmitter<A, B, C> {
    fn vfmsub132ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132ssMaskzEmitter<A, B, C> {
    fn vfmsub132ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub132ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub132ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB132SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB132SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub132ssMaskzErEmitter<A, B, C> {
    fn vfmsub132ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub132ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub132ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB132SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213pdEmitter<A, B, C> {
    fn vfmsub213pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub213pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB213PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub213pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB213PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub213pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB213PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213pdErEmitter<A, B, C> {
    fn vfmsub213pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213pdMaskEmitter<A, B, C> {
    fn vfmsub213pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB213PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB213PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB213PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213pdMaskErEmitter<A, B, C> {
    fn vfmsub213pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213pdMaskzEmitter<A, B, C> {
    fn vfmsub213pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB213PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB213PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB213PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213pdMaskzErEmitter<A, B, C> {
    fn vfmsub213pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213psEmitter<A, B, C> {
    fn vfmsub213ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub213ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB213PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub213ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB213PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub213ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB213PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213psErEmitter<A, B, C> {
    fn vfmsub213ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213psMaskEmitter<A, B, C> {
    fn vfmsub213ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB213PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB213PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB213PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213psMaskErEmitter<A, B, C> {
    fn vfmsub213ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213psMaskzEmitter<A, B, C> {
    fn vfmsub213ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB213PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB213PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB213PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213psMaskzErEmitter<A, B, C> {
    fn vfmsub213ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub213ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB213PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213sdEmitter<A, B, C> {
    fn vfmsub213sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213sdErEmitter<A, B, C> {
    fn vfmsub213sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213sdMaskEmitter<A, B, C> {
    fn vfmsub213sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213sdMaskErEmitter<A, B, C> {
    fn vfmsub213sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213sdMaskzEmitter<A, B, C> {
    fn vfmsub213sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213sdMaskzErEmitter<A, B, C> {
    fn vfmsub213sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213ssEmitter<A, B, C> {
    fn vfmsub213ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213ssErEmitter<A, B, C> {
    fn vfmsub213ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213ssMaskEmitter<A, B, C> {
    fn vfmsub213ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213ssMaskErEmitter<A, B, C> {
    fn vfmsub213ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213ssMaskzEmitter<A, B, C> {
    fn vfmsub213ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub213ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub213ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB213SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB213SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub213ssMaskzErEmitter<A, B, C> {
    fn vfmsub213ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub213ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub213ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB213SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231pdEmitter<A, B, C> {
    fn vfmsub231pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub231pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB231PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub231pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB231PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub231pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB231PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231pdErEmitter<A, B, C> {
    fn vfmsub231pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231pdMaskEmitter<A, B, C> {
    fn vfmsub231pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB231PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB231PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB231PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231pdMaskErEmitter<A, B, C> {
    fn vfmsub231pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231pdMaskzEmitter<A, B, C> {
    fn vfmsub231pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB231PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB231PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB231PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231pdMaskzErEmitter<A, B, C> {
    fn vfmsub231pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231psEmitter<A, B, C> {
    fn vfmsub231ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub231ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB231PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub231ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB231PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub231ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB231PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231psErEmitter<A, B, C> {
    fn vfmsub231ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231psMaskEmitter<A, B, C> {
    fn vfmsub231ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB231PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB231PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB231PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231psMaskErEmitter<A, B, C> {
    fn vfmsub231ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231psMaskzEmitter<A, B, C> {
    fn vfmsub231ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsub231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUB231PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsub231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUB231PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsub231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUB231PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231psMaskzErEmitter<A, B, C> {
    fn vfmsub231ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsub231ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUB231PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231sdEmitter<A, B, C> {
    fn vfmsub231sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231sdErEmitter<A, B, C> {
    fn vfmsub231sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231sdMaskEmitter<A, B, C> {
    fn vfmsub231sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231sdMaskErEmitter<A, B, C> {
    fn vfmsub231sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231sdMaskzEmitter<A, B, C> {
    fn vfmsub231sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231sdMaskzErEmitter<A, B, C> {
    fn vfmsub231sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231ssEmitter<A, B, C> {
    fn vfmsub231ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231ssErEmitter<A, B, C> {
    fn vfmsub231ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231ssMaskEmitter<A, B, C> {
    fn vfmsub231ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231ssMaskErEmitter<A, B, C> {
    fn vfmsub231ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231ssMaskzEmitter<A, B, C> {
    fn vfmsub231ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsub231ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsub231ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUB231SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUB231SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfmsub231ssMaskzErEmitter<A, B, C> {
    fn vfmsub231ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsub231ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsub231ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUB231SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132pdEmitter<A, B, C> {
    fn vfmsubadd132pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd132pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD132PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd132pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD132PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132pdErEmitter<A, B, C> {
    fn vfmsubadd132pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132pdMaskEmitter<A, B, C> {
    fn vfmsubadd132pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD132PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD132PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132pdMaskErEmitter<A, B, C> {
    fn vfmsubadd132pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132pdMaskzEmitter<A, B, C> {
    fn vfmsubadd132pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD132PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD132PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132pdMaskzErEmitter<A, B, C> {
    fn vfmsubadd132pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132psEmitter<A, B, C> {
    fn vfmsubadd132ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd132ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD132PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd132ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD132PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132psErEmitter<A, B, C> {
    fn vfmsubadd132ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132psMaskEmitter<A, B, C> {
    fn vfmsubadd132ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD132PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD132PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132psMaskErEmitter<A, B, C> {
    fn vfmsubadd132ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132psMaskzEmitter<A, B, C> {
    fn vfmsubadd132ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD132PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD132PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd132psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD132PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD132PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd132psMaskzErEmitter<A, B, C> {
    fn vfmsubadd132ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd132psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd132ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD132PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213pdEmitter<A, B, C> {
    fn vfmsubadd213pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd213pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD213PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd213pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD213PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213pdErEmitter<A, B, C> {
    fn vfmsubadd213pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213pdMaskEmitter<A, B, C> {
    fn vfmsubadd213pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD213PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD213PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213pdMaskErEmitter<A, B, C> {
    fn vfmsubadd213pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213pdMaskzEmitter<A, B, C> {
    fn vfmsubadd213pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD213PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD213PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213pdMaskzErEmitter<A, B, C> {
    fn vfmsubadd213pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213psEmitter<A, B, C> {
    fn vfmsubadd213ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd213ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD213PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd213ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD213PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213psErEmitter<A, B, C> {
    fn vfmsubadd213ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213psMaskEmitter<A, B, C> {
    fn vfmsubadd213ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD213PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD213PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213psMaskErEmitter<A, B, C> {
    fn vfmsubadd213ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213psMaskzEmitter<A, B, C> {
    fn vfmsubadd213ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD213PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD213PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd213psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD213PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD213PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd213psMaskzErEmitter<A, B, C> {
    fn vfmsubadd213ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd213psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd213ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD213PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231pdEmitter<A, B, C> {
    fn vfmsubadd231pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd231pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD231PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd231pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD231PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231pdErEmitter<A, B, C> {
    fn vfmsubadd231pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231pdMaskEmitter<A, B, C> {
    fn vfmsubadd231pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD231PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD231PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231pdMaskErEmitter<A, B, C> {
    fn vfmsubadd231pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231pdMaskzEmitter<A, B, C> {
    fn vfmsubadd231pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD231PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD231PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231pdMaskzErEmitter<A, B, C> {
    fn vfmsubadd231pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231psEmitter<A, B, C> {
    fn vfmsubadd231ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd231ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD231PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd231ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD231PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231psErEmitter<A, B, C> {
    fn vfmsubadd231ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231psMaskEmitter<A, B, C> {
    fn vfmsubadd231ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD231PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD231PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231psMaskErEmitter<A, B, C> {
    fn vfmsubadd231ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231psMaskzEmitter<A, B, C> {
    fn vfmsubadd231ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfmsubadd231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFMSUBADD231PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfmsubadd231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFMSUBADD231PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfmsubadd231psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfmsubadd231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFMSUBADD231PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFMSUBADD231PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfmsubadd231psMaskzErEmitter<A, B, C> {
    fn vfmsubadd231ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfmsubadd231psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfmsubadd231ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFMSUBADD231PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132pdEmitter<A, B, C> {
    fn vfnmadd132pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd132pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD132PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd132pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD132PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd132pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD132PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132pdErEmitter<A, B, C> {
    fn vfnmadd132pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132pdMaskEmitter<A, B, C> {
    fn vfnmadd132pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD132PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD132PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD132PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132pdMaskErEmitter<A, B, C> {
    fn vfnmadd132pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132pdMaskzEmitter<A, B, C> {
    fn vfnmadd132pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD132PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD132PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD132PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132pdMaskzErEmitter<A, B, C> {
    fn vfnmadd132pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132psEmitter<A, B, C> {
    fn vfnmadd132ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd132ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD132PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd132ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD132PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd132ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD132PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132psErEmitter<A, B, C> {
    fn vfnmadd132ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132psMaskEmitter<A, B, C> {
    fn vfnmadd132ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD132PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD132PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD132PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132psMaskErEmitter<A, B, C> {
    fn vfnmadd132ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132psMaskzEmitter<A, B, C> {
    fn vfnmadd132ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD132PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD132PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD132PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132psMaskzErEmitter<A, B, C> {
    fn vfnmadd132ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd132ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD132PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132sdEmitter<A, B, C> {
    fn vfnmadd132sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132sdErEmitter<A, B, C> {
    fn vfnmadd132sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132sdMaskEmitter<A, B, C> {
    fn vfnmadd132sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132sdMaskErEmitter<A, B, C> {
    fn vfnmadd132sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132sdMaskzEmitter<A, B, C> {
    fn vfnmadd132sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132sdMaskzErEmitter<A, B, C> {
    fn vfnmadd132sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132ssEmitter<A, B, C> {
    fn vfnmadd132ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132ssErEmitter<A, B, C> {
    fn vfnmadd132ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132ssMaskEmitter<A, B, C> {
    fn vfnmadd132ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132ssMaskErEmitter<A, B, C> {
    fn vfnmadd132ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132ssMaskzEmitter<A, B, C> {
    fn vfnmadd132ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd132ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd132ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD132SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD132SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd132ssMaskzErEmitter<A, B, C> {
    fn vfnmadd132ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd132ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd132ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD132SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213pdEmitter<A, B, C> {
    fn vfnmadd213pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd213pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD213PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd213pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD213PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd213pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD213PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213pdErEmitter<A, B, C> {
    fn vfnmadd213pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213pdMaskEmitter<A, B, C> {
    fn vfnmadd213pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD213PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD213PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD213PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213pdMaskErEmitter<A, B, C> {
    fn vfnmadd213pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213pdMaskzEmitter<A, B, C> {
    fn vfnmadd213pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD213PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD213PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD213PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213pdMaskzErEmitter<A, B, C> {
    fn vfnmadd213pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213psEmitter<A, B, C> {
    fn vfnmadd213ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd213ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD213PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd213ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD213PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd213ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD213PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213psErEmitter<A, B, C> {
    fn vfnmadd213ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213psMaskEmitter<A, B, C> {
    fn vfnmadd213ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD213PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD213PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD213PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213psMaskErEmitter<A, B, C> {
    fn vfnmadd213ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213psMaskzEmitter<A, B, C> {
    fn vfnmadd213ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD213PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD213PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD213PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213psMaskzErEmitter<A, B, C> {
    fn vfnmadd213ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd213ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD213PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213sdEmitter<A, B, C> {
    fn vfnmadd213sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213sdErEmitter<A, B, C> {
    fn vfnmadd213sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213sdMaskEmitter<A, B, C> {
    fn vfnmadd213sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213sdMaskErEmitter<A, B, C> {
    fn vfnmadd213sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213sdMaskzEmitter<A, B, C> {
    fn vfnmadd213sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213sdMaskzErEmitter<A, B, C> {
    fn vfnmadd213sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213ssEmitter<A, B, C> {
    fn vfnmadd213ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213ssErEmitter<A, B, C> {
    fn vfnmadd213ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213ssMaskEmitter<A, B, C> {
    fn vfnmadd213ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213ssMaskErEmitter<A, B, C> {
    fn vfnmadd213ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213ssMaskzEmitter<A, B, C> {
    fn vfnmadd213ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd213ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd213ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD213SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD213SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd213ssMaskzErEmitter<A, B, C> {
    fn vfnmadd213ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd213ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd213ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD213SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231pdEmitter<A, B, C> {
    fn vfnmadd231pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd231pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD231PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd231pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD231PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd231pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD231PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231pdErEmitter<A, B, C> {
    fn vfnmadd231pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231pdMaskEmitter<A, B, C> {
    fn vfnmadd231pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD231PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD231PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD231PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231pdMaskErEmitter<A, B, C> {
    fn vfnmadd231pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231pdMaskzEmitter<A, B, C> {
    fn vfnmadd231pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD231PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD231PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD231PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231pdMaskzErEmitter<A, B, C> {
    fn vfnmadd231pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231psEmitter<A, B, C> {
    fn vfnmadd231ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd231ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD231PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd231ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD231PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd231ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD231PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231psErEmitter<A, B, C> {
    fn vfnmadd231ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231psMaskEmitter<A, B, C> {
    fn vfnmadd231ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD231PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD231PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD231PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231psMaskErEmitter<A, B, C> {
    fn vfnmadd231ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231psMaskzEmitter<A, B, C> {
    fn vfnmadd231ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmadd231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMADD231PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmadd231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMADD231PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmadd231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMADD231PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231psMaskzErEmitter<A, B, C> {
    fn vfnmadd231ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmadd231ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMADD231PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231sdEmitter<A, B, C> {
    fn vfnmadd231sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231sdErEmitter<A, B, C> {
    fn vfnmadd231sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231sdMaskEmitter<A, B, C> {
    fn vfnmadd231sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231sdMaskErEmitter<A, B, C> {
    fn vfnmadd231sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231sdMaskzEmitter<A, B, C> {
    fn vfnmadd231sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231sdMaskzErEmitter<A, B, C> {
    fn vfnmadd231sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231ssEmitter<A, B, C> {
    fn vfnmadd231ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231ssErEmitter<A, B, C> {
    fn vfnmadd231ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231ssMaskEmitter<A, B, C> {
    fn vfnmadd231ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231ssMaskErEmitter<A, B, C> {
    fn vfnmadd231ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231ssMaskzEmitter<A, B, C> {
    fn vfnmadd231ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmadd231ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmadd231ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMADD231SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMADD231SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmadd231ssMaskzErEmitter<A, B, C> {
    fn vfnmadd231ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmadd231ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmadd231ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMADD231SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132pdEmitter<A, B, C> {
    fn vfnmsub132pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub132pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB132PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub132pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB132PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub132pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB132PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132pdErEmitter<A, B, C> {
    fn vfnmsub132pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132pdMaskEmitter<A, B, C> {
    fn vfnmsub132pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB132PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub132pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB132PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub132pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB132PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132pdMaskErEmitter<A, B, C> {
    fn vfnmsub132pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132pdMaskzEmitter<A, B, C> {
    fn vfnmsub132pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB132PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub132pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB132PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub132pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB132PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132pdMaskzErEmitter<A, B, C> {
    fn vfnmsub132pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132psEmitter<A, B, C> {
    fn vfnmsub132ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub132ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB132PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub132ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB132PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub132ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB132PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132psErEmitter<A, B, C> {
    fn vfnmsub132ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132psMaskEmitter<A, B, C> {
    fn vfnmsub132ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB132PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub132ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB132PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub132ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB132PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132psMaskErEmitter<A, B, C> {
    fn vfnmsub132ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132psMaskzEmitter<A, B, C> {
    fn vfnmsub132ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB132PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub132ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB132PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub132ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB132PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132psMaskzErEmitter<A, B, C> {
    fn vfnmsub132ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub132ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB132PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132sdEmitter<A, B, C> {
    fn vfnmsub132sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132sdErEmitter<A, B, C> {
    fn vfnmsub132sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132sdMaskEmitter<A, B, C> {
    fn vfnmsub132sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132sdMaskErEmitter<A, B, C> {
    fn vfnmsub132sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132sdMaskzEmitter<A, B, C> {
    fn vfnmsub132sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132sdMaskzErEmitter<A, B, C> {
    fn vfnmsub132sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132ssEmitter<A, B, C> {
    fn vfnmsub132ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132ssErEmitter<A, B, C> {
    fn vfnmsub132ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132ssMaskEmitter<A, B, C> {
    fn vfnmsub132ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132ssMaskErEmitter<A, B, C> {
    fn vfnmsub132ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132ssMaskzEmitter<A, B, C> {
    fn vfnmsub132ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub132ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub132ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB132SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB132SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub132ssMaskzErEmitter<A, B, C> {
    fn vfnmsub132ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub132ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub132ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB132SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213pdEmitter<A, B, C> {
    fn vfnmsub213pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub213pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB213PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub213pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB213PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub213pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB213PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213pdErEmitter<A, B, C> {
    fn vfnmsub213pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213pdMaskEmitter<A, B, C> {
    fn vfnmsub213pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB213PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub213pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB213PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub213pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB213PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213pdMaskErEmitter<A, B, C> {
    fn vfnmsub213pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213pdMaskzEmitter<A, B, C> {
    fn vfnmsub213pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB213PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub213pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB213PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub213pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB213PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213pdMaskzErEmitter<A, B, C> {
    fn vfnmsub213pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213psEmitter<A, B, C> {
    fn vfnmsub213ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub213ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB213PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub213ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB213PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub213ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB213PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213psErEmitter<A, B, C> {
    fn vfnmsub213ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213psMaskEmitter<A, B, C> {
    fn vfnmsub213ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB213PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub213ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB213PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub213ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB213PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213psMaskErEmitter<A, B, C> {
    fn vfnmsub213ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213psMaskzEmitter<A, B, C> {
    fn vfnmsub213ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB213PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub213ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB213PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub213ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB213PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213psMaskzErEmitter<A, B, C> {
    fn vfnmsub213ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub213ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB213PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213sdEmitter<A, B, C> {
    fn vfnmsub213sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213sdErEmitter<A, B, C> {
    fn vfnmsub213sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213sdMaskEmitter<A, B, C> {
    fn vfnmsub213sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213sdMaskErEmitter<A, B, C> {
    fn vfnmsub213sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213sdMaskzEmitter<A, B, C> {
    fn vfnmsub213sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213sdMaskzErEmitter<A, B, C> {
    fn vfnmsub213sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213ssEmitter<A, B, C> {
    fn vfnmsub213ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213ssErEmitter<A, B, C> {
    fn vfnmsub213ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213ssMaskEmitter<A, B, C> {
    fn vfnmsub213ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213ssMaskErEmitter<A, B, C> {
    fn vfnmsub213ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213ssMaskzEmitter<A, B, C> {
    fn vfnmsub213ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub213ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub213ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB213SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB213SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub213ssMaskzErEmitter<A, B, C> {
    fn vfnmsub213ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub213ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub213ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB213SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231pdEmitter<A, B, C> {
    fn vfnmsub231pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub231pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB231PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub231pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB231PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub231pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB231PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231pdErEmitter<A, B, C> {
    fn vfnmsub231pd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231pdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231pd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231pdMaskEmitter<A, B, C> {
    fn vfnmsub231pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB231PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub231pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB231PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub231pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB231PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231pdMaskErEmitter<A, B, C> {
    fn vfnmsub231pd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231pdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231pd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231pdMaskzEmitter<A, B, C> {
    fn vfnmsub231pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB231PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub231pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB231PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub231pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB231PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231pdMaskzErEmitter<A, B, C> {
    fn vfnmsub231pd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231pdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231pd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231psEmitter<A, B, C> {
    fn vfnmsub231ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub231ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB231PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub231ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB231PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub231ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB231PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231psErEmitter<A, B, C> {
    fn vfnmsub231ps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231psErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231ps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231psMaskEmitter<A, B, C> {
    fn vfnmsub231ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB231PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub231ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB231PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub231ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB231PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231psMaskErEmitter<A, B, C> {
    fn vfnmsub231ps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231psMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231ps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231psMaskzEmitter<A, B, C> {
    fn vfnmsub231ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vfnmsub231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VFNMSUB231PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vfnmsub231ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VFNMSUB231PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vfnmsub231ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VFNMSUB231PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231PS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231psMaskzErEmitter<A, B, C> {
    fn vfnmsub231ps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231psMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vfnmsub231ps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VFNMSUB231PS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231sdEmitter<A, B, C> {
    fn vfnmsub231sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231sdErEmitter<A, B, C> {
    fn vfnmsub231sd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231sdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231sd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231sdMaskEmitter<A, B, C> {
    fn vfnmsub231sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231sdMaskErEmitter<A, B, C> {
    fn vfnmsub231sd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231sdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231sd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231sdMaskzEmitter<A, B, C> {
    fn vfnmsub231sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231sdMaskzErEmitter<A, B, C> {
    fn vfnmsub231sd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231sdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231sd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231ssEmitter<A, B, C> {
    fn vfnmsub231ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231ssErEmitter<A, B, C> {
    fn vfnmsub231ss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231ssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231ssMaskEmitter<A, B, C> {
    fn vfnmsub231ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231ssMaskErEmitter<A, B, C> {
    fn vfnmsub231ss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231ssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231ssMaskzEmitter<A, B, C> {
    fn vfnmsub231ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vfnmsub231ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vfnmsub231ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VFNMSUB231SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VFNMSUB231SS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vfnmsub231ssMaskzErEmitter<A, B, C> {
    fn vfnmsub231ss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vfnmsub231ssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vfnmsub231ss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VFNMSUB231SSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGATHERDPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// | 3 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait VgatherdpdEmitter_2<A, B> {
    fn vgatherdpd_2(&mut self, op0: A, op1: B);
}

impl<'a> VgatherdpdEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vgatherdpd_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGATHERDPD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgatherdpdEmitter_2<Ymm, Mem> for Assembler<'a> {
    fn vgatherdpd_2(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGATHERDPD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgatherdpdEmitter_2<Zmm, Mem> for Assembler<'a> {
    fn vgatherdpd_2(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGATHERDPD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGATHERDPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// | 3 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait VgatherdpsEmitter_2<A, B> {
    fn vgatherdps_2(&mut self, op0: A, op1: B);
}

impl<'a> VgatherdpsEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vgatherdps_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGATHERDPS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgatherdpsEmitter_2<Ymm, Mem> for Assembler<'a> {
    fn vgatherdps_2(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGATHERDPS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgatherdpsEmitter_2<Zmm, Mem> for Assembler<'a> {
    fn vgatherdps_2(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGATHERDPS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGATHERQPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// | 3 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait VgatherqpdEmitter_2<A, B> {
    fn vgatherqpd_2(&mut self, op0: A, op1: B);
}

impl<'a> VgatherqpdEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vgatherqpd_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGATHERQPD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgatherqpdEmitter_2<Ymm, Mem> for Assembler<'a> {
    fn vgatherqpd_2(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGATHERQPD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgatherqpdEmitter_2<Zmm, Mem> for Assembler<'a> {
    fn vgatherqpd_2(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGATHERQPD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGATHERQPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// +---+----------+
/// ```
pub trait VgatherqpsEmitter_2<A, B> {
    fn vgatherqps_2(&mut self, op0: A, op1: B);
}

impl<'a> VgatherqpsEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vgatherqps_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGATHERQPS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgatherqpsEmitter_2<Ymm, Mem> for Assembler<'a> {
    fn vgatherqps_2(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGATHERQPS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppdEmitter<A, B> {
    fn vgetexppd(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vgetexppd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VGETEXPPD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vgetexppd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGETEXPPD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vgetexppd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VGETEXPPD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vgetexppd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGETEXPPD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexppd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vgetexppd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGETEXPPD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppdMaskEmitter<A, B> {
    fn vgetexppd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vgetexppd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VGETEXPPD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vgetexppd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGETEXPPD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vgetexppd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VGETEXPPD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vgetexppd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGETEXPPD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexppd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vgetexppd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGETEXPPD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppdMaskSaeEmitter<A, B> {
    fn vgetexppd_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppdMaskSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexppd_mask_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPD512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppdMaskzEmitter<A, B> {
    fn vgetexppd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vgetexppd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VGETEXPPD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vgetexppd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGETEXPPD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vgetexppd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VGETEXPPD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vgetexppd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGETEXPPD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexppd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vgetexppd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGETEXPPD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppdMaskzSaeEmitter<A, B> {
    fn vgetexppd_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppdMaskzSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexppd_maskz_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPD512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppdSaeEmitter<A, B> {
    fn vgetexppd_sae(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppdSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexppd_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPD512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppsEmitter<A, B> {
    fn vgetexpps(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppsEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vgetexpps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VGETEXPPS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsEmitter<Xmm, Mem> for Assembler<'a> {
    fn vgetexpps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGETEXPPS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vgetexpps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VGETEXPPS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsEmitter<Ymm, Mem> for Assembler<'a> {
    fn vgetexpps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGETEXPPS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexpps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsEmitter<Zmm, Mem> for Assembler<'a> {
    fn vgetexpps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGETEXPPS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppsMaskEmitter<A, B> {
    fn vgetexpps_mask(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppsMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vgetexpps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VGETEXPPS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vgetexpps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGETEXPPS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vgetexpps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VGETEXPPS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vgetexpps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGETEXPPS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexpps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vgetexpps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGETEXPPS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppsMaskSaeEmitter<A, B> {
    fn vgetexpps_mask_sae(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppsMaskSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexpps_mask_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPS512RR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppsMaskzEmitter<A, B> {
    fn vgetexpps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppsMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vgetexpps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VGETEXPPS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vgetexpps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VGETEXPPS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vgetexpps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VGETEXPPS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vgetexpps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VGETEXPPS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexpps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VgetexppsMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vgetexpps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VGETEXPPS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppsMaskzSaeEmitter<A, B> {
    fn vgetexpps_maskz_sae(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppsMaskzSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexpps_maskz_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPS512RR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPPS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VgetexppsSaeEmitter<A, B> {
    fn vgetexpps_sae(&mut self, op0: A, op1: B);
}

impl<'a> VgetexppsSaeEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vgetexpps_sae(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VGETEXPPS512RR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VGETEXPSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpsdEmitter<A, B, C> {
    fn vgetexpsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetexpsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vgetexpsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VGETEXPSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpsdMaskEmitter<A, B, C> {
    fn vgetexpsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetexpsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vgetexpsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VGETEXPSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpsdMaskSaeEmitter<A, B, C> {
    fn vgetexpsd_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpsdMaskSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpsd_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSDRRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpsdMaskzEmitter<A, B, C> {
    fn vgetexpsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetexpsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vgetexpsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VGETEXPSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpsdMaskzSaeEmitter<A, B, C> {
    fn vgetexpsd_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpsdMaskzSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpsd_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSDRRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpsdSaeEmitter<A, B, C> {
    fn vgetexpsd_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpsdSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpsd_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSDRRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpssEmitter<A, B, C> {
    fn vgetexpss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetexpssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vgetexpss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VGETEXPSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpssMaskEmitter<A, B, C> {
    fn vgetexpss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetexpssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vgetexpss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VGETEXPSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpssMaskSaeEmitter<A, B, C> {
    fn vgetexpss_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpssMaskSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpss_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSSRRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpssMaskzEmitter<A, B, C> {
    fn vgetexpss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetexpssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vgetexpss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VGETEXPSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpssMaskzSaeEmitter<A, B, C> {
    fn vgetexpss_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpssMaskzSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpss_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSSRRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETEXPSS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VgetexpssSaeEmitter<A, B, C> {
    fn vgetexpss_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetexpssSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vgetexpss_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VGETEXPSSRRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpdEmitter<A, B, C> {
    fn vgetmantpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpdEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantpd(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VGETMANTPD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vgetmantpd(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VGETMANTPD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantpd(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpdMaskEmitter<A, B, C> {
    fn vgetmantpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpdMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VGETMANTPD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vgetmantpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VGETMANTPD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpdMaskSaeEmitter<A, B, C> {
    fn vgetmantpd_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpdMaskSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantpd_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPD512RRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpdMaskzEmitter<A, B, C> {
    fn vgetmantpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpdMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VGETMANTPD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vgetmantpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VGETMANTPD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpdMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantpd_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpdMaskzSaeEmitter<A, B, C> {
    fn vgetmantpd_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpdMaskzSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantpd_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPD512RRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpdSaeEmitter<A, B, C> {
    fn vgetmantpd_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpdSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantpd_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPD512RRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpsEmitter<A, B, C> {
    fn vgetmantps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpsEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantps(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VGETMANTPS128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vgetmantps(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VGETMANTPS256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantps(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPS512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpsMaskEmitter<A, B, C> {
    fn vgetmantps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpsMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VGETMANTPS128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vgetmantps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VGETMANTPS256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPS512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpsMaskSaeEmitter<A, B, C> {
    fn vgetmantps_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpsMaskSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantps_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPS512RRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpsMaskzEmitter<A, B, C> {
    fn vgetmantps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpsMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VGETMANTPS128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vgetmantps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VGETMANTPS256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPS512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VgetmantpsMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantps_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VGETMANTPS512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpsMaskzSaeEmitter<A, B, C> {
    fn vgetmantps_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpsMaskzSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantps_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPS512RRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTPS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VgetmantpsSaeEmitter<A, B, C> {
    fn vgetmantps_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VgetmantpsSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vgetmantps_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VGETMANTPS512RRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VGETMANTSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantsdEmitter<A, B, C, D> {
    fn vgetmantsd(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantsdEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSDRRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VgetmantsdEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VGETMANTSDRRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantsdMaskEmitter<A, B, C, D> {
    fn vgetmantsd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantsdMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSDRRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VgetmantsdMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VGETMANTSDRRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantsdMaskSaeEmitter<A, B, C, D> {
    fn vgetmantsd_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantsdMaskSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantsd_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSDRRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantsdMaskzEmitter<A, B, C, D> {
    fn vgetmantsd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantsdMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSDRRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VgetmantsdMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VGETMANTSDRRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantsdMaskzSaeEmitter<A, B, C, D> {
    fn vgetmantsd_maskz_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantsdMaskzSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantsd_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSDRRRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantsdSaeEmitter<A, B, C, D> {
    fn vgetmantsd_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantsdSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantsd_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSDRRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantssEmitter<A, B, C, D> {
    fn vgetmantss(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantssEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSSRRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VgetmantssEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantss(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VGETMANTSSRRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantssMaskEmitter<A, B, C, D> {
    fn vgetmantss_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantssMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSSRRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VgetmantssMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VGETMANTSSRRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantssMaskSaeEmitter<A, B, C, D> {
    fn vgetmantss_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantssMaskSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantss_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSSRRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantssMaskzEmitter<A, B, C, D> {
    fn vgetmantss_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantssMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSSRRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VgetmantssMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vgetmantss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VGETMANTSSRRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantssMaskzSaeEmitter<A, B, C, D> {
    fn vgetmantss_maskz_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantssMaskzSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantss_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSSRRRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VGETMANTSS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VgetmantssSaeEmitter<A, B, C, D> {
    fn vgetmantss_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VgetmantssSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vgetmantss_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VGETMANTSSRRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTF32X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Xmm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinsertf32x4Emitter<A, B, C, D> {
    fn vinsertf32x4(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinsertf32x4Emitter<Ymm, Ymm, Xmm, Imm> for Assembler<'a> {
    fn vinsertf32x4(&mut self, op0: Ymm, op1: Ymm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTF32X4_256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4Emitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vinsertf32x4(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF32X4_256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4Emitter<Zmm, Zmm, Xmm, Imm> for Assembler<'a> {
    fn vinsertf32x4(&mut self, op0: Zmm, op1: Zmm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTF32X4_512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4Emitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinsertf32x4(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF32X4_512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTF32X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Xmm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinsertf32x4MaskEmitter<A, B, C, D> {
    fn vinsertf32x4_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinsertf32x4MaskEmitter<Ymm, Ymm, Xmm, Imm> for Assembler<'a> {
    fn vinsertf32x4_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTF32X4_256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4MaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vinsertf32x4_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF32X4_256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4MaskEmitter<Zmm, Zmm, Xmm, Imm> for Assembler<'a> {
    fn vinsertf32x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTF32X4_512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4MaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinsertf32x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF32X4_512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTF32X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Xmm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinsertf32x4MaskzEmitter<A, B, C, D> {
    fn vinsertf32x4_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinsertf32x4MaskzEmitter<Ymm, Ymm, Xmm, Imm> for Assembler<'a> {
    fn vinsertf32x4_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTF32X4_256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4MaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vinsertf32x4_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF32X4_256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4MaskzEmitter<Zmm, Zmm, Xmm, Imm> for Assembler<'a> {
    fn vinsertf32x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTF32X4_512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf32x4MaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinsertf32x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF32X4_512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTF64X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Mem, Imm |
/// | 2 | Zmm, Zmm, Ymm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinsertf64x4Emitter<A, B, C, D> {
    fn vinsertf64x4(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinsertf64x4Emitter<Zmm, Zmm, Ymm, Imm> for Assembler<'a> {
    fn vinsertf64x4(&mut self, op0: Zmm, op1: Zmm, op2: Ymm, op3: Imm) {
        self.emit(
            VINSERTF64X4_512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf64x4Emitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinsertf64x4(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF64X4_512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTF64X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Mem, Imm |
/// | 2 | Zmm, Zmm, Ymm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinsertf64x4MaskEmitter<A, B, C, D> {
    fn vinsertf64x4_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinsertf64x4MaskEmitter<Zmm, Zmm, Ymm, Imm> for Assembler<'a> {
    fn vinsertf64x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Ymm, op3: Imm) {
        self.emit(
            VINSERTF64X4_512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf64x4MaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinsertf64x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF64X4_512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTF64X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Mem, Imm |
/// | 2 | Zmm, Zmm, Ymm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinsertf64x4MaskzEmitter<A, B, C, D> {
    fn vinsertf64x4_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinsertf64x4MaskzEmitter<Zmm, Zmm, Ymm, Imm> for Assembler<'a> {
    fn vinsertf64x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Ymm, op3: Imm) {
        self.emit(
            VINSERTF64X4_512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinsertf64x4MaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinsertf64x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTF64X4_512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTI32X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Xmm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinserti32x4Emitter<A, B, C, D> {
    fn vinserti32x4(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinserti32x4Emitter<Ymm, Ymm, Xmm, Imm> for Assembler<'a> {
    fn vinserti32x4(&mut self, op0: Ymm, op1: Ymm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTI32X4_256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4Emitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vinserti32x4(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI32X4_256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4Emitter<Zmm, Zmm, Xmm, Imm> for Assembler<'a> {
    fn vinserti32x4(&mut self, op0: Zmm, op1: Zmm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTI32X4_512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4Emitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinserti32x4(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI32X4_512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTI32X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Xmm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinserti32x4MaskEmitter<A, B, C, D> {
    fn vinserti32x4_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinserti32x4MaskEmitter<Ymm, Ymm, Xmm, Imm> for Assembler<'a> {
    fn vinserti32x4_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTI32X4_256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4MaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vinserti32x4_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI32X4_256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4MaskEmitter<Zmm, Zmm, Xmm, Imm> for Assembler<'a> {
    fn vinserti32x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTI32X4_512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4MaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinserti32x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI32X4_512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTI32X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Xmm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinserti32x4MaskzEmitter<A, B, C, D> {
    fn vinserti32x4_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinserti32x4MaskzEmitter<Ymm, Ymm, Xmm, Imm> for Assembler<'a> {
    fn vinserti32x4_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTI32X4_256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4MaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vinserti32x4_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI32X4_256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4MaskzEmitter<Zmm, Zmm, Xmm, Imm> for Assembler<'a> {
    fn vinserti32x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTI32X4_512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti32x4MaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinserti32x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI32X4_512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTI64X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Mem, Imm |
/// | 2 | Zmm, Zmm, Ymm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinserti64x4Emitter<A, B, C, D> {
    fn vinserti64x4(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinserti64x4Emitter<Zmm, Zmm, Ymm, Imm> for Assembler<'a> {
    fn vinserti64x4(&mut self, op0: Zmm, op1: Zmm, op2: Ymm, op3: Imm) {
        self.emit(
            VINSERTI64X4_512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti64x4Emitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinserti64x4(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI64X4_512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTI64X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Mem, Imm |
/// | 2 | Zmm, Zmm, Ymm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinserti64x4MaskEmitter<A, B, C, D> {
    fn vinserti64x4_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinserti64x4MaskEmitter<Zmm, Zmm, Ymm, Imm> for Assembler<'a> {
    fn vinserti64x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Ymm, op3: Imm) {
        self.emit(
            VINSERTI64X4_512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti64x4MaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinserti64x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI64X4_512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTI64X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Zmm, Zmm, Mem, Imm |
/// | 2 | Zmm, Zmm, Ymm, Imm |
/// +---+--------------------+
/// ```
pub trait Vinserti64x4MaskzEmitter<A, B, C, D> {
    fn vinserti64x4_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vinserti64x4MaskzEmitter<Zmm, Zmm, Ymm, Imm> for Assembler<'a> {
    fn vinserti64x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Ymm, op3: Imm) {
        self.emit(
            VINSERTI64X4_512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vinserti64x4MaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vinserti64x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTI64X4_512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VINSERTPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VinsertpsEmitter<A, B, C, D> {
    fn vinsertps(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VinsertpsEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vinsertps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VINSERTPSRRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VinsertpsEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vinsertps(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VINSERTPSRRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VMAXPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpdEmitter<A, B, C> {
    fn vmaxpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmaxpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMAXPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmaxpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMAXPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmaxpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMAXPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpdMaskEmitter<A, B, C> {
    fn vmaxpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmaxpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMAXPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmaxpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMAXPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmaxpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMAXPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpdMaskSaeEmitter<A, B, C> {
    fn vmaxpd_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpdMaskSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxpd_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPD512RRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpdMaskzEmitter<A, B, C> {
    fn vmaxpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmaxpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMAXPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmaxpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMAXPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmaxpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMAXPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpdMaskzSaeEmitter<A, B, C> {
    fn vmaxpd_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpdMaskzSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxpd_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPD512RRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpdSaeEmitter<A, B, C> {
    fn vmaxpd_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpdSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxpd_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPD512RRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpsEmitter<A, B, C> {
    fn vmaxps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmaxps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMAXPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmaxps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMAXPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmaxps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMAXPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpsMaskEmitter<A, B, C> {
    fn vmaxps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmaxps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMAXPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmaxps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMAXPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmaxps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMAXPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpsMaskSaeEmitter<A, B, C> {
    fn vmaxps_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpsMaskSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxps_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPS512RRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpsMaskzEmitter<A, B, C> {
    fn vmaxps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmaxps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMAXPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmaxps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMAXPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmaxps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMAXPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpsMaskzSaeEmitter<A, B, C> {
    fn vmaxps_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpsMaskzSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxps_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPS512RRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXPS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmaxpsSaeEmitter<A, B, C> {
    fn vmaxps_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxpsSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmaxps_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMAXPS512RRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxsdEmitter<A, B, C> {
    fn vmaxsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxsdMaskEmitter<A, B, C> {
    fn vmaxsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxsdMaskSaeEmitter<A, B, C> {
    fn vmaxsd_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxsdMaskSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxsd_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSDRRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxsdMaskzEmitter<A, B, C> {
    fn vmaxsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxsdMaskzSaeEmitter<A, B, C> {
    fn vmaxsd_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxsdMaskzSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxsd_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSDRRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxsdSaeEmitter<A, B, C> {
    fn vmaxsd_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxsdSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxsd_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSDRRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxssEmitter<A, B, C> {
    fn vmaxss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxssMaskEmitter<A, B, C> {
    fn vmaxss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxssMaskSaeEmitter<A, B, C> {
    fn vmaxss_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxssMaskSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxss_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSSRRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxssMaskzEmitter<A, B, C> {
    fn vmaxss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmaxssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmaxss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMAXSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxssMaskzSaeEmitter<A, B, C> {
    fn vmaxss_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxssMaskzSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxss_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSSRRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMAXSS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmaxssSaeEmitter<A, B, C> {
    fn vmaxss_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmaxssSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmaxss_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMAXSSRRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpdEmitter<A, B, C> {
    fn vminpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vminpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMINPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vminpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMINPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vminpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMINPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpdMaskEmitter<A, B, C> {
    fn vminpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vminpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMINPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vminpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMINPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vminpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMINPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpdMaskSaeEmitter<A, B, C> {
    fn vminpd_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpdMaskSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminpd_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPD512RRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpdMaskzEmitter<A, B, C> {
    fn vminpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vminpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMINPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vminpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMINPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vminpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMINPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpdMaskzSaeEmitter<A, B, C> {
    fn vminpd_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpdMaskzSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminpd_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPD512RRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpdSaeEmitter<A, B, C> {
    fn vminpd_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpdSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminpd_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPD512RRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpsEmitter<A, B, C> {
    fn vminps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vminps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMINPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vminps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMINPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vminps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMINPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpsMaskEmitter<A, B, C> {
    fn vminps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vminps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMINPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vminps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMINPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vminps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMINPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpsMaskSaeEmitter<A, B, C> {
    fn vminps_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpsMaskSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminps_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPS512RRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpsMaskzEmitter<A, B, C> {
    fn vminps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vminps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMINPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vminps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMINPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vminps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMINPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpsMaskzSaeEmitter<A, B, C> {
    fn vminps_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpsMaskzSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminps_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPS512RRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINPS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VminpsSaeEmitter<A, B, C> {
    fn vminps_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminpsSaeEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vminps_sae(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMINPS512RRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminsdEmitter<A, B, C> {
    fn vminsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminsdMaskEmitter<A, B, C> {
    fn vminsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminsdMaskSaeEmitter<A, B, C> {
    fn vminsd_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminsdMaskSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminsd_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSDRRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminsdMaskzEmitter<A, B, C> {
    fn vminsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminsdMaskzSaeEmitter<A, B, C> {
    fn vminsd_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminsdMaskzSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminsd_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSDRRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminsdSaeEmitter<A, B, C> {
    fn vminsd_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminsdSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminsd_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSDRRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminssEmitter<A, B, C> {
    fn vminss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminssMaskEmitter<A, B, C> {
    fn vminss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminssMaskSaeEmitter<A, B, C> {
    fn vminss_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminssMaskSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminss_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSSRRR_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminssMaskzEmitter<A, B, C> {
    fn vminss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VminssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vminss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMINSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminssMaskzSaeEmitter<A, B, C> {
    fn vminss_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminssMaskzSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminss_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSSRRR_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMINSS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VminssSaeEmitter<A, B, C> {
    fn vminss_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VminssSaeEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vminss_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMINSSRRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVAPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovapdEmitter<A, B> {
    fn vmovapd(&mut self, op0: A, op1: B);
}

impl<'a> VmovapdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVAPD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVAPD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVAPD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVAPD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVAPD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVAPD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVAPD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVAPD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovapd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVAPD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVAPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovapdMaskEmitter<A, B> {
    fn vmovapd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VmovapdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVAPD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVAPD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVAPD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVAPD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVAPD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVAPD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVAPD128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVAPD256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovapd_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVAPD512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVAPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovapdMaskzEmitter<A, B> {
    fn vmovapd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VmovapdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovapd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVAPD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovapd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVAPD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovapd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVAPD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovapd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVAPD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovapd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVAPD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovapd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVAPD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVAPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovapsEmitter<A, B> {
    fn vmovaps(&mut self, op0: A, op1: B);
}

impl<'a> VmovapsEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVAPS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVAPS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVAPS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVAPS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVAPS128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVAPS256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVAPS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVAPS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovaps(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVAPS512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVAPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovapsMaskEmitter<A, B> {
    fn vmovaps_mask(&mut self, op0: A, op1: B);
}

impl<'a> VmovapsMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVAPS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVAPS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVAPS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVAPS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVAPS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVAPS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVAPS128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVAPS256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovaps_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVAPS512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVAPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovapsMaskzEmitter<A, B> {
    fn vmovaps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VmovapsMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovaps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVAPS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovaps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVAPS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovaps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVAPS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovaps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVAPS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovaps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVAPS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovapsMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovaps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVAPS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDDUP`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovddupEmitter<A, B> {
    fn vmovddup(&mut self, op0: A, op1: B);
}

impl<'a> VmovddupEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovddup(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDDUP128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovddup(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDDUP128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovddup(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDDUP256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovddup(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDDUP256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovddup(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDDUP512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovddup(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDDUP512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDDUP_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovddupMaskEmitter<A, B> {
    fn vmovddup_mask(&mut self, op0: A, op1: B);
}

impl<'a> VmovddupMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovddup_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDDUP128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovddup_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDDUP128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovddup_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDDUP256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovddup_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDDUP256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovddup_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDDUP512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovddup_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDDUP512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDDUP_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovddupMaskzEmitter<A, B> {
    fn vmovddup_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VmovddupMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovddup_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDDUP128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovddup_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDDUP128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovddup_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDDUP256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovddup_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDDUP256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovddup_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDDUP512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovddupMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovddup_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDDUP512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQA32`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqa32Emitter<A, B> {
    fn vmovdqa32(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqa32Emitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQA32_128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32Emitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQA32_128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32Emitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQA32_256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32Emitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQA32_256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32Emitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQA32_512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32Emitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQA32_512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32Emitter<Mem, Xmm> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVDQA32_128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32Emitter<Mem, Ymm> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVDQA32_256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32Emitter<Mem, Zmm> for Assembler<'a> {
    fn vmovdqa32(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVDQA32_512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQA32_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqa32MaskEmitter<A, B> {
    fn vmovdqa32_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqa32MaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQA32_128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQA32_128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQA32_256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQA32_256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQA32_512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQA32_512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVDQA32_128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVDQA32_256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovdqa32_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVDQA32_512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQA32_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqa32MaskzEmitter<A, B> {
    fn vmovdqa32_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqa32MaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqa32_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQA32_128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqa32_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQA32_128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqa32_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQA32_256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqa32_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQA32_256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqa32_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQA32_512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa32MaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqa32_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQA32_512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQA64`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqa64Emitter<A, B> {
    fn vmovdqa64(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqa64Emitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQA64_128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64Emitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQA64_128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64Emitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQA64_256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64Emitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQA64_256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64Emitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQA64_512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64Emitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQA64_512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64Emitter<Mem, Xmm> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVDQA64_128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64Emitter<Mem, Ymm> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVDQA64_256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64Emitter<Mem, Zmm> for Assembler<'a> {
    fn vmovdqa64(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVDQA64_512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQA64_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqa64MaskEmitter<A, B> {
    fn vmovdqa64_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqa64MaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQA64_128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQA64_128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQA64_256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQA64_256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQA64_512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQA64_512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVDQA64_128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVDQA64_256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovdqa64_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVDQA64_512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQA64_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqa64MaskzEmitter<A, B> {
    fn vmovdqa64_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqa64MaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqa64_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQA64_128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqa64_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQA64_128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqa64_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQA64_256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqa64_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQA64_256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqa64_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQA64_512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqa64MaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqa64_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQA64_512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQU32`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqu32Emitter<A, B> {
    fn vmovdqu32(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqu32Emitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQU32_128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32Emitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQU32_128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32Emitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQU32_256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32Emitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQU32_256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32Emitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQU32_512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32Emitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQU32_512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32Emitter<Mem, Xmm> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVDQU32_128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32Emitter<Mem, Ymm> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVDQU32_256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32Emitter<Mem, Zmm> for Assembler<'a> {
    fn vmovdqu32(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVDQU32_512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQU32_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqu32MaskEmitter<A, B> {
    fn vmovdqu32_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqu32MaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQU32_128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQU32_128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQU32_256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQU32_256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQU32_512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQU32_512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVDQU32_128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVDQU32_256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovdqu32_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVDQU32_512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQU32_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqu32MaskzEmitter<A, B> {
    fn vmovdqu32_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqu32MaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqu32_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQU32_128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqu32_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQU32_128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqu32_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQU32_256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqu32_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQU32_256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqu32_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQU32_512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu32MaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqu32_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQU32_512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQU64`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqu64Emitter<A, B> {
    fn vmovdqu64(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqu64Emitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQU64_128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64Emitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQU64_128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64Emitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQU64_256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64Emitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQU64_256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64Emitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQU64_512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64Emitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQU64_512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64Emitter<Mem, Xmm> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVDQU64_128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64Emitter<Mem, Ymm> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVDQU64_256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64Emitter<Mem, Zmm> for Assembler<'a> {
    fn vmovdqu64(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVDQU64_512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQU64_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqu64MaskEmitter<A, B> {
    fn vmovdqu64_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqu64MaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQU64_128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQU64_128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQU64_256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQU64_256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQU64_512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQU64_512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVDQU64_128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVDQU64_256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovdqu64_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVDQU64_512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVDQU64_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vmovdqu64MaskzEmitter<A, B> {
    fn vmovdqu64_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vmovdqu64MaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovdqu64_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVDQU64_128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovdqu64_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVDQU64_128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovdqu64_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVDQU64_256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovdqu64_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVDQU64_256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovdqu64_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVDQU64_512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vmovdqu64MaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovdqu64_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVDQU64_512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVHLPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmovhlpsEmitter<A, B, C> {
    fn vmovhlps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovhlpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmovhlps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMOVHLPSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVHPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// +---+----------+
/// ```
pub trait VmovhpdEmitter_2<A, B> {
    fn vmovhpd_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovhpdEmitter_2<Mem, Xmm> for Assembler<'a> {
    fn vmovhpd_2(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVHPDMR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVHPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// +---+---------------+
/// ```
pub trait VmovhpdEmitter_3<A, B, C> {
    fn vmovhpd_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovhpdEmitter_3<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmovhpd_3(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMOVHPDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVHPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// +---+----------+
/// ```
pub trait VmovhpsEmitter_2<A, B> {
    fn vmovhps_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovhpsEmitter_2<Mem, Xmm> for Assembler<'a> {
    fn vmovhps_2(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVHPSMR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVHPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// +---+---------------+
/// ```
pub trait VmovhpsEmitter_3<A, B, C> {
    fn vmovhps_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovhpsEmitter_3<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmovhps_3(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMOVHPSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVLHPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmovlhpsEmitter<A, B, C> {
    fn vmovlhps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovlhpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmovlhps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMOVLHPSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVLPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// +---+----------+
/// ```
pub trait VmovlpdEmitter_2<A, B> {
    fn vmovlpd_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovlpdEmitter_2<Mem, Xmm> for Assembler<'a> {
    fn vmovlpd_2(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVLPDMR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVLPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// +---+---------------+
/// ```
pub trait VmovlpdEmitter_3<A, B, C> {
    fn vmovlpd_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovlpdEmitter_3<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmovlpd_3(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMOVLPDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVLPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// +---+----------+
/// ```
pub trait VmovlpsEmitter_2<A, B> {
    fn vmovlps_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovlpsEmitter_2<Mem, Xmm> for Assembler<'a> {
    fn vmovlps_2(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVLPSMR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVLPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// +---+---------------+
/// ```
pub trait VmovlpsEmitter_3<A, B, C> {
    fn vmovlps_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovlpsEmitter_3<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmovlps_3(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMOVLPSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVNTDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VmovntdqEmitter<A, B> {
    fn vmovntdq(&mut self, op0: A, op1: B);
}

impl<'a> VmovntdqEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovntdq(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVNTDQ128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovntdqEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovntdq(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVNTDQ256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovntdqEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovntdq(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVNTDQ512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVNTDQA`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// | 3 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait VmovntdqaEmitter<A, B> {
    fn vmovntdqa(&mut self, op0: A, op1: B);
}

impl<'a> VmovntdqaEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovntdqa(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVNTDQA128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovntdqaEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovntdqa(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVNTDQA256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovntdqaEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovntdqa(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVNTDQA512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVNTPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VmovntpdEmitter<A, B> {
    fn vmovntpd(&mut self, op0: A, op1: B);
}

impl<'a> VmovntpdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovntpd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVNTPD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovntpdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovntpd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVNTPD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovntpdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovntpd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVNTPD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVNTPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VmovntpsEmitter<A, B> {
    fn vmovntps(&mut self, op0: A, op1: B);
}

impl<'a> VmovntpsEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovntps(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVNTPS128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovntpsEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovntps(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVNTPS256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovntpsEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovntps(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVNTPS512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Xmm, Mem |
/// | 3 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VmovqEmitter<A, B> {
    fn vmovq(&mut self, op0: A, op1: B);
}

impl<'a> VmovqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(VMOVQRR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

impl<'a> VmovqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(VMOVQRM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

impl<'a> VmovqEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovq(&mut self, op0: Mem, op1: Xmm) {
        self.emit(VMOVQMR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

/// `VMOVSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Xmm, Mem |
/// +---+----------+
/// ```
pub trait VmovsdEmitter_2<A, B> {
    fn vmovsd_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovsdEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vmovsd_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(VMOVSDRM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

impl<'a> VmovsdEmitter_2<Mem, Xmm> for Assembler<'a> {
    fn vmovsd_2(&mut self, op0: Mem, op1: Xmm) {
        self.emit(VMOVSDMR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

/// `VMOVSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmovsdEmitter_3<A, B, C> {
    fn vmovsd_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovsdEmitter_3<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmovsd_3(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMOVSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Xmm, Mem |
/// +---+----------+
/// ```
pub trait VmovsdMaskEmitter_2<A, B> {
    fn vmovsd_mask_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovsdMaskEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vmovsd_mask_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSDRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsdMaskEmitter_2<Mem, Xmm> for Assembler<'a> {
    fn vmovsd_mask_2(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVSDMR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmovsdMaskEmitter_3<A, B, C> {
    fn vmovsd_mask_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovsdMaskEmitter_3<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmovsd_mask_3(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMOVSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// +---+----------+
/// ```
pub trait VmovsdMaskzEmitter_2<A, B> {
    fn vmovsd_maskz_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovsdMaskzEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vmovsd_maskz_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSDRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmovsdMaskzEmitter_3<A, B, C> {
    fn vmovsd_maskz_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovsdMaskzEmitter_3<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmovsd_maskz_3(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMOVSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVSHDUP`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovshdupEmitter<A, B> {
    fn vmovshdup(&mut self, op0: A, op1: B);
}

impl<'a> VmovshdupEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovshdup(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVSHDUP128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovshdup(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSHDUP128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovshdup(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVSHDUP256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovshdup(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVSHDUP256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovshdup(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVSHDUP512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovshdup(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVSHDUP512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSHDUP_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovshdupMaskEmitter<A, B> {
    fn vmovshdup_mask(&mut self, op0: A, op1: B);
}

impl<'a> VmovshdupMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovshdup_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVSHDUP128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovshdup_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSHDUP128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovshdup_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVSHDUP256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovshdup_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVSHDUP256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovshdup_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVSHDUP512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovshdup_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVSHDUP512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSHDUP_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovshdupMaskzEmitter<A, B> {
    fn vmovshdup_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VmovshdupMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovshdup_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVSHDUP128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovshdup_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSHDUP128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovshdup_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVSHDUP256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovshdup_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVSHDUP256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovshdup_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVSHDUP512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovshdupMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovshdup_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVSHDUP512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSLDUP`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovsldupEmitter<A, B> {
    fn vmovsldup(&mut self, op0: A, op1: B);
}

impl<'a> VmovsldupEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovsldup(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVSLDUP128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovsldup(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSLDUP128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovsldup(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVSLDUP256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovsldup(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVSLDUP256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovsldup(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVSLDUP512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovsldup(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVSLDUP512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSLDUP_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovsldupMaskEmitter<A, B> {
    fn vmovsldup_mask(&mut self, op0: A, op1: B);
}

impl<'a> VmovsldupMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovsldup_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVSLDUP128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovsldup_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSLDUP128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovsldup_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVSLDUP256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovsldup_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVSLDUP256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovsldup_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVSLDUP512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovsldup_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVSLDUP512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSLDUP_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovsldupMaskzEmitter<A, B> {
    fn vmovsldup_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VmovsldupMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovsldup_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVSLDUP128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovsldup_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSLDUP128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovsldup_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVSLDUP256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovsldup_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVSLDUP256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovsldup_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVSLDUP512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovsldupMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovsldup_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVSLDUP512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Xmm, Mem |
/// +---+----------+
/// ```
pub trait VmovssEmitter_2<A, B> {
    fn vmovss_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovssEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vmovss_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(VMOVSSRM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

impl<'a> VmovssEmitter_2<Mem, Xmm> for Assembler<'a> {
    fn vmovss_2(&mut self, op0: Mem, op1: Xmm) {
        self.emit(VMOVSSMR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
    }
}

/// `VMOVSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmovssEmitter_3<A, B, C> {
    fn vmovss_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovssEmitter_3<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmovss_3(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMOVSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Xmm, Mem |
/// +---+----------+
/// ```
pub trait VmovssMaskEmitter_2<A, B> {
    fn vmovss_mask_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovssMaskEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vmovss_mask_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSSRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovssMaskEmitter_2<Mem, Xmm> for Assembler<'a> {
    fn vmovss_mask_2(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVSSMR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmovssMaskEmitter_3<A, B, C> {
    fn vmovss_mask_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovssMaskEmitter_3<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmovss_mask_3(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMOVSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// +---+----------+
/// ```
pub trait VmovssMaskzEmitter_2<A, B> {
    fn vmovss_maskz_2(&mut self, op0: A, op1: B);
}

impl<'a> VmovssMaskzEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vmovss_maskz_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVSSRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmovssMaskzEmitter_3<A, B, C> {
    fn vmovss_maskz_3(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmovssMaskzEmitter_3<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmovss_maskz_3(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMOVSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMOVUPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovupdEmitter<A, B> {
    fn vmovupd(&mut self, op0: A, op1: B);
}

impl<'a> VmovupdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVUPD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVUPD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVUPD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVUPD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVUPD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVUPD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVUPD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVUPD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovupd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVUPD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVUPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovupdMaskEmitter<A, B> {
    fn vmovupd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VmovupdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVUPD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVUPD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVUPD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVUPD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVUPD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVUPD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVUPD128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVUPD256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovupd_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVUPD512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVUPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovupdMaskzEmitter<A, B> {
    fn vmovupd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VmovupdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovupd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVUPD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovupd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVUPD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovupd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVUPD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovupd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVUPD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovupd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVUPD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovupd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVUPD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVUPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovupsEmitter<A, B> {
    fn vmovups(&mut self, op0: A, op1: B);
}

impl<'a> VmovupsEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovups(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVUPS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovups(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVUPS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovups(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVUPS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovups(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVUPS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovups(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVUPS128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovups(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVUPS256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovups(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVUPS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovups(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVUPS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovups(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVUPS512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVUPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Mem |
/// | 5 | Xmm, Xmm |
/// | 6 | Ymm, Mem |
/// | 7 | Ymm, Ymm |
/// | 8 | Zmm, Mem |
/// | 9 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovupsMaskEmitter<A, B> {
    fn vmovups_mask(&mut self, op0: A, op1: B);
}

impl<'a> VmovupsMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVUPS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVUPS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVUPS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVUPS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVUPS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVUPS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VMOVUPS128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VMOVUPS256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vmovups_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VMOVUPS512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMOVUPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VmovupsMaskzEmitter<A, B> {
    fn vmovups_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VmovupsMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vmovups_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VMOVUPS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vmovups_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VMOVUPS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vmovups_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VMOVUPS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vmovups_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VMOVUPS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vmovups_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VMOVUPS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VmovupsMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vmovups_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VMOVUPS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VMULPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpdEmitter<A, B, C> {
    fn vmulpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmulpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMULPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmulpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMULPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmulpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMULPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpdErEmitter<A, B, C> {
    fn vmulpd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulpd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpdMaskEmitter<A, B, C> {
    fn vmulpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmulpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMULPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmulpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMULPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmulpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMULPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpdMaskErEmitter<A, B, C> {
    fn vmulpd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulpd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpdMaskzEmitter<A, B, C> {
    fn vmulpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmulpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMULPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmulpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMULPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmulpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMULPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpdMaskzErEmitter<A, B, C> {
    fn vmulpd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulpd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpsEmitter<A, B, C> {
    fn vmulps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmulps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMULPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmulps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMULPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmulps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMULPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpsErEmitter<A, B, C> {
    fn vmulps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpsErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpsMaskEmitter<A, B, C> {
    fn vmulps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmulps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMULPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmulps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMULPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmulps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMULPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpsMaskErEmitter<A, B, C> {
    fn vmulps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpsMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpsMaskzEmitter<A, B, C> {
    fn vmulps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vmulps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VMULPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vmulps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VMULPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vmulps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VMULPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULPS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VmulpsMaskzErEmitter<A, B, C> {
    fn vmulps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulpsMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vmulps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VMULPS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulsdEmitter<A, B, C> {
    fn vmulsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulsdErEmitter<A, B, C> {
    fn vmulsd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulsdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulsd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulsdMaskEmitter<A, B, C> {
    fn vmulsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulsdMaskErEmitter<A, B, C> {
    fn vmulsd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulsdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulsd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulsdMaskzEmitter<A, B, C> {
    fn vmulsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulsdMaskzErEmitter<A, B, C> {
    fn vmulsd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulsdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulsd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulssEmitter<A, B, C> {
    fn vmulss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulssErEmitter<A, B, C> {
    fn vmulss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulssMaskEmitter<A, B, C> {
    fn vmulss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulssMaskErEmitter<A, B, C> {
    fn vmulss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulssMaskzEmitter<A, B, C> {
    fn vmulss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VmulssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vmulss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VMULSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VMULSS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VmulssMaskzErEmitter<A, B, C> {
    fn vmulss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VmulssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vmulss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VMULSSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPABSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpabsdEmitter<A, B> {
    fn vpabsd(&mut self, op0: A, op1: B);
}

impl<'a> VpabsdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpabsd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPABSD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpabsd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPABSD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpabsd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPABSD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpabsd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPABSD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpabsd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPABSD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpabsd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPABSD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPABSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpabsdMaskEmitter<A, B> {
    fn vpabsd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpabsdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpabsd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPABSD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpabsd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPABSD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpabsd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPABSD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpabsd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPABSD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpabsd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPABSD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpabsd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPABSD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPABSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpabsdMaskzEmitter<A, B> {
    fn vpabsd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpabsdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpabsd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPABSD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpabsd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPABSD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpabsd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPABSD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpabsd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPABSD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpabsd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPABSD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpabsd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPABSD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPABSQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpabsqEmitter<A, B> {
    fn vpabsq(&mut self, op0: A, op1: B);
}

impl<'a> VpabsqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpabsq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPABSQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpabsq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPABSQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpabsq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPABSQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpabsq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPABSQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpabsq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPABSQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpabsq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPABSQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPABSQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpabsqMaskEmitter<A, B> {
    fn vpabsq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpabsqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpabsq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPABSQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpabsq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPABSQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpabsq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPABSQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpabsq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPABSQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpabsq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPABSQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpabsq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPABSQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPABSQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpabsqMaskzEmitter<A, B> {
    fn vpabsq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpabsqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpabsq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPABSQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpabsq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPABSQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpabsq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPABSQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpabsq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPABSQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpabsq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPABSQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpabsqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpabsq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPABSQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPADDD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpadddEmitter<A, B, C> {
    fn vpaddd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpadddEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpaddd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPADDD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpaddd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPADDD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpaddd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPADDD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpaddd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPADDD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpaddd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPADDD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpaddd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPADDD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPADDD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpadddMaskEmitter<A, B, C> {
    fn vpaddd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpadddMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpaddd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPADDD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpaddd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPADDD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpaddd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPADDD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpaddd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPADDD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpaddd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPADDD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpaddd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPADDD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPADDD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpadddMaskzEmitter<A, B, C> {
    fn vpaddd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpadddMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpaddd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPADDD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpaddd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPADDD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpaddd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPADDD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpaddd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPADDD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpaddd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPADDD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpadddMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpaddd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPADDD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPADDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpaddqEmitter<A, B, C> {
    fn vpaddq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpaddqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpaddq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPADDQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpaddq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPADDQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpaddq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPADDQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpaddq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPADDQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpaddq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPADDQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpaddq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPADDQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPADDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpaddqMaskEmitter<A, B, C> {
    fn vpaddq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpaddqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpaddq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPADDQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpaddq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPADDQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpaddq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPADDQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpaddq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPADDQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpaddq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPADDQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpaddq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPADDQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPADDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpaddqMaskzEmitter<A, B, C> {
    fn vpaddq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpaddqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpaddq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPADDQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpaddq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPADDQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpaddq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPADDQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpaddq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPADDQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpaddq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPADDQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpaddqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpaddq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPADDQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpanddEmitter<A, B, C> {
    fn vpandd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpanddEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpanddMaskEmitter<A, B, C> {
    fn vpandd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpanddMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpanddMaskzEmitter<A, B, C> {
    fn vpandd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpanddMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpanddMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDND`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandndEmitter<A, B, C> {
    fn vpandnd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandndEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandnd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDND128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandnd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDND128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandnd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDND256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandnd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDND256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandnd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDND512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandnd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDND512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDND_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandndMaskEmitter<A, B, C> {
    fn vpandnd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandndMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandnd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDND128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandnd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDND128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandnd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDND256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandnd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDND256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandnd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDND512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandnd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDND512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDND_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandndMaskzEmitter<A, B, C> {
    fn vpandnd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandndMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandnd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDND128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandnd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDND128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandnd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDND256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandnd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDND256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandnd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDND512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandndMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandnd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDND512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDNQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandnqEmitter<A, B, C> {
    fn vpandnq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandnqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandnq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDNQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandnq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDNQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandnq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDNQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandnq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDNQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandnq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDNQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandnq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDNQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDNQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandnqMaskEmitter<A, B, C> {
    fn vpandnq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandnqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandnq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDNQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandnq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDNQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandnq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDNQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandnq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDNQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandnq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDNQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandnq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDNQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDNQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandnqMaskzEmitter<A, B, C> {
    fn vpandnq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandnqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandnq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDNQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandnq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDNQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandnq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDNQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandnq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDNQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandnq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDNQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandnqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandnq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDNQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandqEmitter<A, B, C> {
    fn vpandq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandqMaskEmitter<A, B, C> {
    fn vpandq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPANDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpandqMaskzEmitter<A, B, C> {
    fn vpandq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpandqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpandq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPANDQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpandq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPANDQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpandq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPANDQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpandq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPANDQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpandq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPANDQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpandqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpandq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPANDQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPBLENDMD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpblendmdEmitter<A, B, C> {
    fn vpblendmd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpblendmdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpblendmd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPBLENDMD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpblendmd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPBLENDMD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpblendmd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPBLENDMD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpblendmd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPBLENDMD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpblendmd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPBLENDMD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpblendmd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPBLENDMD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPBLENDMD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpblendmdMaskEmitter<A, B, C> {
    fn vpblendmd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpblendmdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpblendmd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPBLENDMD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpblendmd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPBLENDMD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpblendmd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPBLENDMD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpblendmd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPBLENDMD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpblendmd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPBLENDMD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpblendmd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPBLENDMD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPBLENDMD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpblendmdMaskzEmitter<A, B, C> {
    fn vpblendmd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpblendmdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpblendmd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPBLENDMD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpblendmd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPBLENDMD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpblendmd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPBLENDMD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpblendmd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPBLENDMD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpblendmd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPBLENDMD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpblendmd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPBLENDMD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPBLENDMQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpblendmqEmitter<A, B, C> {
    fn vpblendmq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpblendmqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpblendmq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPBLENDMQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpblendmq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPBLENDMQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpblendmq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPBLENDMQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpblendmq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPBLENDMQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpblendmq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPBLENDMQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpblendmq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPBLENDMQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPBLENDMQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpblendmqMaskEmitter<A, B, C> {
    fn vpblendmq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpblendmqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpblendmq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPBLENDMQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpblendmq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPBLENDMQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpblendmq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPBLENDMQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpblendmq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPBLENDMQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpblendmq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPBLENDMQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpblendmq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPBLENDMQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPBLENDMQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpblendmqMaskzEmitter<A, B, C> {
    fn vpblendmq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpblendmqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpblendmq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPBLENDMQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpblendmq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPBLENDMQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpblendmq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPBLENDMQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpblendmq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPBLENDMQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpblendmq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPBLENDMQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpblendmqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpblendmq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPBLENDMQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPBROADCASTD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpbroadcastdEmitter<A, B> {
    fn vpbroadcastd(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpbroadcastd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPBROADCASTD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpbroadcastd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPBROADCASTD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpbroadcastd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPBROADCASTD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpbroadcastd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPBROADCASTD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpbroadcastd(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPBROADCASTD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpbroadcastd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPBROADCASTD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTD_GP`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Gpd |
/// | 2 | Ymm, Gpd |
/// | 3 | Zmm, Gpd |
/// +---+----------+
/// ```
pub trait VpbroadcastdGpEmitter<A, B> {
    fn vpbroadcastd_gp(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastdGpEmitter<Xmm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp(&mut self, op0: Xmm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdGpEmitter<Ymm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp(&mut self, op0: Ymm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdGpEmitter<Zmm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp(&mut self, op0: Zmm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTD_GP_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Gpd |
/// | 2 | Ymm, Gpd |
/// | 3 | Zmm, Gpd |
/// +---+----------+
/// ```
pub trait VpbroadcastdGpMaskEmitter<A, B> {
    fn vpbroadcastd_gp_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastdGpMaskEmitter<Xmm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp_mask(&mut self, op0: Xmm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdGpMaskEmitter<Ymm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp_mask(&mut self, op0: Ymm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdGpMaskEmitter<Zmm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp_mask(&mut self, op0: Zmm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTD_GP_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Gpd |
/// | 2 | Ymm, Gpd |
/// | 3 | Zmm, Gpd |
/// +---+----------+
/// ```
pub trait VpbroadcastdGpMaskzEmitter<A, B> {
    fn vpbroadcastd_gp_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastdGpMaskzEmitter<Xmm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp_maskz(&mut self, op0: Xmm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdGpMaskzEmitter<Ymm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp_maskz(&mut self, op0: Ymm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdGpMaskzEmitter<Zmm, Gpd> for Assembler<'a> {
    fn vpbroadcastd_gp_maskz(&mut self, op0: Zmm, op1: Gpd) {
        self.emit(
            VPBROADCASTD_GP512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpbroadcastdMaskEmitter<A, B> {
    fn vpbroadcastd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpbroadcastd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPBROADCASTD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpbroadcastd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPBROADCASTD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpbroadcastd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPBROADCASTD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpbroadcastd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPBROADCASTD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpbroadcastd_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPBROADCASTD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpbroadcastd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPBROADCASTD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpbroadcastdMaskzEmitter<A, B> {
    fn vpbroadcastd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpbroadcastd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPBROADCASTD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpbroadcastd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPBROADCASTD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpbroadcastd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPBROADCASTD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpbroadcastd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPBROADCASTD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpbroadcastd_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPBROADCASTD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpbroadcastd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPBROADCASTD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpbroadcastqEmitter<A, B> {
    fn vpbroadcastq(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpbroadcastq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpbroadcastq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPBROADCASTQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpbroadcastq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpbroadcastq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPBROADCASTQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpbroadcastq(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpbroadcastq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPBROADCASTQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTQ_GP`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Gpd |
/// | 2 | Ymm, Gpd |
/// | 3 | Zmm, Gpd |
/// +---+----------+
/// ```
pub trait VpbroadcastqGpEmitter<A, B> {
    fn vpbroadcastq_gp(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastqGpEmitter<Xmm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp(&mut self, op0: Xmm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqGpEmitter<Ymm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp(&mut self, op0: Ymm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqGpEmitter<Zmm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp(&mut self, op0: Zmm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTQ_GP_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Gpd |
/// | 2 | Ymm, Gpd |
/// | 3 | Zmm, Gpd |
/// +---+----------+
/// ```
pub trait VpbroadcastqGpMaskEmitter<A, B> {
    fn vpbroadcastq_gp_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastqGpMaskEmitter<Xmm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp_mask(&mut self, op0: Xmm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqGpMaskEmitter<Ymm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp_mask(&mut self, op0: Ymm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqGpMaskEmitter<Zmm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp_mask(&mut self, op0: Zmm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTQ_GP_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Gpd |
/// | 2 | Ymm, Gpd |
/// | 3 | Zmm, Gpd |
/// +---+----------+
/// ```
pub trait VpbroadcastqGpMaskzEmitter<A, B> {
    fn vpbroadcastq_gp_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastqGpMaskzEmitter<Xmm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp_maskz(&mut self, op0: Xmm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqGpMaskzEmitter<Ymm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp_maskz(&mut self, op0: Ymm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqGpMaskzEmitter<Zmm, Gpd> for Assembler<'a> {
    fn vpbroadcastq_gp_maskz(&mut self, op0: Zmm, op1: Gpd) {
        self.emit(
            VPBROADCASTQ_GP512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpbroadcastqMaskEmitter<A, B> {
    fn vpbroadcastq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpbroadcastq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpbroadcastq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPBROADCASTQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpbroadcastq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpbroadcastq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPBROADCASTQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpbroadcastq_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpbroadcastq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPBROADCASTQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPBROADCASTQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpbroadcastqMaskzEmitter<A, B> {
    fn vpbroadcastq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpbroadcastqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpbroadcastq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpbroadcastq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPBROADCASTQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpbroadcastq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpbroadcastq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPBROADCASTQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpbroadcastq_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPBROADCASTQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpbroadcastqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpbroadcastq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPBROADCASTQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPCMPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VpcmpdEmitter<A, B, C, D> {
    fn vpcmpd(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpcmpdEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpcmpd(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPCMPD128KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpd(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPD128KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpcmpd(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPCMPD256KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpcmpd(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPD256KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpcmpd(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPCMPD512KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpd(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPD512KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPCMPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VpcmpdMaskEmitter<A, B, C, D> {
    fn vpcmpd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpcmpdMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpcmpd_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPCMPD128KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpd_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPD128KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpcmpd_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPCMPD256KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpcmpd_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPD256KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpcmpd_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPCMPD512KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpdMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpd_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPD512KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPCMPEQB_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VpcmpeqbMaskEmitter<A, B, C> {
    fn vpcmpeqb_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpcmpeqbMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vpcmpeqb_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPCMPEQB128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqbMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vpcmpeqb_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPCMPEQB128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqbMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vpcmpeqb_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPCMPEQB256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqbMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vpcmpeqb_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPCMPEQB256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqbMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vpcmpeqb_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPCMPEQB512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqbMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vpcmpeqb_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPCMPEQB512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPCMPEQD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VpcmpeqdMaskEmitter<A, B, C> {
    fn vpcmpeqd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpcmpeqdMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vpcmpeqd_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPCMPEQD128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqdMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vpcmpeqd_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPCMPEQD128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqdMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vpcmpeqd_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPCMPEQD256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqdMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vpcmpeqd_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPCMPEQD256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqdMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vpcmpeqd_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPCMPEQD512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqdMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vpcmpeqd_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPCMPEQD512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPCMPEQQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VpcmpeqqMaskEmitter<A, B, C> {
    fn vpcmpeqq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpcmpeqqMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vpcmpeqq_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPCMPEQQ128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqqMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vpcmpeqq_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPCMPEQQ128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqqMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vpcmpeqq_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPCMPEQQ256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqqMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vpcmpeqq_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPCMPEQQ256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqqMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vpcmpeqq_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPCMPEQQ512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqqMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vpcmpeqq_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPCMPEQQ512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPCMPEQW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VpcmpeqwMaskEmitter<A, B, C> {
    fn vpcmpeqw_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpcmpeqwMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vpcmpeqw_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPCMPEQW128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqwMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vpcmpeqw_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPCMPEQW128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqwMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vpcmpeqw_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPCMPEQW256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqwMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vpcmpeqw_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPCMPEQW256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqwMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vpcmpeqw_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPCMPEQW512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpeqwMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vpcmpeqw_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPCMPEQW512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPCMPGTB_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VpcmpgtbMaskEmitter<A, B, C> {
    fn vpcmpgtb_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpcmpgtbMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vpcmpgtb_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPCMPGTB128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtbMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vpcmpgtb_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPCMPGTB128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtbMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vpcmpgtb_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPCMPGTB256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtbMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vpcmpgtb_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPCMPGTB256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtbMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vpcmpgtb_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPCMPGTB512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtbMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vpcmpgtb_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPCMPGTB512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPCMPGTD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VpcmpgtdMaskEmitter<A, B, C> {
    fn vpcmpgtd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpcmpgtdMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vpcmpgtd_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPCMPGTD128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtdMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vpcmpgtd_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPCMPGTD128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtdMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vpcmpgtd_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPCMPGTD256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtdMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vpcmpgtd_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPCMPGTD256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtdMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vpcmpgtd_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPCMPGTD512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtdMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vpcmpgtd_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPCMPGTD512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPCMPGTQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VpcmpgtqMaskEmitter<A, B, C> {
    fn vpcmpgtq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpcmpgtqMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vpcmpgtq_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPCMPGTQ128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtqMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vpcmpgtq_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPCMPGTQ128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtqMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vpcmpgtq_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPCMPGTQ256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtqMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vpcmpgtq_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPCMPGTQ256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtqMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vpcmpgtq_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPCMPGTQ512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtqMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vpcmpgtq_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPCMPGTQ512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPCMPGTW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VpcmpgtwMaskEmitter<A, B, C> {
    fn vpcmpgtw_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpcmpgtwMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vpcmpgtw_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPCMPGTW128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtwMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vpcmpgtw_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPCMPGTW128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtwMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vpcmpgtw_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPCMPGTW256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtwMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vpcmpgtw_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPCMPGTW256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtwMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vpcmpgtw_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPCMPGTW512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpcmpgtwMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vpcmpgtw_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPCMPGTW512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPCMPQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VpcmpqEmitter<A, B, C, D> {
    fn vpcmpq(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpcmpqEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpcmpq(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPCMPQ128KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpq(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPQ128KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpcmpq(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPCMPQ256KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpcmpq(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPQ256KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpcmpq(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPCMPQ512KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpq(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPQ512KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPCMPQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VpcmpqMaskEmitter<A, B, C, D> {
    fn vpcmpq_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpcmpqMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpcmpq_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPCMPQ128KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpq_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPQ128KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpcmpq_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPCMPQ256KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpcmpq_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPQ256KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpcmpq_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPCMPQ512KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpqMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpq_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPQ512KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPCMPUD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VpcmpudEmitter<A, B, C, D> {
    fn vpcmpud(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpcmpudEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpcmpud(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPCMPUD128KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpud(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUD128KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpcmpud(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPCMPUD256KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpcmpud(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUD256KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpcmpud(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPCMPUD512KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpud(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUD512KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPCMPUD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VpcmpudMaskEmitter<A, B, C, D> {
    fn vpcmpud_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpcmpudMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpcmpud_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPCMPUD128KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpud_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUD128KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpcmpud_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPCMPUD256KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpcmpud_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUD256KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpcmpud_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPCMPUD512KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpudMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpud_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUD512KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPCMPUQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VpcmpuqEmitter<A, B, C, D> {
    fn vpcmpuq(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpcmpuqEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpcmpuq(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPCMPUQ128KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpuq(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUQ128KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpcmpuq(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPCMPUQ256KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpcmpuq(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUQ256KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpcmpuq(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPCMPUQ512KRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpuq(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUQ512KRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPCMPUQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------------+
/// | # | Operands            |
/// +---+---------------------+
/// | 1 | KReg, Xmm, Mem, Imm |
/// | 2 | KReg, Xmm, Xmm, Imm |
/// | 3 | KReg, Ymm, Mem, Imm |
/// | 4 | KReg, Ymm, Ymm, Imm |
/// | 5 | KReg, Zmm, Mem, Imm |
/// | 6 | KReg, Zmm, Zmm, Imm |
/// +---+---------------------+
/// ```
pub trait VpcmpuqMaskEmitter<A, B, C, D> {
    fn vpcmpuq_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpcmpuqMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpcmpuq_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPCMPUQ128KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpuq_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUQ128KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpcmpuq_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPCMPUQ256KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpcmpuq_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUQ256KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpcmpuq_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPCMPUQ512KRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpcmpuqMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpcmpuq_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPCMPUQ512KRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPCOMPRESSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Ymm, Ymm |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpcompressdEmitter<A, B> {
    fn vpcompressd(&mut self, op0: A, op1: B);
}

impl<'a> VpcompressdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpcompressd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPCOMPRESSD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpcompressd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPCOMPRESSD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpcompressd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPCOMPRESSD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpcompressd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPCOMPRESSD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpcompressd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPCOMPRESSD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpcompressd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPCOMPRESSD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPCOMPRESSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Ymm, Ymm |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpcompressdMaskEmitter<A, B> {
    fn vpcompressd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpcompressdMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpcompressd_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPCOMPRESSD128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpcompressd_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPCOMPRESSD256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpcompressd_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPCOMPRESSD512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpcompressd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPCOMPRESSD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpcompressd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPCOMPRESSD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpcompressd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPCOMPRESSD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPCOMPRESSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Ymm, Ymm |
/// | 3 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpcompressdMaskzEmitter<A, B> {
    fn vpcompressd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpcompressdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpcompressd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPCOMPRESSD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpcompressd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPCOMPRESSD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpcompressd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPCOMPRESSD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPCOMPRESSQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Ymm, Ymm |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpcompressqEmitter<A, B> {
    fn vpcompressq(&mut self, op0: A, op1: B);
}

impl<'a> VpcompressqEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpcompressq(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPCOMPRESSQ128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpcompressq(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPCOMPRESSQ256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpcompressq(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPCOMPRESSQ512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpcompressq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPCOMPRESSQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpcompressq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPCOMPRESSQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpcompressq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPCOMPRESSQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPCOMPRESSQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Ymm, Ymm |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpcompressqMaskEmitter<A, B> {
    fn vpcompressq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpcompressqMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpcompressq_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPCOMPRESSQ128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpcompressq_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPCOMPRESSQ256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpcompressq_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPCOMPRESSQ512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpcompressq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPCOMPRESSQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpcompressq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPCOMPRESSQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpcompressq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPCOMPRESSQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPCOMPRESSQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Ymm, Ymm |
/// | 3 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpcompressqMaskzEmitter<A, B> {
    fn vpcompressq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpcompressqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpcompressq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPCOMPRESSQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpcompressq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPCOMPRESSQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpcompressqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpcompressq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPCOMPRESSQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPERMD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Ymm, Mem |
/// | 2 | Ymm, Ymm, Ymm |
/// | 3 | Zmm, Zmm, Mem |
/// | 4 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermdEmitter<A, B, C> {
    fn vpermd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Ymm, Mem |
/// | 2 | Ymm, Ymm, Ymm |
/// | 3 | Zmm, Zmm, Mem |
/// | 4 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermdMaskEmitter<A, B, C> {
    fn vpermd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Ymm, Mem |
/// | 2 | Ymm, Ymm, Ymm |
/// | 3 | Zmm, Zmm, Mem |
/// | 4 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermdMaskzEmitter<A, B, C> {
    fn vpermd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2D`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2dEmitter<A, B, C> {
    fn vpermi2d(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2dEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2d(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2D128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2d(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2D128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2d(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2D256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2d(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2D256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2d(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2D512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2d(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2D512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2D_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2dMaskEmitter<A, B, C> {
    fn vpermi2d_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2dMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2d_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2D128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2d_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2D128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2d_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2D256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2d_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2D256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2d_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2D512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2d_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2D512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2D_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2dMaskzEmitter<A, B, C> {
    fn vpermi2d_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2dMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2d_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2D128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2d_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2D128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2d_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2D256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2d_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2D256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2d_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2D512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2dMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2d_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2D512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2pdEmitter<A, B, C> {
    fn vpermi2pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2pdMaskEmitter<A, B, C> {
    fn vpermi2pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2pdMaskzEmitter<A, B, C> {
    fn vpermi2pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2psEmitter<A, B, C> {
    fn vpermi2ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2psMaskEmitter<A, B, C> {
    fn vpermi2ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2psMaskzEmitter<A, B, C> {
    fn vpermi2ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2Q`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2qEmitter<A, B, C> {
    fn vpermi2q(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2qEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2q(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2Q128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2q(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2Q128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2q(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2Q256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2q(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2Q256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2q(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2Q512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2q(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2Q512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2Q_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2qMaskEmitter<A, B, C> {
    fn vpermi2q_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2qMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2q_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2Q128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2q_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2Q128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2q_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2Q256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2q_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2Q256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2q_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2Q512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2q_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2Q512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMI2Q_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermi2qMaskzEmitter<A, B, C> {
    fn vpermi2q_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermi2qMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermi2q_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMI2Q128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermi2q_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMI2Q128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermi2q_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMI2Q256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermi2q_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMI2Q256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermi2q_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMI2Q512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermi2qMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermi2q_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMI2Q512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMILPD`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Ymm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Zmm |
/// +----+---------------+
/// ```
pub trait VpermilpdEmitter<A, B, C> {
    fn vpermilpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermilpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMILPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMILPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMILPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMILPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPERMILPD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMILPD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMILPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMILPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMILPD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMILPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Ymm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Zmm |
/// +----+---------------+
/// ```
pub trait VpermilpdMaskEmitter<A, B, C> {
    fn vpermilpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermilpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMILPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMILPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMILPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMILPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMILPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMILPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPERMILPD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMILPD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMILPD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMILPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Ymm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Zmm |
/// +----+---------------+
/// ```
pub trait VpermilpdMaskzEmitter<A, B, C> {
    fn vpermilpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermilpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMILPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMILPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMILPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMILPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMILPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMILPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPERMILPD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMILPD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMILPD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpdMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermilpd_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMILPS`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Ymm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Zmm |
/// +----+---------------+
/// ```
pub trait VpermilpsEmitter<A, B, C> {
    fn vpermilps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermilpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMILPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMILPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMILPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMILPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPERMILPS128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMILPS256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMILPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMILPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMILPS512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermilps(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMILPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Ymm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Zmm |
/// +----+---------------+
/// ```
pub trait VpermilpsMaskEmitter<A, B, C> {
    fn vpermilps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermilpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMILPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMILPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMILPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMILPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMILPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMILPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPERMILPS128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMILPS256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMILPS512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermilps_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMILPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Ymm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Zmm |
/// +----+---------------+
/// ```
pub trait VpermilpsMaskzEmitter<A, B, C> {
    fn vpermilps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermilpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMILPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMILPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMILPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMILPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMILPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMILPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPERMILPS128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMILPS256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMILPS512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermilpsMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermilps_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMILPS512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Imm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// | 7 | Zmm, Zmm, Mem |
/// | 8 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermpdEmitter<A, B, C> {
    fn vpermpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermpdEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermpd(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMPD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermpd(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMPD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermpd(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMPD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermpd(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMPD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Imm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// | 7 | Zmm, Zmm, Mem |
/// | 8 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermpdMaskEmitter<A, B, C> {
    fn vpermpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMPD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermpd_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMPD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMPD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermpd_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMPD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Imm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// | 7 | Zmm, Zmm, Mem |
/// | 8 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermpdMaskzEmitter<A, B, C> {
    fn vpermpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMPD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermpd_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMPD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMPD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpdMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermpd_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMPD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Ymm, Mem |
/// | 2 | Ymm, Ymm, Ymm |
/// | 3 | Zmm, Zmm, Mem |
/// | 4 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermpsEmitter<A, B, C> {
    fn vpermps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Ymm, Mem |
/// | 2 | Ymm, Ymm, Ymm |
/// | 3 | Zmm, Zmm, Mem |
/// | 4 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermpsMaskEmitter<A, B, C> {
    fn vpermps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Ymm, Mem |
/// | 2 | Ymm, Ymm, Ymm |
/// | 3 | Zmm, Zmm, Mem |
/// | 4 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermpsMaskzEmitter<A, B, C> {
    fn vpermps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Imm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// | 7 | Zmm, Zmm, Mem |
/// | 8 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermqEmitter<A, B, C> {
    fn vpermq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermqEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermq(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMQ256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermq(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMQ256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermq(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMQ512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermq(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMQ512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Imm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// | 7 | Zmm, Zmm, Mem |
/// | 8 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermqMaskEmitter<A, B, C> {
    fn vpermq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMQ256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermq_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMQ256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMQ512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermq_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMQ512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Imm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// | 7 | Zmm, Zmm, Mem |
/// | 8 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpermqMaskzEmitter<A, B, C> {
    fn vpermq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpermqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpermq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPERMQ256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpermq_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMQ256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpermq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPERMQ512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpermqMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpermq_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPERMQ512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2D`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2dEmitter<A, B, C> {
    fn vpermt2d(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2dEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2d(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2D128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2d(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2D128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2d(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2D256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2d(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2D256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2d(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2D512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2d(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2D512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2D_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2dMaskEmitter<A, B, C> {
    fn vpermt2d_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2dMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2d_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2D128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2d_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2D128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2d_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2D256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2d_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2D256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2d_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2D512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2d_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2D512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2D_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2dMaskzEmitter<A, B, C> {
    fn vpermt2d_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2dMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2d_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2D128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2d_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2D128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2d_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2D256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2d_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2D256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2d_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2D512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2dMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2d_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2D512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2pdEmitter<A, B, C> {
    fn vpermt2pd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2pdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2pd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2PD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2pd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2PD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2pd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2PD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2pd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2PD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2pd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2PD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2pd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2PD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2pdMaskEmitter<A, B, C> {
    fn vpermt2pd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2pdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2PD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2pd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2PD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2PD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2pd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2PD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2PD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2pd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2PD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2pdMaskzEmitter<A, B, C> {
    fn vpermt2pd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2pdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2PD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2pd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2PD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2PD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2pd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2PD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2PD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2pdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2pd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2PD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2psEmitter<A, B, C> {
    fn vpermt2ps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2PS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2PS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2PS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2PS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2PS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2PS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2psMaskEmitter<A, B, C> {
    fn vpermt2ps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2PS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2PS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2PS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2PS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2PS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2PS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2psMaskzEmitter<A, B, C> {
    fn vpermt2ps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2PS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2PS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2PS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2PS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2PS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2PS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2Q`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2qEmitter<A, B, C> {
    fn vpermt2q(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2qEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2q(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2Q128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2q(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2Q128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2q(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2Q256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2q(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2Q256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2q(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2Q512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2q(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2Q512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2Q_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2qMaskEmitter<A, B, C> {
    fn vpermt2q_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2qMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2q_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2Q128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2q_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2Q128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2q_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2Q256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2q_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2Q256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2q_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2Q512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2q_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2Q512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPERMT2Q_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait Vpermt2qMaskzEmitter<A, B, C> {
    fn vpermt2q_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vpermt2qMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpermt2q_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPERMT2Q128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpermt2q_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPERMT2Q128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpermt2q_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPERMT2Q256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpermt2q_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPERMT2Q256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpermt2q_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPERMT2Q512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vpermt2qMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpermt2q_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPERMT2Q512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPEXPANDD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpexpanddEmitter<A, B> {
    fn vpexpandd(&mut self, op0: A, op1: B);
}

impl<'a> VpexpanddEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpexpandd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPEXPANDD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpexpandd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPEXPANDD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpexpandd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPEXPANDD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpexpandd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPEXPANDD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpexpandd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPEXPANDD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpexpandd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPEXPANDD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPEXPANDD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpexpanddMaskEmitter<A, B> {
    fn vpexpandd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpexpanddMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpexpandd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPEXPANDD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpexpandd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPEXPANDD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpexpandd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPEXPANDD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpexpandd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPEXPANDD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpexpandd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPEXPANDD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpexpandd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPEXPANDD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPEXPANDD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpexpanddMaskzEmitter<A, B> {
    fn vpexpandd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpexpanddMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpexpandd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPEXPANDD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpexpandd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPEXPANDD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpexpandd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPEXPANDD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpexpandd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPEXPANDD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpexpandd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPEXPANDD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpanddMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpexpandd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPEXPANDD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPEXPANDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpexpandqEmitter<A, B> {
    fn vpexpandq(&mut self, op0: A, op1: B);
}

impl<'a> VpexpandqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpexpandq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPEXPANDQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpexpandq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPEXPANDQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpexpandq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPEXPANDQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpexpandq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPEXPANDQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpexpandq(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPEXPANDQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpexpandq(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPEXPANDQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPEXPANDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpexpandqMaskEmitter<A, B> {
    fn vpexpandq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpexpandqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpexpandq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPEXPANDQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpexpandq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPEXPANDQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpexpandq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPEXPANDQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpexpandq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPEXPANDQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpexpandq_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPEXPANDQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpexpandq_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPEXPANDQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPEXPANDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VpexpandqMaskzEmitter<A, B> {
    fn vpexpandq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpexpandqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpexpandq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPEXPANDQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpexpandq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPEXPANDQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpexpandq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPEXPANDQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpexpandq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPEXPANDQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vpexpandq_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VPEXPANDQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpexpandqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vpexpandq_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VPEXPANDQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPGATHERDD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// | 3 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait VpgatherddEmitter_2<A, B> {
    fn vpgatherdd_2(&mut self, op0: A, op1: B);
}

impl<'a> VpgatherddEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vpgatherdd_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPGATHERDD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpgatherddEmitter_2<Ymm, Mem> for Assembler<'a> {
    fn vpgatherdd_2(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPGATHERDD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpgatherddEmitter_2<Zmm, Mem> for Assembler<'a> {
    fn vpgatherdd_2(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPGATHERDD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPGATHERDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// | 3 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait VpgatherdqEmitter_2<A, B> {
    fn vpgatherdq_2(&mut self, op0: A, op1: B);
}

impl<'a> VpgatherdqEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vpgatherdq_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPGATHERDQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpgatherdqEmitter_2<Ymm, Mem> for Assembler<'a> {
    fn vpgatherdq_2(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPGATHERDQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpgatherdqEmitter_2<Zmm, Mem> for Assembler<'a> {
    fn vpgatherdq_2(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPGATHERDQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPGATHERQD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// +---+----------+
/// ```
pub trait VpgatherqdEmitter_2<A, B> {
    fn vpgatherqd_2(&mut self, op0: A, op1: B);
}

impl<'a> VpgatherqdEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vpgatherqd_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPGATHERQD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpgatherqdEmitter_2<Ymm, Mem> for Assembler<'a> {
    fn vpgatherqd_2(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPGATHERQD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPGATHERQQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Ymm, Mem |
/// | 3 | Zmm, Mem |
/// +---+----------+
/// ```
pub trait VpgatherqqEmitter_2<A, B> {
    fn vpgatherqq_2(&mut self, op0: A, op1: B);
}

impl<'a> VpgatherqqEmitter_2<Xmm, Mem> for Assembler<'a> {
    fn vpgatherqq_2(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPGATHERQQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpgatherqqEmitter_2<Ymm, Mem> for Assembler<'a> {
    fn vpgatherqq_2(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPGATHERQQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpgatherqqEmitter_2<Zmm, Mem> for Assembler<'a> {
    fn vpgatherqq_2(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPGATHERQQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMAXSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxsdEmitter<A, B, C> {
    fn vpmaxsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXSD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXSD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxsd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXSD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxsd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXSD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxsd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXSD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxsd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXSD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxsdMaskEmitter<A, B, C> {
    fn vpmaxsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXSD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXSD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxsd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXSD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxsd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXSD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxsd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXSD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxsd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXSD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxsdMaskzEmitter<A, B, C> {
    fn vpmaxsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXSD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXSD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxsd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXSD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxsd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXSD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxsd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXSD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxsd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXSD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXSQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxsqEmitter<A, B, C> {
    fn vpmaxsq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxsqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxsq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXSQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxsq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXSQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxsq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXSQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxsq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXSQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxsq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXSQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxsq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXSQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXSQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxsqMaskEmitter<A, B, C> {
    fn vpmaxsq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxsqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxsq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXSQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxsq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXSQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxsq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXSQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxsq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXSQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxsq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXSQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxsq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXSQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXSQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxsqMaskzEmitter<A, B, C> {
    fn vpmaxsq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxsqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxsq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXSQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxsq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXSQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxsq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXSQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxsq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXSQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxsq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXSQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxsqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxsq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXSQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXUD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxudEmitter<A, B, C> {
    fn vpmaxud(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxudEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxud(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXUD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxud(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXUD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxud(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXUD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxud(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXUD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxud(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXUD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxud(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXUD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXUD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxudMaskEmitter<A, B, C> {
    fn vpmaxud_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxudMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxud_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXUD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxud_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXUD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxud_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXUD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxud_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXUD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxud_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXUD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxud_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXUD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXUD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxudMaskzEmitter<A, B, C> {
    fn vpmaxud_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxudMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxud_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXUD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxud_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXUD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxud_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXUD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxud_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXUD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxud_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXUD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxudMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxud_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXUD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXUQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxuqEmitter<A, B, C> {
    fn vpmaxuq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxuqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxuq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXUQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxuq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXUQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxuq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXUQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxuq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXUQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxuq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXUQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxuq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXUQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXUQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxuqMaskEmitter<A, B, C> {
    fn vpmaxuq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxuqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxuq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXUQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxuq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXUQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxuq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXUQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxuq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXUQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxuq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXUQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxuq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXUQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMAXUQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmaxuqMaskzEmitter<A, B, C> {
    fn vpmaxuq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmaxuqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmaxuq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMAXUQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmaxuq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMAXUQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmaxuq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMAXUQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmaxuq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMAXUQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmaxuq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMAXUQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmaxuqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmaxuq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMAXUQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminsdEmitter<A, B, C> {
    fn vpminsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINSD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINSD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminsd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINSD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminsd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINSD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminsd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINSD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminsd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINSD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminsdMaskEmitter<A, B, C> {
    fn vpminsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINSD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINSD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminsd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINSD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminsd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINSD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminsd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINSD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminsd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINSD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminsdMaskzEmitter<A, B, C> {
    fn vpminsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINSD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINSD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminsd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINSD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminsd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINSD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminsd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINSD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminsd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINSD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINSQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminsqEmitter<A, B, C> {
    fn vpminsq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminsqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminsq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINSQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminsq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINSQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminsq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINSQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminsq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINSQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminsq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINSQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminsq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINSQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINSQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminsqMaskEmitter<A, B, C> {
    fn vpminsq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminsqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminsq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINSQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminsq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINSQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminsq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINSQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminsq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINSQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminsq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINSQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminsq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINSQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINSQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminsqMaskzEmitter<A, B, C> {
    fn vpminsq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminsqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminsq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINSQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminsq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINSQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminsq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINSQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminsq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINSQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminsq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINSQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminsqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminsq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINSQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINUD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminudEmitter<A, B, C> {
    fn vpminud(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminudEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminud(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINUD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminud(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINUD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminud(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINUD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminud(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINUD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminud(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINUD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminud(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINUD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINUD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminudMaskEmitter<A, B, C> {
    fn vpminud_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminudMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminud_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINUD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminud_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINUD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminud_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINUD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminud_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINUD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminud_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINUD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminud_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINUD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINUD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminudMaskzEmitter<A, B, C> {
    fn vpminud_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminudMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminud_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINUD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminud_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINUD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminud_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINUD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminud_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINUD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminud_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINUD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminudMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminud_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINUD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINUQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminuqEmitter<A, B, C> {
    fn vpminuq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminuqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminuq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINUQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminuq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINUQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminuq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINUQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminuq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINUQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminuq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINUQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminuq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINUQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINUQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminuqMaskEmitter<A, B, C> {
    fn vpminuq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminuqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminuq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINUQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminuq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINUQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminuq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINUQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminuq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINUQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminuq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINUQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminuq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINUQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMINUQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpminuqMaskzEmitter<A, B, C> {
    fn vpminuq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpminuqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpminuq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMINUQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpminuq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMINUQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpminuq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMINUQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpminuq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMINUQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpminuq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMINUQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpminuqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpminuq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMINUQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMOVDB`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovdbEmitter<A, B> {
    fn vpmovdb(&mut self, op0: A, op1: B);
}

impl<'a> VpmovdbEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovdb(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVDB128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovdb(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVDB128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovdb(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVDB256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovdb(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVDB256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovdb(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVDB512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovdb(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVDB512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVDB_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovdbMaskEmitter<A, B> {
    fn vpmovdb_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovdbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovdb_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVDB128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovdb_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVDB128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovdb_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVDB256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovdb_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVDB256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovdb_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVDB512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovdb_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVDB512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVDB_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovdbMaskzEmitter<A, B> {
    fn vpmovdb_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovdbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovdb_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVDB128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovdb_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVDB256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdbMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovdb_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVDB512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVDW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovdwEmitter<A, B> {
    fn vpmovdw(&mut self, op0: A, op1: B);
}

impl<'a> VpmovdwEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovdw(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVDW128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovdw(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVDW128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovdw(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVDW256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovdw(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVDW256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovdw(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVDW512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovdw(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVDW512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVDW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovdwMaskEmitter<A, B> {
    fn vpmovdw_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovdwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovdw_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVDW128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovdw_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVDW128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovdw_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVDW256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovdw_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVDW256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovdw_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVDW512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovdw_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVDW512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVDW_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovdwMaskzEmitter<A, B> {
    fn vpmovdw_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovdwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovdw_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVDW128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovdw_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVDW256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovdwMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovdw_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVDW512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQB`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqbEmitter<A, B> {
    fn vpmovqb(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqbEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqb(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQB128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovqb(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVQB128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqb(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQB256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovqb(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVQB256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovqb(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVQB512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovqb(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVQB512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQB_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqbMaskEmitter<A, B> {
    fn vpmovqb_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqb_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQB128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovqb_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVQB128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqb_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQB256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovqb_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVQB256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovqb_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVQB512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovqb_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVQB512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQB_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqbMaskzEmitter<A, B> {
    fn vpmovqb_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqb_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQB128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqb_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQB256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqbMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovqb_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVQB512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqdEmitter<A, B> {
    fn vpmovqd(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovqd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVQD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqd(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovqd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVQD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovqd(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVQD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovqd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVQD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqdMaskEmitter<A, B> {
    fn vpmovqd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovqd_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVQD128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqd_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovqd_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVQD256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovqd_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVQD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovqd_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVQD512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqdMaskzEmitter<A, B> {
    fn vpmovqd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqd_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqdMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovqd_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVQD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqwEmitter<A, B> {
    fn vpmovqw(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqwEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqw(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQW128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovqw(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVQW128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqw(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQW256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovqw(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVQW256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovqw(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVQW512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovqw(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVQW512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqwMaskEmitter<A, B> {
    fn vpmovqw_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqw_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQW128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovqw_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVQW128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqw_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQW256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovqw_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVQW256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovqw_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVQW512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovqw_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVQW512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVQW_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovqwMaskzEmitter<A, B> {
    fn vpmovqw_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovqwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovqw_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVQW128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovqw_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVQW256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovqwMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovqw_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVQW512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSDB`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsdbEmitter<A, B> {
    fn vpmovsdb(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsdbEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsdb(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSDB128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsdb(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSDB128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsdb(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSDB256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsdb(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSDB256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsdb(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSDB512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsdb(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSDB512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSDB_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsdbMaskEmitter<A, B> {
    fn vpmovsdb_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsdbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsdb_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSDB128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsdb_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSDB128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsdb_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSDB256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsdb_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSDB256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsdb_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSDB512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsdb_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSDB512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSDB_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsdbMaskzEmitter<A, B> {
    fn vpmovsdb_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsdbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsdb_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSDB128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsdb_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSDB256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdbMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsdb_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSDB512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSDW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsdwEmitter<A, B> {
    fn vpmovsdw(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsdwEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsdw(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSDW128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsdw(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSDW128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsdw(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSDW256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsdw(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSDW256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovsdw(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVSDW512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsdw(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSDW512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSDW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsdwMaskEmitter<A, B> {
    fn vpmovsdw_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsdwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsdw_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSDW128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsdw_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSDW128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsdw_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSDW256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsdw_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSDW256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovsdw_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVSDW512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsdw_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSDW512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSDW_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsdwMaskzEmitter<A, B> {
    fn vpmovsdw_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsdwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsdw_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSDW128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsdw_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSDW256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsdwMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovsdw_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVSDW512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQB`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqbEmitter<A, B> {
    fn vpmovsqb(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqbEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqb(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQB128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsqb(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSQB128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqb(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQB256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsqb(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSQB256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsqb(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSQB512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsqb(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSQB512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQB_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqbMaskEmitter<A, B> {
    fn vpmovsqb_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqb_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQB128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsqb_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSQB128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqb_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQB256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsqb_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSQB256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsqb_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSQB512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsqb_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSQB512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQB_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqbMaskzEmitter<A, B> {
    fn vpmovsqb_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqb_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQB128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqb_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQB256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqbMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsqb_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSQB512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqdEmitter<A, B> {
    fn vpmovsqd(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsqd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSQD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqd(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsqd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSQD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovsqd(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVSQD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsqd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSQD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqdMaskEmitter<A, B> {
    fn vpmovsqd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsqd_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSQD128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqd_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsqd_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSQD256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovsqd_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVSQD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsqd_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSQD512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqdMaskzEmitter<A, B> {
    fn vpmovsqd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqd_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqdMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovsqd_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVSQD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqwEmitter<A, B> {
    fn vpmovsqw(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqwEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqw(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQW128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsqw(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSQW128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqw(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQW256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsqw(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSQW256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsqw(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSQW512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsqw(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSQW512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqwMaskEmitter<A, B> {
    fn vpmovsqw_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqw_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQW128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovsqw_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVSQW128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqw_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQW256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovsqw_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVSQW256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsqw_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSQW512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovsqw_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVSQW512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSQW_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovsqwMaskzEmitter<A, B> {
    fn vpmovsqw_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsqwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsqw_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSQW128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovsqw_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVSQW256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsqwMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovsqw_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVSQW512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxbdEmitter<A, B> {
    fn vpmovsxbd(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxbd(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXBD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxbdMaskEmitter<A, B> {
    fn vpmovsxbd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxbd_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXBD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxbdMaskzEmitter<A, B> {
    fn vpmovsxbd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxbd_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXBD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxbqEmitter<A, B> {
    fn vpmovsxbq(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxbq(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxbqMaskEmitter<A, B> {
    fn vpmovsxbq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxbq_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxbqMaskzEmitter<A, B> {
    fn vpmovsxbq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxbq_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXBQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxbwEmitter<A, B> {
    fn vpmovsxbw(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbwEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbw(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBW128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbw(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBW128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbw(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBW256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbw(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBW256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxbw(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXBW512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbw(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBW512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxbwMaskEmitter<A, B> {
    fn vpmovsxbw_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbw_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBW128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbw_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBW128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbw_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBW256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbw_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBW256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxbw_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXBW512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbw_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBW512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXBW_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxbwMaskzEmitter<A, B> {
    fn vpmovsxbw_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxbwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxbw_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXBW128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxbw_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXBW128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxbw_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXBW256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxbw_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXBW256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxbw_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXBW512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxbwMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxbw_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXBW512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxdqEmitter<A, B> {
    fn vpmovsxdq(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxdqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxdq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXDQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxdq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXDQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxdq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXDQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxdq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXDQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxdq(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXDQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxdq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXDQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxdqMaskEmitter<A, B> {
    fn vpmovsxdq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxdqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxdq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXDQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxdq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXDQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxdq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXDQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxdq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXDQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxdq_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXDQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxdq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXDQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxdqMaskzEmitter<A, B> {
    fn vpmovsxdq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxdqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxdq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXDQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxdq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXDQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxdq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXDQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxdq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXDQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxdq_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXDQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxdqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxdq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXDQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXWD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxwdEmitter<A, B> {
    fn vpmovsxwd(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxwdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxwd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXWD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxwd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXWD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxwd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXWD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxwd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXWD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxwd(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXWD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxwd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXWD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXWD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxwdMaskEmitter<A, B> {
    fn vpmovsxwd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxwdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxwd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXWD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxwd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXWD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxwd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXWD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxwd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXWD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxwd_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXWD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxwd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXWD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXWD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovsxwdMaskzEmitter<A, B> {
    fn vpmovsxwd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxwdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxwd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXWD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxwd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXWD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxwd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXWD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxwd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXWD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovsxwd_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVSXWD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxwd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXWD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXWQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxwqEmitter<A, B> {
    fn vpmovsxwq(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxwqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxwq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxwq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXWQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxwq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxwq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXWQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxwq(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxwq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXWQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXWQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxwqMaskEmitter<A, B> {
    fn vpmovsxwq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxwqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxwq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxwq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXWQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxwq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxwq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXWQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxwq_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxwq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXWQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVSXWQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovsxwqMaskzEmitter<A, B> {
    fn vpmovsxwq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovsxwqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovsxwq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovsxwq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVSXWQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovsxwq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovsxwq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVSXWQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovsxwq_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVSXWQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovsxwqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovsxwq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVSXWQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSDB`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusdbEmitter<A, B> {
    fn vpmovusdb(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusdbEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusdb(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSDB128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusdb(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSDB128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusdb(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSDB256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusdb(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSDB256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusdb(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSDB512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusdb(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSDB512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSDB_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusdbMaskEmitter<A, B> {
    fn vpmovusdb_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusdbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusdb_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSDB128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusdb_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSDB128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusdb_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSDB256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusdb_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSDB256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusdb_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSDB512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusdb_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSDB512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSDB_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusdbMaskzEmitter<A, B> {
    fn vpmovusdb_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusdbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusdb_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSDB128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusdb_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSDB256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdbMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusdb_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSDB512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSDW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusdwEmitter<A, B> {
    fn vpmovusdw(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusdwEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusdw(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSDW128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusdw(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSDW128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusdw(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSDW256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusdw(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSDW256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovusdw(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVUSDW512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusdw(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSDW512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSDW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusdwMaskEmitter<A, B> {
    fn vpmovusdw_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusdwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusdw_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSDW128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusdw_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSDW128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusdw_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSDW256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusdw_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSDW256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovusdw_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVUSDW512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusdw_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSDW512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSDW_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusdwMaskzEmitter<A, B> {
    fn vpmovusdw_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusdwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusdw_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSDW128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusdw_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSDW256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusdwMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovusdw_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVUSDW512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQB`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqbEmitter<A, B> {
    fn vpmovusqb(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqbEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqb(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQB128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusqb(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSQB128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqb(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQB256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusqb(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSQB256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusqb(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSQB512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusqb(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSQB512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQB_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqbMaskEmitter<A, B> {
    fn vpmovusqb_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqb_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQB128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusqb_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSQB128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqb_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQB256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusqb_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSQB256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusqb_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSQB512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusqb_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSQB512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQB_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqbMaskzEmitter<A, B> {
    fn vpmovusqb_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqb_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQB128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqb_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQB256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqbMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusqb_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSQB512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqdEmitter<A, B> {
    fn vpmovusqd(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusqd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSQD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqd(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusqd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSQD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovusqd(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVUSQD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusqd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSQD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqdMaskEmitter<A, B> {
    fn vpmovusqd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusqd_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSQD128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqd_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusqd_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSQD256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdMaskEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovusqd_mask(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVUSQD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusqd_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSQD512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Ymm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqdMaskzEmitter<A, B> {
    fn vpmovusqd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqd_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqdMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
    fn vpmovusqd_maskz(&mut self, op0: Ymm, op1: Zmm) {
        self.emit(
            VPMOVUSQD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqwEmitter<A, B> {
    fn vpmovusqw(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqwEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqw(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQW128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusqw(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSQW128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqw(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQW256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusqw(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSQW256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusqw(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSQW512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusqw(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSQW512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// | 4 | Xmm, Xmm |
/// | 5 | Xmm, Ymm |
/// | 6 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqwMaskEmitter<A, B> {
    fn vpmovusqw_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqw_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQW128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwMaskEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpmovusqw_mask(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPMOVUSQW128MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwMaskEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqw_mask(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQW256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwMaskEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpmovusqw_mask(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPMOVUSQW256MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwMaskEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusqw_mask(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSQW512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwMaskEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpmovusqw_mask(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPMOVUSQW512MR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVUSQW_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// | 2 | Xmm, Ymm |
/// | 3 | Xmm, Zmm |
/// +---+----------+
/// ```
pub trait VpmovusqwMaskzEmitter<A, B> {
    fn vpmovusqw_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovusqwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovusqw_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVUSQW128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
    fn vpmovusqw_maskz(&mut self, op0: Xmm, op1: Ymm) {
        self.emit(
            VPMOVUSQW256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovusqwMaskzEmitter<Xmm, Zmm> for Assembler<'a> {
    fn vpmovusqw_maskz(&mut self, op0: Xmm, op1: Zmm) {
        self.emit(
            VPMOVUSQW512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxbdEmitter<A, B> {
    fn vpmovzxbd(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxbd(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXBD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxbdMaskEmitter<A, B> {
    fn vpmovzxbd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxbd_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXBD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxbdMaskzEmitter<A, B> {
    fn vpmovzxbd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxbd_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXBD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxbqEmitter<A, B> {
    fn vpmovzxbq(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxbq(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxbqMaskEmitter<A, B> {
    fn vpmovzxbq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxbq_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxbqMaskzEmitter<A, B> {
    fn vpmovzxbq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxbq_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXBQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBW`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxbwEmitter<A, B> {
    fn vpmovzxbw(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbwEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbw(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBW128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbw(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBW128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbw(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBW256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbw(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBW256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxbw(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXBW512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbw(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBW512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBW_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxbwMaskEmitter<A, B> {
    fn vpmovzxbw_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbw_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBW128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbw_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBW128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbw_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBW256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbw_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBW256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxbw_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXBW512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbw_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBW512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXBW_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxbwMaskzEmitter<A, B> {
    fn vpmovzxbw_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxbwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxbw_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXBW128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxbw_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXBW128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxbw_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXBW256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxbw_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXBW256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxbw_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXBW512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxbwMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxbw_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXBW512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxdqEmitter<A, B> {
    fn vpmovzxdq(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxdqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxdq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXDQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxdq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXDQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxdq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXDQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxdq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXDQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxdq(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXDQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxdq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXDQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxdqMaskEmitter<A, B> {
    fn vpmovzxdq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxdqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxdq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXDQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxdq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXDQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxdq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXDQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxdq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXDQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxdq_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXDQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxdq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXDQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxdqMaskzEmitter<A, B> {
    fn vpmovzxdq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxdqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxdq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXDQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxdq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXDQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxdq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXDQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxdq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXDQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxdq_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXDQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxdqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxdq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXDQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXWD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxwdEmitter<A, B> {
    fn vpmovzxwd(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxwdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxwd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXWD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxwd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXWD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxwd(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXWD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxwd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXWD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxwd(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXWD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxwd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXWD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXWD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxwdMaskEmitter<A, B> {
    fn vpmovzxwd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxwdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxwd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXWD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxwd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXWD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxwd_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXWD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxwd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXWD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxwd_mask(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXWD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxwd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXWD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXWD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Ymm |
/// +---+----------+
/// ```
pub trait VpmovzxwdMaskzEmitter<A, B> {
    fn vpmovzxwd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxwdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxwd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXWD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxwd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXWD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxwd_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXWD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxwd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXWD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskzEmitter<Zmm, Ymm> for Assembler<'a> {
    fn vpmovzxwd_maskz(&mut self, op0: Zmm, op1: Ymm) {
        self.emit(
            VPMOVZXWD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxwd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXWD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXWQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxwqEmitter<A, B> {
    fn vpmovzxwq(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxwqEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxwq(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxwq(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXWQ128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxwq(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxwq(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXWQ256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxwq(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxwq(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXWQ512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXWQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxwqMaskEmitter<A, B> {
    fn vpmovzxwq_mask(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxwqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxwq_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxwq_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXWQ128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxwq_mask(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxwq_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXWQ256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxwq_mask(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxwq_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXWQ512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMOVZXWQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Xmm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Xmm |
/// +---+----------+
/// ```
pub trait VpmovzxwqMaskzEmitter<A, B> {
    fn vpmovzxwq_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VpmovzxwqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vpmovzxwq_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vpmovzxwq_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VPMOVZXWQ128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
    fn vpmovzxwq_maskz(&mut self, op0: Ymm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vpmovzxwq_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VPMOVZXWQ256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
    fn vpmovzxwq_maskz(&mut self, op0: Zmm, op1: Xmm) {
        self.emit(
            VPMOVZXWQ512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpmovzxwqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vpmovzxwq_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VPMOVZXWQ512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPMULDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmuldqEmitter<A, B, C> {
    fn vpmuldq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmuldqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmuldq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMULDQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmuldq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMULDQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmuldq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMULDQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmuldq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMULDQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmuldq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMULDQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmuldq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMULDQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMULDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmuldqMaskEmitter<A, B, C> {
    fn vpmuldq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmuldqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmuldq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMULDQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmuldq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMULDQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmuldq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMULDQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmuldq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMULDQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmuldq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMULDQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmuldq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMULDQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMULDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmuldqMaskzEmitter<A, B, C> {
    fn vpmuldq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmuldqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmuldq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMULDQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmuldq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMULDQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmuldq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMULDQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmuldq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMULDQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmuldq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMULDQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuldqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmuldq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMULDQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMULUDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmuludqEmitter<A, B, C> {
    fn vpmuludq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmuludqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmuludq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMULUDQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmuludq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMULUDQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmuludq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMULUDQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmuludq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMULUDQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmuludq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMULUDQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmuludq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMULUDQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMULUDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmuludqMaskEmitter<A, B, C> {
    fn vpmuludq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmuludqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmuludq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMULUDQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmuludq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMULUDQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmuludq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMULUDQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmuludq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMULUDQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmuludq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMULUDQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmuludq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMULUDQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPMULUDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpmuludqMaskzEmitter<A, B, C> {
    fn vpmuludq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpmuludqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpmuludq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPMULUDQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpmuludq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPMULUDQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpmuludq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPMULUDQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpmuludq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPMULUDQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpmuludq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPMULUDQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpmuludqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpmuludq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPMULUDQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPORD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpordEmitter<A, B, C> {
    fn vpord(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpordEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpord(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPORD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpord(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPORD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpord(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPORD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpord(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPORD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpord(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPORD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpord(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPORD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPORD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpordMaskEmitter<A, B, C> {
    fn vpord_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpordMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpord_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPORD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpord_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPORD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpord_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPORD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpord_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPORD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpord_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPORD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpord_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPORD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPORD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpordMaskzEmitter<A, B, C> {
    fn vpord_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpordMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpord_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPORD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpord_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPORD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpord_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPORD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpord_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPORD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpord_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPORD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpordMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpord_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPORD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPORQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VporqEmitter<A, B, C> {
    fn vporq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VporqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vporq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPORQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vporq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPORQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vporq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPORQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vporq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPORQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vporq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPORQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vporq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPORQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPORQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VporqMaskEmitter<A, B, C> {
    fn vporq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VporqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vporq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPORQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vporq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPORQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vporq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPORQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vporq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPORQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vporq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPORQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vporq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPORQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPORQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VporqMaskzEmitter<A, B, C> {
    fn vporq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VporqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vporq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPORQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vporq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPORQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vporq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPORQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vporq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPORQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vporq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPORQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VporqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vporq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPORQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VproldEmitter<A, B, C> {
    fn vprold(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VproldEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprold(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPROLD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprold(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprold(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPROLD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprold(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprold(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPROLD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprold(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VproldMaskEmitter<A, B, C> {
    fn vprold_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VproldMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprold_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPROLD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprold_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprold_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPROLD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprold_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprold_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPROLD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprold_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VproldMaskzEmitter<A, B, C> {
    fn vprold_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VproldMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprold_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPROLD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprold_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprold_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPROLD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprold_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprold_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPROLD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VproldMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprold_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprolqEmitter<A, B, C> {
    fn vprolq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolqEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprolq(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPROLQ128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprolq(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprolq(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPROLQ256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprolq(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprolq(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPROLQ512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprolq(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprolqMaskEmitter<A, B, C> {
    fn vprolq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolqMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprolq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPROLQ128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprolq_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprolq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPROLQ256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprolq_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprolq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPROLQ512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprolq_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprolqMaskzEmitter<A, B, C> {
    fn vprolq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolqMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprolq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPROLQ128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprolq_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprolq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPROLQ256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprolq_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprolq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPROLQ512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolqMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprolq_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPROLQ512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLVD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprolvdEmitter<A, B, C> {
    fn vprolvd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolvdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprolvd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPROLVD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprolvd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPROLVD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprolvd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPROLVD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprolvd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPROLVD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprolvd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPROLVD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprolvd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPROLVD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLVD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprolvdMaskEmitter<A, B, C> {
    fn vprolvd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolvdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprolvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPROLVD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprolvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPROLVD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprolvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPROLVD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprolvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPROLVD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprolvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPROLVD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprolvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPROLVD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLVD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprolvdMaskzEmitter<A, B, C> {
    fn vprolvd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolvdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprolvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPROLVD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprolvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPROLVD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprolvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPROLVD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprolvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPROLVD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprolvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPROLVD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprolvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPROLVD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLVQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprolvqEmitter<A, B, C> {
    fn vprolvq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolvqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprolvq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPROLVQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprolvq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPROLVQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprolvq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPROLVQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprolvq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPROLVQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprolvq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPROLVQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprolvq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPROLVQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLVQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprolvqMaskEmitter<A, B, C> {
    fn vprolvq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolvqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprolvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPROLVQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprolvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPROLVQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprolvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPROLVQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprolvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPROLVQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprolvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPROLVQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprolvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPROLVQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPROLVQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprolvqMaskzEmitter<A, B, C> {
    fn vprolvq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprolvqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprolvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPROLVQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprolvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPROLVQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprolvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPROLVQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprolvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPROLVQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprolvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPROLVQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprolvqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprolvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPROLVQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprordEmitter<A, B, C> {
    fn vprord(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprordEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprord(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPRORD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprord(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprord(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPRORD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprord(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprord(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPRORD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprord(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprordMaskEmitter<A, B, C> {
    fn vprord_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprordMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprord_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPRORD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprord_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprord_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPRORD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprord_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprord_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPRORD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprord_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprordMaskzEmitter<A, B, C> {
    fn vprord_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprordMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprord_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPRORD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprord_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprord_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPRORD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprord_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprord_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPRORD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprordMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprord_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprorqEmitter<A, B, C> {
    fn vprorq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorqEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprorq(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPRORQ128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprorq(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprorq(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPRORQ256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprorq(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprorq(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPRORQ512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprorq(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprorqMaskEmitter<A, B, C> {
    fn vprorq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorqMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprorq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPRORQ128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprorq_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprorq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPRORQ256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprorq_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprorq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPRORQ512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprorq_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VprorqMaskzEmitter<A, B, C> {
    fn vprorq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorqMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vprorq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPRORQ128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vprorq_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vprorq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPRORQ256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vprorq_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vprorq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPRORQ512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorqMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vprorq_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPRORQ512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORVD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprorvdEmitter<A, B, C> {
    fn vprorvd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorvdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprorvd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPRORVD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprorvd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPRORVD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprorvd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPRORVD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprorvd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPRORVD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprorvd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPRORVD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprorvd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPRORVD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORVD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprorvdMaskEmitter<A, B, C> {
    fn vprorvd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorvdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprorvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPRORVD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprorvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPRORVD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprorvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPRORVD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprorvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPRORVD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprorvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPRORVD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprorvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPRORVD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORVD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprorvdMaskzEmitter<A, B, C> {
    fn vprorvd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorvdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprorvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPRORVD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprorvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPRORVD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprorvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPRORVD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprorvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPRORVD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprorvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPRORVD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprorvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPRORVD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORVQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprorvqEmitter<A, B, C> {
    fn vprorvq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorvqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprorvq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPRORVQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprorvq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPRORVQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprorvq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPRORVQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprorvq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPRORVQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprorvq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPRORVQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprorvq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPRORVQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORVQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprorvqMaskEmitter<A, B, C> {
    fn vprorvq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorvqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprorvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPRORVQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprorvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPRORVQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprorvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPRORVQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprorvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPRORVQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprorvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPRORVQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprorvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPRORVQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPRORVQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VprorvqMaskzEmitter<A, B, C> {
    fn vprorvq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VprorvqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vprorvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPRORVQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vprorvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPRORVQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vprorvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPRORVQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vprorvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPRORVQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vprorvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPRORVQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VprorvqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vprorvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPRORVQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSCATTERDD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VpscatterddEmitter<A, B> {
    fn vpscatterdd(&mut self, op0: A, op1: B);
}

impl<'a> VpscatterddEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpscatterdd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPSCATTERDD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpscatterddEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpscatterdd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPSCATTERDD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpscatterddEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpscatterdd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPSCATTERDD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPSCATTERDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VpscatterdqEmitter<A, B> {
    fn vpscatterdq(&mut self, op0: A, op1: B);
}

impl<'a> VpscatterdqEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpscatterdq(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPSCATTERDQ128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpscatterdqEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpscatterdq(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPSCATTERDQ256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpscatterdqEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpscatterdq(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPSCATTERDQ512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPSCATTERQD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// +---+----------+
/// ```
pub trait VpscatterqdEmitter<A, B> {
    fn vpscatterqd(&mut self, op0: A, op1: B);
}

impl<'a> VpscatterqdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpscatterqd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPSCATTERQD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpscatterqdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpscatterqd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPSCATTERQD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPSCATTERQQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VpscatterqqEmitter<A, B> {
    fn vpscatterqq(&mut self, op0: A, op1: B);
}

impl<'a> VpscatterqqEmitter<Mem, Xmm> for Assembler<'a> {
    fn vpscatterqq(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VPSCATTERQQ128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpscatterqqEmitter<Mem, Ymm> for Assembler<'a> {
    fn vpscatterqq(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VPSCATTERQQ256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VpscatterqqEmitter<Mem, Zmm> for Assembler<'a> {
    fn vpscatterqq(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VPSCATTERQQ512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VPSHUFD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VpshufdEmitter<A, B, C> {
    fn vpshufd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpshufdEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpshufd(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSHUFD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpshufd(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpshufd(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSHUFD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpshufd(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpshufd(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSHUFD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpshufd(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSHUFD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VpshufdMaskEmitter<A, B, C> {
    fn vpshufd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpshufdMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpshufd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSHUFD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpshufd_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpshufd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSHUFD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpshufd_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpshufd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSHUFD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpshufd_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSHUFD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VpshufdMaskzEmitter<A, B, C> {
    fn vpshufd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpshufdMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpshufd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSHUFD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpshufd_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpshufd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSHUFD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpshufd_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpshufd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSHUFD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpshufdMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpshufd_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSHUFD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLD`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpslldEmitter<A, B, C> {
    fn vpslld(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpslldEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSLLD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSLLD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpslld(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSLLD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpslld(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSLLD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpslld(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSLLD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpslld(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpslldMaskEmitter<A, B, C> {
    fn vpslld_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpslldMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSLLD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSLLD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSLLD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSLLD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSLLD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpslld_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpslldMaskzEmitter<A, B, C> {
    fn vpslld_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpslldMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSLLD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSLLD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSLLD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSLLD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSLLD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpslldMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpslld_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLQ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsllqEmitter<A, B, C> {
    fn vpsllq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllqEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSLLQ128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSLLQ256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSLLQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSLLQ512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSLLQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsllqMaskEmitter<A, B, C> {
    fn vpsllq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllqMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSLLQ128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSLLQ256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSLLQ512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSLLQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSLLQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsllqMaskzEmitter<A, B, C> {
    fn vpsllq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllqMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSLLQ128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSLLQ256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSLLQ512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSLLQ512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSLLQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSLLQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLVD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsllvdEmitter<A, B, C> {
    fn vpsllvd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllvdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllvd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLVD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllvd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLVD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsllvd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSLLVD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllvd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLVD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsllvd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSLLVD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllvd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLVD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLVD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsllvdMaskEmitter<A, B, C> {
    fn vpsllvd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllvdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLVD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLVD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsllvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSLLVD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLVD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsllvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSLLVD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLVD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLVD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsllvdMaskzEmitter<A, B, C> {
    fn vpsllvd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllvdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLVD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLVD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsllvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSLLVD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLVD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsllvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSLLVD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLVD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLVQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsllvqEmitter<A, B, C> {
    fn vpsllvq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllvqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllvq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLVQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllvq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLVQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsllvq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSLLVQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllvq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLVQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsllvq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSLLVQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllvq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLVQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLVQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsllvqMaskEmitter<A, B, C> {
    fn vpsllvq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllvqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLVQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLVQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsllvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSLLVQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLVQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsllvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSLLVQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLVQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSLLVQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsllvqMaskzEmitter<A, B, C> {
    fn vpsllvq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsllvqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsllvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSLLVQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsllvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSLLVQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsllvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSLLVQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsllvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSLLVQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsllvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSLLVQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsllvqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsllvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSLLVQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAD`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsradEmitter<A, B, C> {
    fn vpsrad(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsradEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRAD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRAD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRAD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRAD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRAD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrad(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsradMaskEmitter<A, B, C> {
    fn vpsrad_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsradMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRAD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRAD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRAD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRAD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRAD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrad_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsradMaskzEmitter<A, B, C> {
    fn vpsrad_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsradMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRAD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRAD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRAD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRAD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRAD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsradMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrad_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAQ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsraqEmitter<A, B, C> {
    fn vpsraq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsraqEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRAQ128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRAQ256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRAQ512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRAQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRAQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsraq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsraqMaskEmitter<A, B, C> {
    fn vpsraq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsraqMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRAQ128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRAQ256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRAQ512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRAQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRAQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsraq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsraqMaskzEmitter<A, B, C> {
    fn vpsraq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsraqMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRAQ128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRAQ256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRAQ512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRAQ512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRAQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRAQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsraqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsraq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAVD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsravdEmitter<A, B, C> {
    fn vpsravd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsravdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsravd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAVD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsravd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAVD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsravd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRAVD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsravd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAVD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsravd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRAVD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsravd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAVD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAVD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsravdMaskEmitter<A, B, C> {
    fn vpsravd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsravdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsravd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAVD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsravd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAVD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsravd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRAVD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsravd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAVD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsravd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRAVD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsravd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAVD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAVD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsravdMaskzEmitter<A, B, C> {
    fn vpsravd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsravdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsravd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAVD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsravd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAVD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsravd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRAVD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsravd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAVD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsravd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRAVD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsravd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAVD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAVQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsravqEmitter<A, B, C> {
    fn vpsravq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsravqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsravq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAVQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsravq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAVQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsravq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRAVQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsravq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAVQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsravq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRAVQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsravq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAVQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAVQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsravqMaskEmitter<A, B, C> {
    fn vpsravq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsravqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsravq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAVQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsravq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAVQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsravq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRAVQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsravq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAVQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsravq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRAVQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsravq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAVQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRAVQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsravqMaskzEmitter<A, B, C> {
    fn vpsravq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsravqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsravq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRAVQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsravq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRAVQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsravq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRAVQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsravq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRAVQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsravq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRAVQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsravqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsravq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRAVQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLD`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsrldEmitter<A, B, C> {
    fn vpsrld(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrldEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRLD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRLD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRLD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRLD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRLD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrld(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsrldMaskEmitter<A, B, C> {
    fn vpsrld_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrldMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRLD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRLD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRLD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRLD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRLD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrld_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsrldMaskzEmitter<A, B, C> {
    fn vpsrld_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrldMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRLD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRLD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRLD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRLD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRLD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrldMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrld_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLQ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsrlqEmitter<A, B, C> {
    fn vpsrlq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlqEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRLQ128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRLQ256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRLQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRLQ512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRLQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsrlqMaskEmitter<A, B, C> {
    fn vpsrlq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlqMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRLQ128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRLQ256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRLQ512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRLQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRLQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +----+---------------+
/// | #  | Operands      |
/// +----+---------------+
/// | 1  | Xmm, Mem, Imm |
/// | 2  | Xmm, Xmm, Imm |
/// | 3  | Xmm, Xmm, Mem |
/// | 4  | Xmm, Xmm, Xmm |
/// | 5  | Ymm, Mem, Imm |
/// | 6  | Ymm, Ymm, Imm |
/// | 7  | Ymm, Ymm, Mem |
/// | 8  | Ymm, Ymm, Xmm |
/// | 9  | Zmm, Mem, Imm |
/// | 10 | Zmm, Zmm, Imm |
/// | 11 | Zmm, Zmm, Mem |
/// | 12 | Zmm, Zmm, Xmm |
/// +----+---------------+
/// ```
pub trait VpsrlqMaskzEmitter<A, B, C> {
    fn vpsrlq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlqMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VPSRLQ128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VPSRLQ256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VPSRLQ512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VPSRLQ512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
        self.emit(
            VPSRLQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
        self.emit(
            VPSRLQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLVD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsrlvdEmitter<A, B, C> {
    fn vpsrlvd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlvdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlvd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLVD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlvd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLVD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsrlvd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRLVD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlvd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLVD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsrlvd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRLVD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlvd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLVD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLVD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsrlvdMaskEmitter<A, B, C> {
    fn vpsrlvd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlvdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLVD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLVD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsrlvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRLVD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLVD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsrlvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRLVD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLVD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLVD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsrlvdMaskzEmitter<A, B, C> {
    fn vpsrlvd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlvdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLVD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLVD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsrlvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRLVD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLVD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsrlvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRLVD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLVD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLVQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsrlvqEmitter<A, B, C> {
    fn vpsrlvq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlvqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlvq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLVQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlvq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLVQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsrlvq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRLVQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlvq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLVQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsrlvq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRLVQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlvq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLVQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLVQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsrlvqMaskEmitter<A, B, C> {
    fn vpsrlvq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlvqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLVQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLVQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsrlvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRLVQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLVQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsrlvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRLVQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLVQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSRLVQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsrlvqMaskzEmitter<A, B, C> {
    fn vpsrlvq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsrlvqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsrlvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSRLVQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsrlvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSRLVQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsrlvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSRLVQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsrlvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSRLVQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsrlvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSRLVQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsrlvqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsrlvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSRLVQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSUBD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsubdEmitter<A, B, C> {
    fn vpsubd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsubdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsubd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSUBD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsubd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSUBD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsubd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSUBD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsubd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSUBD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsubd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSUBD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsubd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSUBD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSUBD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsubdMaskEmitter<A, B, C> {
    fn vpsubd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsubdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsubd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSUBD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsubd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSUBD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsubd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSUBD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsubd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSUBD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsubd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSUBD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsubd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSUBD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSUBD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsubdMaskzEmitter<A, B, C> {
    fn vpsubd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsubdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsubd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSUBD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsubd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSUBD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsubd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSUBD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsubd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSUBD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsubd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSUBD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsubd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSUBD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSUBQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsubqEmitter<A, B, C> {
    fn vpsubq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsubqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsubq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSUBQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsubq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSUBQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsubq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSUBQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsubq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSUBQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsubq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSUBQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsubq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSUBQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSUBQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsubqMaskEmitter<A, B, C> {
    fn vpsubq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsubqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsubq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSUBQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsubq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSUBQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsubq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSUBQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsubq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSUBQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsubq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSUBQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsubq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSUBQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPSUBQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpsubqMaskzEmitter<A, B, C> {
    fn vpsubq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpsubqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpsubq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPSUBQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpsubq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPSUBQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpsubq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPSUBQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpsubq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPSUBQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpsubq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPSUBQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpsubqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpsubq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPSUBQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPTERNLOGD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VpternlogdEmitter<A, B, C, D> {
    fn vpternlogd(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpternlogdEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpternlogd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPTERNLOGD128RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD128RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpternlogd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPTERNLOGD256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpternlogd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPTERNLOGD512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPTERNLOGD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VpternlogdMaskEmitter<A, B, C, D> {
    fn vpternlogd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpternlogdMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpternlogd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPTERNLOGD128RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD128RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpternlogd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPTERNLOGD256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpternlogd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPTERNLOGD512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPTERNLOGD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VpternlogdMaskzEmitter<A, B, C, D> {
    fn vpternlogd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpternlogdMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpternlogd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPTERNLOGD128RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD128RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpternlogd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPTERNLOGD256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpternlogd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPTERNLOGD512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogdMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGD512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPTERNLOGQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VpternlogqEmitter<A, B, C, D> {
    fn vpternlogq(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpternlogqEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpternlogq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPTERNLOGQ128RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ128RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpternlogq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPTERNLOGQ256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpternlogq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPTERNLOGQ512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPTERNLOGQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VpternlogqMaskEmitter<A, B, C, D> {
    fn vpternlogq_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpternlogqMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpternlogq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPTERNLOGQ128RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ128RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpternlogq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPTERNLOGQ256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpternlogq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPTERNLOGQ512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPTERNLOGQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VpternlogqMaskzEmitter<A, B, C, D> {
    fn vpternlogq_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VpternlogqMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vpternlogq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VPTERNLOGQ128RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ128RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vpternlogq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VPTERNLOGQ256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vpternlogq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VPTERNLOGQ512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VpternlogqMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vpternlogq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VPTERNLOGQ512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VPTESTMD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VptestmdEmitter<A, B, C> {
    fn vptestmd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VptestmdEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vptestmd(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPTESTMD128KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vptestmd(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPTESTMD128KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vptestmd(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPTESTMD256KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vptestmd(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPTESTMD256KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vptestmd(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPTESTMD512KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vptestmd(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPTESTMD512KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPTESTMD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VptestmdMaskEmitter<A, B, C> {
    fn vptestmd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VptestmdMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vptestmd_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPTESTMD128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vptestmd_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPTESTMD128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vptestmd_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPTESTMD256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vptestmd_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPTESTMD256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vptestmd_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPTESTMD512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmdMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vptestmd_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPTESTMD512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPTESTMQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VptestmqEmitter<A, B, C> {
    fn vptestmq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VptestmqEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vptestmq(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPTESTMQ128KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vptestmq(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPTESTMQ128KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vptestmq(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPTESTMQ256KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vptestmq(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPTESTMQ256KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vptestmq(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPTESTMQ512KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vptestmq(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPTESTMQ512KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPTESTMQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VptestmqMaskEmitter<A, B, C> {
    fn vptestmq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VptestmqMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vptestmq_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPTESTMQ128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vptestmq_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPTESTMQ128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vptestmq_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPTESTMQ256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vptestmq_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPTESTMQ256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vptestmq_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPTESTMQ512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestmqMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vptestmq_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPTESTMQ512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPTESTNMD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VptestnmdEmitter<A, B, C> {
    fn vptestnmd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VptestnmdEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vptestnmd(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPTESTNMD128KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vptestnmd(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPTESTNMD128KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vptestnmd(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPTESTNMD256KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vptestnmd(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPTESTNMD256KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vptestnmd(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPTESTNMD512KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vptestnmd(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPTESTNMD512KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPTESTNMD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VptestnmdMaskEmitter<A, B, C> {
    fn vptestnmd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VptestnmdMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vptestnmd_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPTESTNMD128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vptestnmd_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPTESTNMD128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vptestnmd_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPTESTNMD256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vptestnmd_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPTESTNMD256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vptestnmd_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPTESTNMD512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmdMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vptestnmd_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPTESTNMD512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPTESTNMQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VptestnmqEmitter<A, B, C> {
    fn vptestnmq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VptestnmqEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vptestnmq(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPTESTNMQ128KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vptestnmq(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPTESTNMQ128KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vptestnmq(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPTESTNMQ256KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vptestnmq(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPTESTNMQ256KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vptestnmq(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPTESTNMQ512KRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vptestnmq(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPTESTNMQ512KRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPTESTNMQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------------+
/// | # | Operands       |
/// +---+----------------+
/// | 1 | KReg, Xmm, Mem |
/// | 2 | KReg, Xmm, Xmm |
/// | 3 | KReg, Ymm, Mem |
/// | 4 | KReg, Ymm, Ymm |
/// | 5 | KReg, Zmm, Mem |
/// | 6 | KReg, Zmm, Zmm |
/// +---+----------------+
/// ```
pub trait VptestnmqMaskEmitter<A, B, C> {
    fn vptestnmq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VptestnmqMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
    fn vptestnmq_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
        self.emit(
            VPTESTNMQ128KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
    fn vptestnmq_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
        self.emit(
            VPTESTNMQ128KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
    fn vptestnmq_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
        self.emit(
            VPTESTNMQ256KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
    fn vptestnmq_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
        self.emit(
            VPTESTNMQ256KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
    fn vptestnmq_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
        self.emit(
            VPTESTNMQ512KRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VptestnmqMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
    fn vptestnmq_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
        self.emit(
            VPTESTNMQ512KRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKHDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckhdqEmitter<A, B, C> {
    fn vpunpckhdq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckhdqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckhdq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKHDQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckhdq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckhdq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKHDQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckhdq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckhdq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKHDQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckhdq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKHDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckhdqMaskEmitter<A, B, C> {
    fn vpunpckhdq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckhdqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckhdq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKHDQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckhdq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckhdq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKHDQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckhdq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckhdq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKHDQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckhdq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKHDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckhdqMaskzEmitter<A, B, C> {
    fn vpunpckhdq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckhdqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckhdq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKHDQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckhdq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckhdq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKHDQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckhdq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckhdq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKHDQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhdqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckhdq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKHDQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKHQDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckhqdqEmitter<A, B, C> {
    fn vpunpckhqdq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckhqdqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckhqdq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKHQDQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckhqdq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckhqdq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKHQDQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckhqdq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckhqdq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKHQDQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckhqdq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKHQDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckhqdqMaskEmitter<A, B, C> {
    fn vpunpckhqdq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckhqdqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckhqdq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKHQDQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckhqdq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckhqdq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKHQDQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckhqdq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckhqdq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKHQDQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckhqdq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKHQDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckhqdqMaskzEmitter<A, B, C> {
    fn vpunpckhqdq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckhqdqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckhqdq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKHQDQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckhqdq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckhqdq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKHQDQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckhqdq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckhqdq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKHQDQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckhqdqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckhqdq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKHQDQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKLDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckldqEmitter<A, B, C> {
    fn vpunpckldq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckldqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckldq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKLDQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckldq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckldq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKLDQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckldq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckldq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKLDQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckldq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKLDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckldqMaskEmitter<A, B, C> {
    fn vpunpckldq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckldqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckldq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKLDQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckldq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckldq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKLDQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckldq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckldq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKLDQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckldq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKLDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpckldqMaskzEmitter<A, B, C> {
    fn vpunpckldq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpckldqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpckldq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKLDQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpckldq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpckldq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKLDQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpckldq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpckldq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKLDQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpckldqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpckldq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKLDQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKLQDQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpcklqdqEmitter<A, B, C> {
    fn vpunpcklqdq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpcklqdqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpcklqdq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKLQDQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpcklqdq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpcklqdq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKLQDQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpcklqdq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpcklqdq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKLQDQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpcklqdq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKLQDQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpcklqdqMaskEmitter<A, B, C> {
    fn vpunpcklqdq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpcklqdqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpcklqdq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKLQDQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpcklqdq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpcklqdq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKLQDQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpcklqdq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpcklqdq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKLQDQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpcklqdq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPUNPCKLQDQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpunpcklqdqMaskzEmitter<A, B, C> {
    fn vpunpcklqdq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpunpcklqdqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpunpcklqdq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPUNPCKLQDQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpunpcklqdq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpunpcklqdq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPUNPCKLQDQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpunpcklqdq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpunpcklqdq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPUNPCKLQDQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpunpcklqdqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpunpcklqdq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPUNPCKLQDQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPXORD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpxordEmitter<A, B, C> {
    fn vpxord(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpxordEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpxord(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPXORD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpxord(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPXORD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpxord(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPXORD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpxord(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPXORD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpxord(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPXORD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpxord(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPXORD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPXORD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpxordMaskEmitter<A, B, C> {
    fn vpxord_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpxordMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpxord_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPXORD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpxord_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPXORD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpxord_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPXORD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpxord_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPXORD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpxord_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPXORD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpxord_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPXORD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPXORD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpxordMaskzEmitter<A, B, C> {
    fn vpxord_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpxordMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpxord_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPXORD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpxord_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPXORD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpxord_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPXORD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpxord_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPXORD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpxord_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPXORD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxordMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpxord_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPXORD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPXORQ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpxorqEmitter<A, B, C> {
    fn vpxorq(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpxorqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpxorq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPXORQ128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpxorq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPXORQ128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpxorq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPXORQ256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpxorq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPXORQ256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpxorq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPXORQ512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpxorq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPXORQ512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPXORQ_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpxorqMaskEmitter<A, B, C> {
    fn vpxorq_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpxorqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpxorq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPXORQ128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpxorq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPXORQ128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpxorq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPXORQ256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpxorq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPXORQ256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpxorq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPXORQ512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpxorq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPXORQ512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VPXORQ_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VpxorqMaskzEmitter<A, B, C> {
    fn vpxorq_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VpxorqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vpxorq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VPXORQ128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vpxorq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VPXORQ128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vpxorq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VPXORQ256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vpxorq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VPXORQ256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vpxorq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VPXORQ512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VpxorqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vpxorq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VPXORQ512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRCP14PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrcp14pdEmitter<A, B> {
    fn vrcp14pd(&mut self, op0: A, op1: B);
}

impl<'a> Vrcp14pdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrcp14pd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRCP14PD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrcp14pd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRCP14PD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrcp14pd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRCP14PD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrcp14pd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRCP14PD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrcp14pd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRCP14PD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrcp14pd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRCP14PD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRCP14PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrcp14pdMaskEmitter<A, B> {
    fn vrcp14pd_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vrcp14pdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrcp14pd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRCP14PD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrcp14pd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRCP14PD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrcp14pd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRCP14PD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrcp14pd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRCP14PD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrcp14pd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRCP14PD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrcp14pd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRCP14PD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRCP14PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrcp14pdMaskzEmitter<A, B> {
    fn vrcp14pd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vrcp14pdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrcp14pd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRCP14PD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrcp14pd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRCP14PD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrcp14pd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRCP14PD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrcp14pd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRCP14PD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrcp14pd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRCP14PD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14pdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrcp14pd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRCP14PD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRCP14PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrcp14psEmitter<A, B> {
    fn vrcp14ps(&mut self, op0: A, op1: B);
}

impl<'a> Vrcp14psEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrcp14ps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRCP14PS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrcp14ps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRCP14PS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrcp14ps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRCP14PS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrcp14ps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRCP14PS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrcp14ps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRCP14PS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrcp14ps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRCP14PS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRCP14PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrcp14psMaskEmitter<A, B> {
    fn vrcp14ps_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vrcp14psMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrcp14ps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRCP14PS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrcp14ps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRCP14PS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrcp14ps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRCP14PS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrcp14ps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRCP14PS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrcp14ps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRCP14PS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrcp14ps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRCP14PS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRCP14PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrcp14psMaskzEmitter<A, B> {
    fn vrcp14ps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vrcp14psMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrcp14ps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRCP14PS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrcp14ps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRCP14PS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrcp14ps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRCP14PS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrcp14ps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRCP14PS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrcp14ps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRCP14PS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrcp14psMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrcp14ps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRCP14PS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRCP14SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrcp14sdEmitter<A, B, C> {
    fn vrcp14sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrcp14sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrcp14sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRCP14SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrcp14sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrcp14sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRCP14SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRCP14SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrcp14sdMaskEmitter<A, B, C> {
    fn vrcp14sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrcp14sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrcp14sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRCP14SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrcp14sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrcp14sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRCP14SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRCP14SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrcp14sdMaskzEmitter<A, B, C> {
    fn vrcp14sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrcp14sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrcp14sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRCP14SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrcp14sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrcp14sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRCP14SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRCP14SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrcp14ssEmitter<A, B, C> {
    fn vrcp14ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrcp14ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrcp14ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRCP14SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrcp14ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrcp14ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRCP14SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRCP14SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrcp14ssMaskEmitter<A, B, C> {
    fn vrcp14ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrcp14ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrcp14ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRCP14SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrcp14ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrcp14ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRCP14SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRCP14SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrcp14ssMaskzEmitter<A, B, C> {
    fn vrcp14ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrcp14ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrcp14ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRCP14SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrcp14ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrcp14ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRCP14SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepdEmitter<A, B, C> {
    fn vrndscalepd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepdEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalepd(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vrndscalepd(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VRNDSCALEPD256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscalepd(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepdMaskEmitter<A, B, C> {
    fn vrndscalepd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepdMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalepd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vrndscalepd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VRNDSCALEPD256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscalepd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepdMaskSaeEmitter<A, B, C> {
    fn vrndscalepd_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepdMaskSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscalepd_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepdMaskzEmitter<A, B, C> {
    fn vrndscalepd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepdMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalepd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vrndscalepd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VRNDSCALEPD256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscalepd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepdMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalepd_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepdMaskzSaeEmitter<A, B, C> {
    fn vrndscalepd_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepdMaskzSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscalepd_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepdSaeEmitter<A, B, C> {
    fn vrndscalepd_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepdSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscalepd_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPD512RRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepsEmitter<A, B, C> {
    fn vrndscaleps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepsEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaleps(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS128RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS128RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vrndscaleps(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VRNDSCALEPS256RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS256RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscaleps(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepsMaskEmitter<A, B, C> {
    fn vrndscaleps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepsMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaleps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS128RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS128RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vrndscaleps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VRNDSCALEPS256RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS256RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscaleps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepsMaskSaeEmitter<A, B, C> {
    fn vrndscaleps_mask_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepsMaskSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscaleps_mask_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Imm |
/// | 3 | Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Imm |
/// | 5 | Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepsMaskzEmitter<A, B, C> {
    fn vrndscaleps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepsMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaleps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS128RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS128RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
    fn vrndscaleps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
        self.emit(
            VRNDSCALEPS256RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS256RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscaleps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VrndscalepsMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaleps_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepsMaskzSaeEmitter<A, B, C> {
    fn vrndscaleps_maskz_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepsMaskzSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscaleps_maskz_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALEPS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Imm |
/// +---+---------------+
/// ```
pub trait VrndscalepsSaeEmitter<A, B, C> {
    fn vrndscaleps_sae(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VrndscalepsSaeEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
    fn vrndscaleps_sae(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
        self.emit(
            VRNDSCALEPS512RRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRNDSCALESD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalesdEmitter<A, B, C, D> {
    fn vrndscalesd(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalesdEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalesd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESDRRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VrndscalesdEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalesd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VRNDSCALESDRRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalesdMaskEmitter<A, B, C, D> {
    fn vrndscalesd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalesdMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalesd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESDRRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VrndscalesdMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalesd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VRNDSCALESDRRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESD_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalesdMaskSaeEmitter<A, B, C, D> {
    fn vrndscalesd_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalesdMaskSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalesd_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESDRRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalesdMaskzEmitter<A, B, C, D> {
    fn vrndscalesd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalesdMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalesd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESDRRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VrndscalesdMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscalesd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VRNDSCALESDRRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESD_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalesdMaskzSaeEmitter<A, B, C, D> {
    fn vrndscalesd_maskz_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalesdMaskzSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalesd_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESDRRRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalesdSaeEmitter<A, B, C, D> {
    fn vrndscalesd_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalesdSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscalesd_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESDRRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalessEmitter<A, B, C, D> {
    fn vrndscaless(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalessEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaless(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESSRRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VrndscalessEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaless(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VRNDSCALESSRRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalessMaskEmitter<A, B, C, D> {
    fn vrndscaless_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalessMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaless_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESSRRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VrndscalessMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaless_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VRNDSCALESSRRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESS_MASK_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalessMaskSaeEmitter<A, B, C, D> {
    fn vrndscaless_mask_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalessMaskSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaless_mask_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESSRRRI_MASK_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalessMaskzEmitter<A, B, C, D> {
    fn vrndscaless_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalessMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaless_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESSRRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VrndscalessMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vrndscaless_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VRNDSCALESSRRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESS_MASKZ_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalessMaskzSaeEmitter<A, B, C, D> {
    fn vrndscaless_maskz_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalessMaskzSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaless_maskz_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESSRRRI_MASKZ_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRNDSCALESS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Xmm, Imm |
/// +---+--------------------+
/// ```
pub trait VrndscalessSaeEmitter<A, B, C, D> {
    fn vrndscaless_sae(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VrndscalessSaeEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vrndscaless_sae(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VRNDSCALESSRRRI_SAE,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VRSQRT14PD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrsqrt14pdEmitter<A, B> {
    fn vrsqrt14pd(&mut self, op0: A, op1: B);
}

impl<'a> Vrsqrt14pdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14pd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRSQRT14PD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14pd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRSQRT14PD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrsqrt14pd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRSQRT14PD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrsqrt14pd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRSQRT14PD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrsqrt14pd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRSQRT14PD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrsqrt14pd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRSQRT14PD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRSQRT14PD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrsqrt14pdMaskEmitter<A, B> {
    fn vrsqrt14pd_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vrsqrt14pdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14pd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRSQRT14PD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14pd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRSQRT14PD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrsqrt14pd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRSQRT14PD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrsqrt14pd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRSQRT14PD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrsqrt14pd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRSQRT14PD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrsqrt14pd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRSQRT14PD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRSQRT14PD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrsqrt14pdMaskzEmitter<A, B> {
    fn vrsqrt14pd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vrsqrt14pdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14pd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRSQRT14PD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14pd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRSQRT14PD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrsqrt14pd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRSQRT14PD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrsqrt14pd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRSQRT14PD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrsqrt14pd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRSQRT14PD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14pdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrsqrt14pd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRSQRT14PD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRSQRT14PS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrsqrt14psEmitter<A, B> {
    fn vrsqrt14ps(&mut self, op0: A, op1: B);
}

impl<'a> Vrsqrt14psEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14ps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRSQRT14PS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14ps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRSQRT14PS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrsqrt14ps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRSQRT14PS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrsqrt14ps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRSQRT14PS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrsqrt14ps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRSQRT14PS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrsqrt14ps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRSQRT14PS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRSQRT14PS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrsqrt14psMaskEmitter<A, B> {
    fn vrsqrt14ps_mask(&mut self, op0: A, op1: B);
}

impl<'a> Vrsqrt14psMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14ps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRSQRT14PS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14ps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRSQRT14PS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrsqrt14ps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRSQRT14PS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrsqrt14ps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRSQRT14PS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrsqrt14ps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRSQRT14PS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrsqrt14ps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRSQRT14PS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRSQRT14PS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait Vrsqrt14psMaskzEmitter<A, B> {
    fn vrsqrt14ps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> Vrsqrt14psMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14ps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VRSQRT14PS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14ps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VRSQRT14PS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vrsqrt14ps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VRSQRT14PS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vrsqrt14ps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VRSQRT14PS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vrsqrt14ps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VRSQRT14PS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14psMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vrsqrt14ps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VRSQRT14PS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VRSQRT14SD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrsqrt14sdEmitter<A, B, C> {
    fn vrsqrt14sd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrsqrt14sdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14sd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRSQRT14SDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14sdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14sd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRSQRT14SDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRSQRT14SD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrsqrt14sdMaskEmitter<A, B, C> {
    fn vrsqrt14sd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrsqrt14sdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRSQRT14SDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14sdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14sd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRSQRT14SDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRSQRT14SD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrsqrt14sdMaskzEmitter<A, B, C> {
    fn vrsqrt14sd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrsqrt14sdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRSQRT14SDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14sdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14sd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRSQRT14SDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRSQRT14SS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrsqrt14ssEmitter<A, B, C> {
    fn vrsqrt14ss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrsqrt14ssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14ss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRSQRT14SSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14ssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14ss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRSQRT14SSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRSQRT14SS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrsqrt14ssMaskEmitter<A, B, C> {
    fn vrsqrt14ss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrsqrt14ssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRSQRT14SSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14ssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14ss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRSQRT14SSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VRSQRT14SS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait Vrsqrt14ssMaskzEmitter<A, B, C> {
    fn vrsqrt14ss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> Vrsqrt14ssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vrsqrt14ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VRSQRT14SSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Vrsqrt14ssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vrsqrt14ss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VRSQRT14SSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpdEmitter<A, B, C> {
    fn vscalefpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vscalefpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSCALEFPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vscalefpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSCALEFPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vscalefpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSCALEFPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpdErEmitter<A, B, C> {
    fn vscalefpd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefpd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpdMaskEmitter<A, B, C> {
    fn vscalefpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vscalefpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSCALEFPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vscalefpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSCALEFPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vscalefpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSCALEFPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpdMaskErEmitter<A, B, C> {
    fn vscalefpd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefpd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpdMaskzEmitter<A, B, C> {
    fn vscalefpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vscalefpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSCALEFPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vscalefpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSCALEFPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vscalefpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSCALEFPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpdMaskzErEmitter<A, B, C> {
    fn vscalefpd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefpd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpsEmitter<A, B, C> {
    fn vscalefps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vscalefps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSCALEFPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vscalefps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSCALEFPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vscalefps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSCALEFPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpsErEmitter<A, B, C> {
    fn vscalefps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpsErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpsMaskEmitter<A, B, C> {
    fn vscalefps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vscalefps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSCALEFPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vscalefps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSCALEFPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vscalefps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSCALEFPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpsMaskErEmitter<A, B, C> {
    fn vscalefps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpsMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpsMaskzEmitter<A, B, C> {
    fn vscalefps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vscalefps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSCALEFPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vscalefps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSCALEFPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vscalefps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSCALEFPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFPS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VscalefpsMaskzErEmitter<A, B, C> {
    fn vscalefps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefpsMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vscalefps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSCALEFPS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefsdEmitter<A, B, C> {
    fn vscalefsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefsdErEmitter<A, B, C> {
    fn vscalefsd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefsdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefsd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefsdMaskEmitter<A, B, C> {
    fn vscalefsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefsdMaskErEmitter<A, B, C> {
    fn vscalefsd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefsdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefsd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefsdMaskzEmitter<A, B, C> {
    fn vscalefsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefsdMaskzErEmitter<A, B, C> {
    fn vscalefsd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefsdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefsd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefssEmitter<A, B, C> {
    fn vscalefss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefssErEmitter<A, B, C> {
    fn vscalefss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefssMaskEmitter<A, B, C> {
    fn vscalefss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefssMaskErEmitter<A, B, C> {
    fn vscalefss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefssMaskzEmitter<A, B, C> {
    fn vscalefss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VscalefssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vscalefss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSCALEFSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCALEFSS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VscalefssMaskzErEmitter<A, B, C> {
    fn vscalefss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VscalefssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vscalefss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSCALEFSSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSCATTERDPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VscatterdpdEmitter<A, B> {
    fn vscatterdpd(&mut self, op0: A, op1: B);
}

impl<'a> VscatterdpdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vscatterdpd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VSCATTERDPD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VscatterdpdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vscatterdpd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VSCATTERDPD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VscatterdpdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vscatterdpd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VSCATTERDPD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSCATTERDPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VscatterdpsEmitter<A, B> {
    fn vscatterdps(&mut self, op0: A, op1: B);
}

impl<'a> VscatterdpsEmitter<Mem, Xmm> for Assembler<'a> {
    fn vscatterdps(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VSCATTERDPS128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VscatterdpsEmitter<Mem, Ymm> for Assembler<'a> {
    fn vscatterdps(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VSCATTERDPS256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VscatterdpsEmitter<Mem, Zmm> for Assembler<'a> {
    fn vscatterdps(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VSCATTERDPS512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSCATTERQPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// | 3 | Mem, Zmm |
/// +---+----------+
/// ```
pub trait VscatterqpdEmitter<A, B> {
    fn vscatterqpd(&mut self, op0: A, op1: B);
}

impl<'a> VscatterqpdEmitter<Mem, Xmm> for Assembler<'a> {
    fn vscatterqpd(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VSCATTERQPD128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VscatterqpdEmitter<Mem, Ymm> for Assembler<'a> {
    fn vscatterqpd(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VSCATTERQPD256MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VscatterqpdEmitter<Mem, Zmm> for Assembler<'a> {
    fn vscatterqpd(&mut self, op0: Mem, op1: Zmm) {
        self.emit(
            VSCATTERQPD512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSCATTERQPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Mem, Xmm |
/// | 2 | Mem, Ymm |
/// +---+----------+
/// ```
pub trait VscatterqpsEmitter<A, B> {
    fn vscatterqps(&mut self, op0: A, op1: B);
}

impl<'a> VscatterqpsEmitter<Mem, Xmm> for Assembler<'a> {
    fn vscatterqps(&mut self, op0: Mem, op1: Xmm) {
        self.emit(
            VSCATTERQPS128MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VscatterqpsEmitter<Mem, Ymm> for Assembler<'a> {
    fn vscatterqps(&mut self, op0: Mem, op1: Ymm) {
        self.emit(
            VSCATTERQPS512MR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSHUFF32X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshuff32x4Emitter<A, B, C, D> {
    fn vshuff32x4(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshuff32x4Emitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshuff32x4(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFF32X4_256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4Emitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshuff32x4(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF32X4_256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4Emitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshuff32x4(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFF32X4_512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4Emitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshuff32x4(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF32X4_512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFF32X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshuff32x4MaskEmitter<A, B, C, D> {
    fn vshuff32x4_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshuff32x4MaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshuff32x4_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFF32X4_256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4MaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshuff32x4_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF32X4_256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4MaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshuff32x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFF32X4_512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4MaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshuff32x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF32X4_512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFF32X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshuff32x4MaskzEmitter<A, B, C, D> {
    fn vshuff32x4_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshuff32x4MaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshuff32x4_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFF32X4_256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4MaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshuff32x4_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF32X4_256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4MaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshuff32x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFF32X4_512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff32x4MaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshuff32x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF32X4_512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFF64X2`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshuff64x2Emitter<A, B, C, D> {
    fn vshuff64x2(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshuff64x2Emitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshuff64x2(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFF64X2_256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2Emitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshuff64x2(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF64X2_256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2Emitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshuff64x2(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFF64X2_512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2Emitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshuff64x2(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF64X2_512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFF64X2_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshuff64x2MaskEmitter<A, B, C, D> {
    fn vshuff64x2_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshuff64x2MaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshuff64x2_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFF64X2_256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2MaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshuff64x2_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF64X2_256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2MaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshuff64x2_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFF64X2_512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2MaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshuff64x2_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF64X2_512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFF64X2_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshuff64x2MaskzEmitter<A, B, C, D> {
    fn vshuff64x2_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshuff64x2MaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshuff64x2_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFF64X2_256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2MaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshuff64x2_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF64X2_256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2MaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshuff64x2_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFF64X2_512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshuff64x2MaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshuff64x2_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFF64X2_512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFI32X4`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshufi32x4Emitter<A, B, C, D> {
    fn vshufi32x4(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshufi32x4Emitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufi32x4(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFI32X4_256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4Emitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufi32x4(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI32X4_256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4Emitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufi32x4(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFI32X4_512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4Emitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufi32x4(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI32X4_512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFI32X4_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshufi32x4MaskEmitter<A, B, C, D> {
    fn vshufi32x4_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshufi32x4MaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufi32x4_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFI32X4_256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4MaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufi32x4_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI32X4_256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4MaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufi32x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFI32X4_512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4MaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufi32x4_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI32X4_512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFI32X4_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshufi32x4MaskzEmitter<A, B, C, D> {
    fn vshufi32x4_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshufi32x4MaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufi32x4_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFI32X4_256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4MaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufi32x4_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI32X4_256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4MaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufi32x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFI32X4_512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi32x4MaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufi32x4_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI32X4_512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFI64X2`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshufi64x2Emitter<A, B, C, D> {
    fn vshufi64x2(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshufi64x2Emitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufi64x2(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFI64X2_256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2Emitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufi64x2(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI64X2_256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2Emitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufi64x2(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFI64X2_512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2Emitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufi64x2(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI64X2_512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFI64X2_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshufi64x2MaskEmitter<A, B, C, D> {
    fn vshufi64x2_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshufi64x2MaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufi64x2_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFI64X2_256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2MaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufi64x2_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI64X2_256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2MaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufi64x2_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFI64X2_512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2MaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufi64x2_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI64X2_512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFI64X2_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Ymm, Ymm, Mem, Imm |
/// | 2 | Ymm, Ymm, Ymm, Imm |
/// | 3 | Zmm, Zmm, Mem, Imm |
/// | 4 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait Vshufi64x2MaskzEmitter<A, B, C, D> {
    fn vshufi64x2_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> Vshufi64x2MaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufi64x2_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFI64X2_256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2MaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufi64x2_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI64X2_256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2MaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufi64x2_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFI64X2_512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> Vshufi64x2MaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufi64x2_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFI64X2_512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VshufpdEmitter<A, B, C, D> {
    fn vshufpd(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VshufpdEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vshufpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VSHUFPD128RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vshufpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD128RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFPD256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFPD512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VshufpdMaskEmitter<A, B, C, D> {
    fn vshufpd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VshufpdMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vshufpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VSHUFPD128RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vshufpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD128RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFPD256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFPD512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VshufpdMaskzEmitter<A, B, C, D> {
    fn vshufpd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VshufpdMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vshufpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VSHUFPD128RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vshufpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD128RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFPD256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFPD512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpdMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPD512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VshufpsEmitter<A, B, C, D> {
    fn vshufps(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VshufpsEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vshufps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VSHUFPS128RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vshufps(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS128RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFPS256RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufps(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS256RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFPS512RRRI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufps(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS512RRMI,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VshufpsMaskEmitter<A, B, C, D> {
    fn vshufps_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VshufpsMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vshufps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VSHUFPS128RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vshufps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS128RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFPS256RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS256RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFPS512RRRI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS512RRMI_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSHUFPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+--------------------+
/// | # | Operands           |
/// +---+--------------------+
/// | 1 | Xmm, Xmm, Mem, Imm |
/// | 2 | Xmm, Xmm, Xmm, Imm |
/// | 3 | Ymm, Ymm, Mem, Imm |
/// | 4 | Ymm, Ymm, Ymm, Imm |
/// | 5 | Zmm, Zmm, Mem, Imm |
/// | 6 | Zmm, Zmm, Zmm, Imm |
/// +---+--------------------+
/// ```
pub trait VshufpsMaskzEmitter<A, B, C, D> {
    fn vshufps_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
}

impl<'a> VshufpsMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
    fn vshufps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
        self.emit(
            VSHUFPS128RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
    fn vshufps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS128RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
    fn vshufps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
        self.emit(
            VSHUFPS256RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
    fn vshufps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS256RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
    fn vshufps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
        self.emit(
            VSHUFPS512RRRI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

impl<'a> VshufpsMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
    fn vshufps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
        self.emit(
            VSHUFPS512RRMI_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            op3.as_operand(),
        );
    }
}

/// `VSQRTPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpdEmitter<A, B> {
    fn vsqrtpd(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vsqrtpd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VSQRTPD128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vsqrtpd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VSQRTPD128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vsqrtpd(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VSQRTPD256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdEmitter<Ymm, Mem> for Assembler<'a> {
    fn vsqrtpd(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VSQRTPD256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtpd(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPD512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdEmitter<Zmm, Mem> for Assembler<'a> {
    fn vsqrtpd(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VSQRTPD512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpdErEmitter<A, B> {
    fn vsqrtpd_er(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpdErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtpd_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPD512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpdMaskEmitter<A, B> {
    fn vsqrtpd_mask(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vsqrtpd_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VSQRTPD128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vsqrtpd_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VSQRTPD128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vsqrtpd_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VSQRTPD256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vsqrtpd_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VSQRTPD256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtpd_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPD512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vsqrtpd_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VSQRTPD512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpdMaskErEmitter<A, B> {
    fn vsqrtpd_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpdMaskErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtpd_mask_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPD512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpdMaskzEmitter<A, B> {
    fn vsqrtpd_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vsqrtpd_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VSQRTPD128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vsqrtpd_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VSQRTPD128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vsqrtpd_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VSQRTPD256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vsqrtpd_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VSQRTPD256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtpd_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPD512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vsqrtpd_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VSQRTPD512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpdMaskzErEmitter<A, B> {
    fn vsqrtpd_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpdMaskzErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtpd_maskz_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPD512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpsEmitter<A, B> {
    fn vsqrtps(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpsEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vsqrtps(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VSQRTPS128RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsEmitter<Xmm, Mem> for Assembler<'a> {
    fn vsqrtps(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VSQRTPS128RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vsqrtps(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VSQRTPS256RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsEmitter<Ymm, Mem> for Assembler<'a> {
    fn vsqrtps(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VSQRTPS256RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtps(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPS512RR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsEmitter<Zmm, Mem> for Assembler<'a> {
    fn vsqrtps(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VSQRTPS512RM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpsErEmitter<A, B> {
    fn vsqrtps_er(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpsErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtps_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPS512RR_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpsMaskEmitter<A, B> {
    fn vsqrtps_mask(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpsMaskEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vsqrtps_mask(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VSQRTPS128RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskEmitter<Xmm, Mem> for Assembler<'a> {
    fn vsqrtps_mask(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VSQRTPS128RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vsqrtps_mask(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VSQRTPS256RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskEmitter<Ymm, Mem> for Assembler<'a> {
    fn vsqrtps_mask(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VSQRTPS256RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtps_mask(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPS512RR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskEmitter<Zmm, Mem> for Assembler<'a> {
    fn vsqrtps_mask(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VSQRTPS512RM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpsMaskErEmitter<A, B> {
    fn vsqrtps_mask_er(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpsMaskErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtps_mask_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPS512RR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// | 3 | Ymm, Mem |
/// | 4 | Ymm, Ymm |
/// | 5 | Zmm, Mem |
/// | 6 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpsMaskzEmitter<A, B> {
    fn vsqrtps_maskz(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpsMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vsqrtps_maskz(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VSQRTPS128RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskzEmitter<Xmm, Mem> for Assembler<'a> {
    fn vsqrtps_maskz(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VSQRTPS128RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
    fn vsqrtps_maskz(&mut self, op0: Ymm, op1: Ymm) {
        self.emit(
            VSQRTPS256RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskzEmitter<Ymm, Mem> for Assembler<'a> {
    fn vsqrtps_maskz(&mut self, op0: Ymm, op1: Mem) {
        self.emit(
            VSQRTPS256RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtps_maskz(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPS512RR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VsqrtpsMaskzEmitter<Zmm, Mem> for Assembler<'a> {
    fn vsqrtps_maskz(&mut self, op0: Zmm, op1: Mem) {
        self.emit(
            VSQRTPS512RM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTPS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Zmm, Zmm |
/// +---+----------+
/// ```
pub trait VsqrtpsMaskzErEmitter<A, B> {
    fn vsqrtps_maskz_er(&mut self, op0: A, op1: B);
}

impl<'a> VsqrtpsMaskzErEmitter<Zmm, Zmm> for Assembler<'a> {
    fn vsqrtps_maskz_er(&mut self, op0: Zmm, op1: Zmm) {
        self.emit(
            VSQRTPS512RR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VSQRTSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtsdEmitter<A, B, C> {
    fn vsqrtsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsqrtsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsqrtsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSQRTSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtsdErEmitter<A, B, C> {
    fn vsqrtsd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtsdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtsd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtsdMaskEmitter<A, B, C> {
    fn vsqrtsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsqrtsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsqrtsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSQRTSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtsdMaskErEmitter<A, B, C> {
    fn vsqrtsd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtsdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtsd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtsdMaskzEmitter<A, B, C> {
    fn vsqrtsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsqrtsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsqrtsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSQRTSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtsdMaskzErEmitter<A, B, C> {
    fn vsqrtsd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtsdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtsd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtssEmitter<A, B, C> {
    fn vsqrtss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsqrtssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsqrtss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSQRTSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtssErEmitter<A, B, C> {
    fn vsqrtss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtssMaskEmitter<A, B, C> {
    fn vsqrtss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsqrtssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsqrtss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSQRTSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtssMaskErEmitter<A, B, C> {
    fn vsqrtss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtssMaskzEmitter<A, B, C> {
    fn vsqrtss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsqrtssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsqrtss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSQRTSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSQRTSS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsqrtssMaskzErEmitter<A, B, C> {
    fn vsqrtss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsqrtssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsqrtss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSQRTSSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpdEmitter<A, B, C> {
    fn vsubpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vsubpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSUBPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vsubpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSUBPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vsubpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSUBPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpdErEmitter<A, B, C> {
    fn vsubpd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpdErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubpd_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPD512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpdMaskEmitter<A, B, C> {
    fn vsubpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vsubpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSUBPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vsubpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSUBPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vsubpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSUBPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpdMaskErEmitter<A, B, C> {
    fn vsubpd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpdMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubpd_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPD512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpdMaskzEmitter<A, B, C> {
    fn vsubpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vsubpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSUBPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vsubpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSUBPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vsubpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSUBPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpdMaskzErEmitter<A, B, C> {
    fn vsubpd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpdMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubpd_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPD512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpsEmitter<A, B, C> {
    fn vsubps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vsubps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSUBPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vsubps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSUBPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vsubps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSUBPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpsErEmitter<A, B, C> {
    fn vsubps_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpsErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubps_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPS512RRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpsMaskEmitter<A, B, C> {
    fn vsubps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vsubps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSUBPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vsubps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSUBPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vsubps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSUBPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpsMaskErEmitter<A, B, C> {
    fn vsubps_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpsMaskErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubps_mask_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPS512RRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpsMaskzEmitter<A, B, C> {
    fn vsubps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vsubps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VSUBPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vsubps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VSUBPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vsubps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VSUBPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBPS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VsubpsMaskzErEmitter<A, B, C> {
    fn vsubps_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubpsMaskzErEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vsubps_maskz_er(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VSUBPS512RRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubsdEmitter<A, B, C> {
    fn vsubsd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubsdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubsd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSDRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubsdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubsd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBSDRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSD_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubsdErEmitter<A, B, C> {
    fn vsubsd_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubsdErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubsd_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSDRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubsdMaskEmitter<A, B, C> {
    fn vsubsd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubsdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSDRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubsdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubsd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBSDRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSD_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubsdMaskErEmitter<A, B, C> {
    fn vsubsd_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubsdMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubsd_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSDRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubsdMaskzEmitter<A, B, C> {
    fn vsubsd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubsdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSDRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubsdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubsd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBSDRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSD_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubsdMaskzErEmitter<A, B, C> {
    fn vsubsd_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubsdMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubsd_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSDRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubssEmitter<A, B, C> {
    fn vsubss(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubssEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubss(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSSRRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubssEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubss(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBSSRRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSS_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubssErEmitter<A, B, C> {
    fn vsubss_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubssErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubss_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSSRRR_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubssMaskEmitter<A, B, C> {
    fn vsubss_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubssMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSSRRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubssMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubss_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBSSRRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSS_MASK_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubssMaskErEmitter<A, B, C> {
    fn vsubss_mask_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubssMaskErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubss_mask_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSSRRR_MASK_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubssMaskzEmitter<A, B, C> {
    fn vsubss_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubssMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSSRRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VsubssMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vsubss_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VSUBSSRRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VSUBSS_MASKZ_ER`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Xmm |
/// +---+---------------+
/// ```
pub trait VsubssMaskzErEmitter<A, B, C> {
    fn vsubss_maskz_er(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VsubssMaskzErEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vsubss_maskz_er(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VSUBSSRRR_MASKZ_ER,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUCOMISD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VucomisdEmitter<A, B> {
    fn vucomisd(&mut self, op0: A, op1: B);
}

impl<'a> VucomisdEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vucomisd(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VUCOMISDRR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VucomisdEmitter<Xmm, Mem> for Assembler<'a> {
    fn vucomisd(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VUCOMISDRM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VUCOMISD_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VucomisdSaeEmitter<A, B> {
    fn vucomisd_sae(&mut self, op0: A, op1: B);
}

impl<'a> VucomisdSaeEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vucomisd_sae(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VUCOMISDRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VUCOMISS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Mem |
/// | 2 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VucomissEmitter<A, B> {
    fn vucomiss(&mut self, op0: A, op1: B);
}

impl<'a> VucomissEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vucomiss(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VUCOMISSRR,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

impl<'a> VucomissEmitter<Xmm, Mem> for Assembler<'a> {
    fn vucomiss(&mut self, op0: Xmm, op1: Mem) {
        self.emit(
            VUCOMISSRM,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VUCOMISS_SAE`.
///
/// Supported operand variants:
///
/// ```text
/// +---+----------+
/// | # | Operands |
/// +---+----------+
/// | 1 | Xmm, Xmm |
/// +---+----------+
/// ```
pub trait VucomissSaeEmitter<A, B> {
    fn vucomiss_sae(&mut self, op0: A, op1: B);
}

impl<'a> VucomissSaeEmitter<Xmm, Xmm> for Assembler<'a> {
    fn vucomiss_sae(&mut self, op0: Xmm, op1: Xmm) {
        self.emit(
            VUCOMISSRR_SAE,
            op0.as_operand(),
            op1.as_operand(),
            &NOREG,
            &NOREG,
        );
    }
}

/// `VUNPCKHPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpckhpdEmitter<A, B, C> {
    fn vunpckhpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpckhpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpckhpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKHPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpckhpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKHPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpckhpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKHPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpckhpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKHPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpckhpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKHPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpckhpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKHPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKHPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpckhpdMaskEmitter<A, B, C> {
    fn vunpckhpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpckhpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpckhpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKHPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpckhpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKHPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpckhpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKHPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpckhpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKHPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpckhpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKHPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpckhpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKHPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKHPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpckhpdMaskzEmitter<A, B, C> {
    fn vunpckhpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpckhpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpckhpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKHPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpckhpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKHPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpckhpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKHPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpckhpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKHPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpckhpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKHPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpckhpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKHPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKHPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpckhpsEmitter<A, B, C> {
    fn vunpckhps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpckhpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpckhps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKHPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpckhps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKHPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpckhps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKHPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpckhps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKHPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpckhps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKHPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpckhps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKHPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKHPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpckhpsMaskEmitter<A, B, C> {
    fn vunpckhps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpckhpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpckhps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKHPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpckhps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKHPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpckhps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKHPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpckhps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKHPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpckhps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKHPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpckhps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKHPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKHPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpckhpsMaskzEmitter<A, B, C> {
    fn vunpckhps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpckhpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpckhps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKHPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpckhps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKHPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpckhps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKHPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpckhps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKHPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpckhps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKHPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpckhpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpckhps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKHPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKLPD`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpcklpdEmitter<A, B, C> {
    fn vunpcklpd(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpcklpdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpcklpd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKLPD128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpcklpd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKLPD128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpcklpd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKLPD256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpcklpd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKLPD256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpcklpd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKLPD512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpcklpd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKLPD512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKLPD_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpcklpdMaskEmitter<A, B, C> {
    fn vunpcklpd_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpcklpdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpcklpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKLPD128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpcklpd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKLPD128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpcklpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKLPD256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpcklpd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKLPD256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpcklpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKLPD512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpcklpd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKLPD512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKLPD_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpcklpdMaskzEmitter<A, B, C> {
    fn vunpcklpd_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpcklpdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpcklpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKLPD128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpcklpd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKLPD128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpcklpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKLPD256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpcklpd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKLPD256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpcklpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKLPD512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpcklpd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKLPD512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKLPS`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpcklpsEmitter<A, B, C> {
    fn vunpcklps(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpcklpsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpcklps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKLPS128RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpcklps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKLPS128RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpcklps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKLPS256RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpcklps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKLPS256RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpcklps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKLPS512RRR,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpcklps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKLPS512RRM,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKLPS_MASK`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpcklpsMaskEmitter<A, B, C> {
    fn vunpcklps_mask(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpcklpsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpcklps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKLPS128RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpcklps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKLPS128RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpcklps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKLPS256RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpcklps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKLPS256RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpcklps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKLPS512RRR_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpcklps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKLPS512RRM_MASK,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

/// `VUNPCKLPS_MASKZ`.
///
/// Supported operand variants:
///
/// ```text
/// +---+---------------+
/// | # | Operands      |
/// +---+---------------+
/// | 1 | Xmm, Xmm, Mem |
/// | 2 | Xmm, Xmm, Xmm |
/// | 3 | Ymm, Ymm, Mem |
/// | 4 | Ymm, Ymm, Ymm |
/// | 5 | Zmm, Zmm, Mem |
/// | 6 | Zmm, Zmm, Zmm |
/// +---+---------------+
/// ```
pub trait VunpcklpsMaskzEmitter<A, B, C> {
    fn vunpcklps_maskz(&mut self, op0: A, op1: B, op2: C);
}

impl<'a> VunpcklpsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
    fn vunpcklps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
        self.emit(
            VUNPCKLPS128RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
    fn vunpcklps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
        self.emit(
            VUNPCKLPS128RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
    fn vunpcklps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
        self.emit(
            VUNPCKLPS256RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
    fn vunpcklps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
        self.emit(
            VUNPCKLPS256RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
    fn vunpcklps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
        self.emit(
            VUNPCKLPS512RRR_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> VunpcklpsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
    fn vunpcklps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
        self.emit(
            VUNPCKLPS512RRM_MASKZ,
            op0.as_operand(),
            op1.as_operand(),
            op2.as_operand(),
            &NOREG,
        );
    }
}

impl<'a> Assembler<'a> {
    /// `KANDNW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------------+
    /// | # | Operands         |
    /// +---+------------------+
    /// | 1 | KReg, KReg, KReg |
    /// +---+------------------+
    /// ```
    #[inline]
    pub fn kandnw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: KandnwEmitter<A, B, C>,
    {
        <Self as KandnwEmitter<A, B, C>>::kandnw(self, op0, op1, op2);
    }
    /// `KANDW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------------+
    /// | # | Operands         |
    /// +---+------------------+
    /// | 1 | KReg, KReg, KReg |
    /// +---+------------------+
    /// ```
    #[inline]
    pub fn kandw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: KandwEmitter<A, B, C>,
    {
        <Self as KandwEmitter<A, B, C>>::kandw(self, op0, op1, op2);
    }
    /// `KMOVW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------+
    /// | # | Operands   |
    /// +---+------------+
    /// | 1 | Gpd, KReg  |
    /// | 2 | KReg, Gpd  |
    /// | 3 | KReg, KReg |
    /// | 4 | KReg, Mem  |
    /// | 5 | Mem, KReg  |
    /// +---+------------+
    /// ```
    #[inline]
    pub fn kmovw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: KmovwEmitter<A, B>,
    {
        <Self as KmovwEmitter<A, B>>::kmovw(self, op0, op1);
    }
    /// `KNOTW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------+
    /// | # | Operands   |
    /// +---+------------+
    /// | 1 | KReg, KReg |
    /// +---+------------+
    /// ```
    #[inline]
    pub fn knotw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: KnotwEmitter<A, B>,
    {
        <Self as KnotwEmitter<A, B>>::knotw(self, op0, op1);
    }
    /// `KORTESTW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------+
    /// | # | Operands   |
    /// +---+------------+
    /// | 1 | KReg, KReg |
    /// +---+------------+
    /// ```
    #[inline]
    pub fn kortestw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: KortestwEmitter<A, B>,
    {
        <Self as KortestwEmitter<A, B>>::kortestw(self, op0, op1);
    }
    /// `KORW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------------+
    /// | # | Operands         |
    /// +---+------------------+
    /// | 1 | KReg, KReg, KReg |
    /// +---+------------------+
    /// ```
    #[inline]
    pub fn korw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: KorwEmitter<A, B, C>,
    {
        <Self as KorwEmitter<A, B, C>>::korw(self, op0, op1, op2);
    }
    /// `KSHIFTLW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+-----------------+
    /// | # | Operands        |
    /// +---+-----------------+
    /// | 1 | KReg, KReg, Imm |
    /// +---+-----------------+
    /// ```
    #[inline]
    pub fn kshiftlw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: KshiftlwEmitter<A, B, C>,
    {
        <Self as KshiftlwEmitter<A, B, C>>::kshiftlw(self, op0, op1, op2);
    }
    /// `KSHIFTRW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+-----------------+
    /// | # | Operands        |
    /// +---+-----------------+
    /// | 1 | KReg, KReg, Imm |
    /// +---+-----------------+
    /// ```
    #[inline]
    pub fn kshiftrw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: KshiftrwEmitter<A, B, C>,
    {
        <Self as KshiftrwEmitter<A, B, C>>::kshiftrw(self, op0, op1, op2);
    }
    /// `KUNPCKBW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------------+
    /// | # | Operands         |
    /// +---+------------------+
    /// | 1 | KReg, KReg, KReg |
    /// +---+------------------+
    /// ```
    #[inline]
    pub fn kunpckbw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: KunpckbwEmitter<A, B, C>,
    {
        <Self as KunpckbwEmitter<A, B, C>>::kunpckbw(self, op0, op1, op2);
    }
    /// `KXNORW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------------+
    /// | # | Operands         |
    /// +---+------------------+
    /// | 1 | KReg, KReg, KReg |
    /// +---+------------------+
    /// ```
    #[inline]
    pub fn kxnorw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: KxnorwEmitter<A, B, C>,
    {
        <Self as KxnorwEmitter<A, B, C>>::kxnorw(self, op0, op1, op2);
    }
    /// `KXORW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+------------------+
    /// | # | Operands         |
    /// +---+------------------+
    /// | 1 | KReg, KReg, KReg |
    /// +---+------------------+
    /// ```
    #[inline]
    pub fn kxorw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: KxorwEmitter<A, B, C>,
    {
        <Self as KxorwEmitter<A, B, C>>::kxorw(self, op0, op1, op2);
    }
    /// `VADDPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpdEmitter<A, B, C>,
    {
        <Self as VaddpdEmitter<A, B, C>>::vaddpd(self, op0, op1, op2);
    }
    /// `VADDPD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddpd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpdErEmitter<A, B, C>,
    {
        <Self as VaddpdErEmitter<A, B, C>>::vaddpd_er(self, op0, op1, op2);
    }
    /// `VADDPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpdMaskEmitter<A, B, C>,
    {
        <Self as VaddpdMaskEmitter<A, B, C>>::vaddpd_mask(self, op0, op1, op2);
    }
    /// `VADDPD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddpd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpdMaskErEmitter<A, B, C>,
    {
        <Self as VaddpdMaskErEmitter<A, B, C>>::vaddpd_mask_er(self, op0, op1, op2);
    }
    /// `VADDPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpdMaskzEmitter<A, B, C>,
    {
        <Self as VaddpdMaskzEmitter<A, B, C>>::vaddpd_maskz(self, op0, op1, op2);
    }
    /// `VADDPD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddpd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpdMaskzErEmitter<A, B, C>,
    {
        <Self as VaddpdMaskzErEmitter<A, B, C>>::vaddpd_maskz_er(self, op0, op1, op2);
    }
    /// `VADDPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpsEmitter<A, B, C>,
    {
        <Self as VaddpsEmitter<A, B, C>>::vaddps(self, op0, op1, op2);
    }
    /// `VADDPS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpsErEmitter<A, B, C>,
    {
        <Self as VaddpsErEmitter<A, B, C>>::vaddps_er(self, op0, op1, op2);
    }
    /// `VADDPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpsMaskEmitter<A, B, C>,
    {
        <Self as VaddpsMaskEmitter<A, B, C>>::vaddps_mask(self, op0, op1, op2);
    }
    /// `VADDPS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpsMaskErEmitter<A, B, C>,
    {
        <Self as VaddpsMaskErEmitter<A, B, C>>::vaddps_mask_er(self, op0, op1, op2);
    }
    /// `VADDPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpsMaskzEmitter<A, B, C>,
    {
        <Self as VaddpsMaskzEmitter<A, B, C>>::vaddps_maskz(self, op0, op1, op2);
    }
    /// `VADDPS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddpsMaskzErEmitter<A, B, C>,
    {
        <Self as VaddpsMaskzErEmitter<A, B, C>>::vaddps_maskz_er(self, op0, op1, op2);
    }
    /// `VADDSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddsdEmitter<A, B, C>,
    {
        <Self as VaddsdEmitter<A, B, C>>::vaddsd(self, op0, op1, op2);
    }
    /// `VADDSD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddsd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddsdErEmitter<A, B, C>,
    {
        <Self as VaddsdErEmitter<A, B, C>>::vaddsd_er(self, op0, op1, op2);
    }
    /// `VADDSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddsdMaskEmitter<A, B, C>,
    {
        <Self as VaddsdMaskEmitter<A, B, C>>::vaddsd_mask(self, op0, op1, op2);
    }
    /// `VADDSD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddsd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddsdMaskErEmitter<A, B, C>,
    {
        <Self as VaddsdMaskErEmitter<A, B, C>>::vaddsd_mask_er(self, op0, op1, op2);
    }
    /// `VADDSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddsdMaskzEmitter<A, B, C>,
    {
        <Self as VaddsdMaskzEmitter<A, B, C>>::vaddsd_maskz(self, op0, op1, op2);
    }
    /// `VADDSD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddsd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddsdMaskzErEmitter<A, B, C>,
    {
        <Self as VaddsdMaskzErEmitter<A, B, C>>::vaddsd_maskz_er(self, op0, op1, op2);
    }
    /// `VADDSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddssEmitter<A, B, C>,
    {
        <Self as VaddssEmitter<A, B, C>>::vaddss(self, op0, op1, op2);
    }
    /// `VADDSS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddssErEmitter<A, B, C>,
    {
        <Self as VaddssErEmitter<A, B, C>>::vaddss_er(self, op0, op1, op2);
    }
    /// `VADDSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddssMaskEmitter<A, B, C>,
    {
        <Self as VaddssMaskEmitter<A, B, C>>::vaddss_mask(self, op0, op1, op2);
    }
    /// `VADDSS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddssMaskErEmitter<A, B, C>,
    {
        <Self as VaddssMaskErEmitter<A, B, C>>::vaddss_mask_er(self, op0, op1, op2);
    }
    /// `VADDSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddssMaskzEmitter<A, B, C>,
    {
        <Self as VaddssMaskzEmitter<A, B, C>>::vaddss_maskz(self, op0, op1, op2);
    }
    /// `VADDSS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vaddss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VaddssMaskzErEmitter<A, B, C>,
    {
        <Self as VaddssMaskzErEmitter<A, B, C>>::vaddss_maskz_er(self, op0, op1, op2);
    }
    /// `VALIGND`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn valignd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: ValigndEmitter<A, B, C, D>,
    {
        <Self as ValigndEmitter<A, B, C, D>>::valignd(self, op0, op1, op2, op3);
    }
    /// `VALIGND_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn valignd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: ValigndMaskEmitter<A, B, C, D>,
    {
        <Self as ValigndMaskEmitter<A, B, C, D>>::valignd_mask(self, op0, op1, op2, op3);
    }
    /// `VALIGND_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn valignd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: ValigndMaskzEmitter<A, B, C, D>,
    {
        <Self as ValigndMaskzEmitter<A, B, C, D>>::valignd_maskz(self, op0, op1, op2, op3);
    }
    /// `VALIGNQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn valignq<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: ValignqEmitter<A, B, C, D>,
    {
        <Self as ValignqEmitter<A, B, C, D>>::valignq(self, op0, op1, op2, op3);
    }
    /// `VALIGNQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn valignq_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: ValignqMaskEmitter<A, B, C, D>,
    {
        <Self as ValignqMaskEmitter<A, B, C, D>>::valignq_mask(self, op0, op1, op2, op3);
    }
    /// `VALIGNQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn valignq_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: ValignqMaskzEmitter<A, B, C, D>,
    {
        <Self as ValignqMaskzEmitter<A, B, C, D>>::valignq_maskz(self, op0, op1, op2, op3);
    }
    /// `VBLENDMPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vblendmpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VblendmpdEmitter<A, B, C>,
    {
        <Self as VblendmpdEmitter<A, B, C>>::vblendmpd(self, op0, op1, op2);
    }
    /// `VBLENDMPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vblendmpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VblendmpdMaskEmitter<A, B, C>,
    {
        <Self as VblendmpdMaskEmitter<A, B, C>>::vblendmpd_mask(self, op0, op1, op2);
    }
    /// `VBLENDMPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vblendmpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VblendmpdMaskzEmitter<A, B, C>,
    {
        <Self as VblendmpdMaskzEmitter<A, B, C>>::vblendmpd_maskz(self, op0, op1, op2);
    }
    /// `VBLENDMPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vblendmps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VblendmpsEmitter<A, B, C>,
    {
        <Self as VblendmpsEmitter<A, B, C>>::vblendmps(self, op0, op1, op2);
    }
    /// `VBLENDMPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vblendmps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VblendmpsMaskEmitter<A, B, C>,
    {
        <Self as VblendmpsMaskEmitter<A, B, C>>::vblendmps_mask(self, op0, op1, op2);
    }
    /// `VBLENDMPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vblendmps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VblendmpsMaskzEmitter<A, B, C>,
    {
        <Self as VblendmpsMaskzEmitter<A, B, C>>::vblendmps_maskz(self, op0, op1, op2);
    }
    /// `VBROADCASTF32X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Mem |
    /// | 2 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastf32x4<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcastf32x4Emitter<A, B>,
    {
        <Self as Vbroadcastf32x4Emitter<A, B>>::vbroadcastf32x4(self, op0, op1);
    }
    /// `VBROADCASTF32X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Mem |
    /// | 2 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastf32x4_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcastf32x4MaskEmitter<A, B>,
    {
        <Self as Vbroadcastf32x4MaskEmitter<A, B>>::vbroadcastf32x4_mask(self, op0, op1);
    }
    /// `VBROADCASTF32X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Mem |
    /// | 2 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastf32x4_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcastf32x4MaskzEmitter<A, B>,
    {
        <Self as Vbroadcastf32x4MaskzEmitter<A, B>>::vbroadcastf32x4_maskz(self, op0, op1);
    }
    /// `VBROADCASTF64X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastf64x4<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcastf64x4Emitter<A, B>,
    {
        <Self as Vbroadcastf64x4Emitter<A, B>>::vbroadcastf64x4(self, op0, op1);
    }
    /// `VBROADCASTF64X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastf64x4_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcastf64x4MaskEmitter<A, B>,
    {
        <Self as Vbroadcastf64x4MaskEmitter<A, B>>::vbroadcastf64x4_mask(self, op0, op1);
    }
    /// `VBROADCASTF64X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastf64x4_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcastf64x4MaskzEmitter<A, B>,
    {
        <Self as Vbroadcastf64x4MaskzEmitter<A, B>>::vbroadcastf64x4_maskz(self, op0, op1);
    }
    /// `VBROADCASTI64X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcasti64x4<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcasti64x4Emitter<A, B>,
    {
        <Self as Vbroadcasti64x4Emitter<A, B>>::vbroadcasti64x4(self, op0, op1);
    }
    /// `VBROADCASTI64X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcasti64x4_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcasti64x4MaskEmitter<A, B>,
    {
        <Self as Vbroadcasti64x4MaskEmitter<A, B>>::vbroadcasti64x4_mask(self, op0, op1);
    }
    /// `VBROADCASTI64X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcasti64x4_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vbroadcasti64x4MaskzEmitter<A, B>,
    {
        <Self as Vbroadcasti64x4MaskzEmitter<A, B>>::vbroadcasti64x4_maskz(self, op0, op1);
    }
    /// `VBROADCASTSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Mem |
    /// | 2 | Ymm, Xmm |
    /// | 3 | Zmm, Mem |
    /// | 4 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastsd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VbroadcastsdEmitter<A, B>,
    {
        <Self as VbroadcastsdEmitter<A, B>>::vbroadcastsd(self, op0, op1);
    }
    /// `VBROADCASTSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Mem |
    /// | 2 | Ymm, Xmm |
    /// | 3 | Zmm, Mem |
    /// | 4 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastsd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VbroadcastsdMaskEmitter<A, B>,
    {
        <Self as VbroadcastsdMaskEmitter<A, B>>::vbroadcastsd_mask(self, op0, op1);
    }
    /// `VBROADCASTSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Mem |
    /// | 2 | Ymm, Xmm |
    /// | 3 | Zmm, Mem |
    /// | 4 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastsd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VbroadcastsdMaskzEmitter<A, B>,
    {
        <Self as VbroadcastsdMaskzEmitter<A, B>>::vbroadcastsd_maskz(self, op0, op1);
    }
    /// `VBROADCASTSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastss<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VbroadcastssEmitter<A, B>,
    {
        <Self as VbroadcastssEmitter<A, B>>::vbroadcastss(self, op0, op1);
    }
    /// `VBROADCASTSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastss_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VbroadcastssMaskEmitter<A, B>,
    {
        <Self as VbroadcastssMaskEmitter<A, B>>::vbroadcastss_mask(self, op0, op1);
    }
    /// `VBROADCASTSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vbroadcastss_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VbroadcastssMaskzEmitter<A, B>,
    {
        <Self as VbroadcastssMaskzEmitter<A, B>>::vbroadcastss_maskz(self, op0, op1);
    }
    /// `VCMPPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmppd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmppdMaskEmitter<A, B, C, D>,
    {
        <Self as VcmppdMaskEmitter<A, B, C, D>>::vcmppd_mask(self, op0, op1, op2, op3);
    }
    /// `VCMPPD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmppd_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmppdMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VcmppdMaskSaeEmitter<A, B, C, D>>::vcmppd_mask_sae(self, op0, op1, op2, op3);
    }
    /// `VCMPPD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmppd_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmppdSaeEmitter<A, B, C, D>,
    {
        <Self as VcmppdSaeEmitter<A, B, C, D>>::vcmppd_sae(self, op0, op1, op2, op3);
    }
    /// `VCMPPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpps_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmppsMaskEmitter<A, B, C, D>,
    {
        <Self as VcmppsMaskEmitter<A, B, C, D>>::vcmpps_mask(self, op0, op1, op2, op3);
    }
    /// `VCMPPS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpps_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmppsMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VcmppsMaskSaeEmitter<A, B, C, D>>::vcmpps_mask_sae(self, op0, op1, op2, op3);
    }
    /// `VCMPPS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpps_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmppsSaeEmitter<A, B, C, D>,
    {
        <Self as VcmppsSaeEmitter<A, B, C, D>>::vcmpps_sae(self, op0, op1, op2, op3);
    }
    /// `VCMPSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpsd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmpsdMaskEmitter<A, B, C, D>,
    {
        <Self as VcmpsdMaskEmitter<A, B, C, D>>::vcmpsd_mask(self, op0, op1, op2, op3);
    }
    /// `VCMPSD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Xmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpsd_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmpsdMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VcmpsdMaskSaeEmitter<A, B, C, D>>::vcmpsd_mask_sae(self, op0, op1, op2, op3);
    }
    /// `VCMPSD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Xmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpsd_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmpsdSaeEmitter<A, B, C, D>,
    {
        <Self as VcmpsdSaeEmitter<A, B, C, D>>::vcmpsd_sae(self, op0, op1, op2, op3);
    }
    /// `VCMPSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpss_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmpssMaskEmitter<A, B, C, D>,
    {
        <Self as VcmpssMaskEmitter<A, B, C, D>>::vcmpss_mask(self, op0, op1, op2, op3);
    }
    /// `VCMPSS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Xmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpss_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmpssMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VcmpssMaskSaeEmitter<A, B, C, D>>::vcmpss_mask_sae(self, op0, op1, op2, op3);
    }
    /// `VCMPSS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Xmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vcmpss_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VcmpssSaeEmitter<A, B, C, D>,
    {
        <Self as VcmpssSaeEmitter<A, B, C, D>>::vcmpss_sae(self, op0, op1, op2, op3);
    }
    /// `VCOMISD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcomisd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcomisdEmitter<A, B>,
    {
        <Self as VcomisdEmitter<A, B>>::vcomisd(self, op0, op1);
    }
    /// `VCOMISD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcomisd_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcomisdSaeEmitter<A, B>,
    {
        <Self as VcomisdSaeEmitter<A, B>>::vcomisd_sae(self, op0, op1);
    }
    /// `VCOMISS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcomiss<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcomissEmitter<A, B>,
    {
        <Self as VcomissEmitter<A, B>>::vcomiss(self, op0, op1);
    }
    /// `VCOMISS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcomiss_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcomissSaeEmitter<A, B>,
    {
        <Self as VcomissSaeEmitter<A, B>>::vcomiss_sae(self, op0, op1);
    }
    /// `VCOMPRESSPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Ymm, Ymm |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcompresspd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcompresspdEmitter<A, B>,
    {
        <Self as VcompresspdEmitter<A, B>>::vcompresspd(self, op0, op1);
    }
    /// `VCOMPRESSPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Ymm, Ymm |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcompresspd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcompresspdMaskEmitter<A, B>,
    {
        <Self as VcompresspdMaskEmitter<A, B>>::vcompresspd_mask(self, op0, op1);
    }
    /// `VCOMPRESSPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Ymm, Ymm |
    /// | 3 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcompresspd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcompresspdMaskzEmitter<A, B>,
    {
        <Self as VcompresspdMaskzEmitter<A, B>>::vcompresspd_maskz(self, op0, op1);
    }
    /// `VCOMPRESSPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Ymm, Ymm |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcompressps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcompresspsEmitter<A, B>,
    {
        <Self as VcompresspsEmitter<A, B>>::vcompressps(self, op0, op1);
    }
    /// `VCOMPRESSPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Ymm, Ymm |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcompressps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcompresspsMaskEmitter<A, B>,
    {
        <Self as VcompresspsMaskEmitter<A, B>>::vcompressps_mask(self, op0, op1);
    }
    /// `VCOMPRESSPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Ymm, Ymm |
    /// | 3 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcompressps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VcompresspsMaskzEmitter<A, B>,
    {
        <Self as VcompresspsMaskzEmitter<A, B>>::vcompressps_maskz(self, op0, op1);
    }
    /// `VCVTDQ2PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2pd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2pdEmitter<A, B>,
    {
        <Self as Vcvtdq2pdEmitter<A, B>>::vcvtdq2pd(self, op0, op1);
    }
    /// `VCVTDQ2PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2pd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2pdMaskEmitter<A, B>,
    {
        <Self as Vcvtdq2pdMaskEmitter<A, B>>::vcvtdq2pd_mask(self, op0, op1);
    }
    /// `VCVTDQ2PD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2pd_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2pdMaskSaeEmitter<A, B>,
    {
        <Self as Vcvtdq2pdMaskSaeEmitter<A, B>>::vcvtdq2pd_mask_sae(self, op0, op1);
    }
    /// `VCVTDQ2PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2pd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2pdMaskzEmitter<A, B>,
    {
        <Self as Vcvtdq2pdMaskzEmitter<A, B>>::vcvtdq2pd_maskz(self, op0, op1);
    }
    /// `VCVTDQ2PD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2pd_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2pdMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvtdq2pdMaskzSaeEmitter<A, B>>::vcvtdq2pd_maskz_sae(self, op0, op1);
    }
    /// `VCVTDQ2PD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2pd_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2pdSaeEmitter<A, B>,
    {
        <Self as Vcvtdq2pdSaeEmitter<A, B>>::vcvtdq2pd_sae(self, op0, op1);
    }
    /// `VCVTDQ2PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2ps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2psEmitter<A, B>,
    {
        <Self as Vcvtdq2psEmitter<A, B>>::vcvtdq2ps(self, op0, op1);
    }
    /// `VCVTDQ2PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2ps_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2psErEmitter<A, B>,
    {
        <Self as Vcvtdq2psErEmitter<A, B>>::vcvtdq2ps_er(self, op0, op1);
    }
    /// `VCVTDQ2PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2ps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2psMaskEmitter<A, B>,
    {
        <Self as Vcvtdq2psMaskEmitter<A, B>>::vcvtdq2ps_mask(self, op0, op1);
    }
    /// `VCVTDQ2PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2ps_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2psMaskErEmitter<A, B>,
    {
        <Self as Vcvtdq2psMaskErEmitter<A, B>>::vcvtdq2ps_mask_er(self, op0, op1);
    }
    /// `VCVTDQ2PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2ps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2psMaskzEmitter<A, B>,
    {
        <Self as Vcvtdq2psMaskzEmitter<A, B>>::vcvtdq2ps_maskz(self, op0, op1);
    }
    /// `VCVTDQ2PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtdq2ps_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtdq2psMaskzErEmitter<A, B>,
    {
        <Self as Vcvtdq2psMaskzErEmitter<A, B>>::vcvtdq2ps_maskz_er(self, op0, op1);
    }
    /// `VCVTPD2DQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2dq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2dqEmitter<A, B>,
    {
        <Self as Vcvtpd2dqEmitter<A, B>>::vcvtpd2dq(self, op0, op1);
    }
    /// `VCVTPD2DQ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2dq_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2dqErEmitter<A, B>,
    {
        <Self as Vcvtpd2dqErEmitter<A, B>>::vcvtpd2dq_er(self, op0, op1);
    }
    /// `VCVTPD2DQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2dq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2dqMaskEmitter<A, B>,
    {
        <Self as Vcvtpd2dqMaskEmitter<A, B>>::vcvtpd2dq_mask(self, op0, op1);
    }
    /// `VCVTPD2DQ_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2dq_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2dqMaskErEmitter<A, B>,
    {
        <Self as Vcvtpd2dqMaskErEmitter<A, B>>::vcvtpd2dq_mask_er(self, op0, op1);
    }
    /// `VCVTPD2DQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2dq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2dqMaskzEmitter<A, B>,
    {
        <Self as Vcvtpd2dqMaskzEmitter<A, B>>::vcvtpd2dq_maskz(self, op0, op1);
    }
    /// `VCVTPD2DQ_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2dq_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2dqMaskzErEmitter<A, B>,
    {
        <Self as Vcvtpd2dqMaskzErEmitter<A, B>>::vcvtpd2dq_maskz_er(self, op0, op1);
    }
    /// `VCVTPD2PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2ps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2psEmitter<A, B>,
    {
        <Self as Vcvtpd2psEmitter<A, B>>::vcvtpd2ps(self, op0, op1);
    }
    /// `VCVTPD2PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2ps_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2psErEmitter<A, B>,
    {
        <Self as Vcvtpd2psErEmitter<A, B>>::vcvtpd2ps_er(self, op0, op1);
    }
    /// `VCVTPD2PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2ps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2psMaskEmitter<A, B>,
    {
        <Self as Vcvtpd2psMaskEmitter<A, B>>::vcvtpd2ps_mask(self, op0, op1);
    }
    /// `VCVTPD2PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2ps_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2psMaskErEmitter<A, B>,
    {
        <Self as Vcvtpd2psMaskErEmitter<A, B>>::vcvtpd2ps_mask_er(self, op0, op1);
    }
    /// `VCVTPD2PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2ps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2psMaskzEmitter<A, B>,
    {
        <Self as Vcvtpd2psMaskzEmitter<A, B>>::vcvtpd2ps_maskz(self, op0, op1);
    }
    /// `VCVTPD2PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2ps_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2psMaskzErEmitter<A, B>,
    {
        <Self as Vcvtpd2psMaskzErEmitter<A, B>>::vcvtpd2ps_maskz_er(self, op0, op1);
    }
    /// `VCVTPD2UDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2udq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2udqEmitter<A, B>,
    {
        <Self as Vcvtpd2udqEmitter<A, B>>::vcvtpd2udq(self, op0, op1);
    }
    /// `VCVTPD2UDQ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2udq_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2udqErEmitter<A, B>,
    {
        <Self as Vcvtpd2udqErEmitter<A, B>>::vcvtpd2udq_er(self, op0, op1);
    }
    /// `VCVTPD2UDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2udq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2udqMaskEmitter<A, B>,
    {
        <Self as Vcvtpd2udqMaskEmitter<A, B>>::vcvtpd2udq_mask(self, op0, op1);
    }
    /// `VCVTPD2UDQ_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2udq_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2udqMaskErEmitter<A, B>,
    {
        <Self as Vcvtpd2udqMaskErEmitter<A, B>>::vcvtpd2udq_mask_er(self, op0, op1);
    }
    /// `VCVTPD2UDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2udq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2udqMaskzEmitter<A, B>,
    {
        <Self as Vcvtpd2udqMaskzEmitter<A, B>>::vcvtpd2udq_maskz(self, op0, op1);
    }
    /// `VCVTPD2UDQ_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2udq_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2udqMaskzErEmitter<A, B>,
    {
        <Self as Vcvtpd2udqMaskzErEmitter<A, B>>::vcvtpd2udq_maskz_er(self, op0, op1);
    }
    /// `VCVTPD2UQQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2uqq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2uqqEmitter<A, B>,
    {
        <Self as Vcvtpd2uqqEmitter<A, B>>::vcvtpd2uqq(self, op0, op1);
    }
    /// `VCVTPD2UQQ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2uqq_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2uqqErEmitter<A, B>,
    {
        <Self as Vcvtpd2uqqErEmitter<A, B>>::vcvtpd2uqq_er(self, op0, op1);
    }
    /// `VCVTPD2UQQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2uqq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2uqqMaskEmitter<A, B>,
    {
        <Self as Vcvtpd2uqqMaskEmitter<A, B>>::vcvtpd2uqq_mask(self, op0, op1);
    }
    /// `VCVTPD2UQQ_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2uqq_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2uqqMaskErEmitter<A, B>,
    {
        <Self as Vcvtpd2uqqMaskErEmitter<A, B>>::vcvtpd2uqq_mask_er(self, op0, op1);
    }
    /// `VCVTPD2UQQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2uqq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2uqqMaskzEmitter<A, B>,
    {
        <Self as Vcvtpd2uqqMaskzEmitter<A, B>>::vcvtpd2uqq_maskz(self, op0, op1);
    }
    /// `VCVTPD2UQQ_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtpd2uqq_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtpd2uqqMaskzErEmitter<A, B>,
    {
        <Self as Vcvtpd2uqqMaskzErEmitter<A, B>>::vcvtpd2uqq_maskz_er(self, op0, op1);
    }
    /// `VCVTPH2PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtph2ps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtph2psEmitter<A, B>,
    {
        <Self as Vcvtph2psEmitter<A, B>>::vcvtph2ps(self, op0, op1);
    }
    /// `VCVTPH2PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtph2ps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtph2psMaskEmitter<A, B>,
    {
        <Self as Vcvtph2psMaskEmitter<A, B>>::vcvtph2ps_mask(self, op0, op1);
    }
    /// `VCVTPH2PS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtph2ps_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtph2psMaskSaeEmitter<A, B>,
    {
        <Self as Vcvtph2psMaskSaeEmitter<A, B>>::vcvtph2ps_mask_sae(self, op0, op1);
    }
    /// `VCVTPH2PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtph2ps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtph2psMaskzEmitter<A, B>,
    {
        <Self as Vcvtph2psMaskzEmitter<A, B>>::vcvtph2ps_maskz(self, op0, op1);
    }
    /// `VCVTPH2PS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtph2ps_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtph2psMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvtph2psMaskzSaeEmitter<A, B>>::vcvtph2ps_maskz_sae(self, op0, op1);
    }
    /// `VCVTPH2PS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtph2ps_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtph2psSaeEmitter<A, B>,
    {
        <Self as Vcvtph2psSaeEmitter<A, B>>::vcvtph2ps_sae(self, op0, op1);
    }
    /// `VCVTPS2DQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2dq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2dqEmitter<A, B>,
    {
        <Self as Vcvtps2dqEmitter<A, B>>::vcvtps2dq(self, op0, op1);
    }
    /// `VCVTPS2DQ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2dq_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2dqErEmitter<A, B>,
    {
        <Self as Vcvtps2dqErEmitter<A, B>>::vcvtps2dq_er(self, op0, op1);
    }
    /// `VCVTPS2DQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2dq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2dqMaskEmitter<A, B>,
    {
        <Self as Vcvtps2dqMaskEmitter<A, B>>::vcvtps2dq_mask(self, op0, op1);
    }
    /// `VCVTPS2DQ_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2dq_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2dqMaskErEmitter<A, B>,
    {
        <Self as Vcvtps2dqMaskErEmitter<A, B>>::vcvtps2dq_mask_er(self, op0, op1);
    }
    /// `VCVTPS2DQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2dq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2dqMaskzEmitter<A, B>,
    {
        <Self as Vcvtps2dqMaskzEmitter<A, B>>::vcvtps2dq_maskz(self, op0, op1);
    }
    /// `VCVTPS2DQ_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2dq_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2dqMaskzErEmitter<A, B>,
    {
        <Self as Vcvtps2dqMaskzErEmitter<A, B>>::vcvtps2dq_maskz_er(self, op0, op1);
    }
    /// `VCVTPS2PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2pd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2pdEmitter<A, B>,
    {
        <Self as Vcvtps2pdEmitter<A, B>>::vcvtps2pd(self, op0, op1);
    }
    /// `VCVTPS2PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2pd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2pdMaskEmitter<A, B>,
    {
        <Self as Vcvtps2pdMaskEmitter<A, B>>::vcvtps2pd_mask(self, op0, op1);
    }
    /// `VCVTPS2PD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2pd_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2pdMaskSaeEmitter<A, B>,
    {
        <Self as Vcvtps2pdMaskSaeEmitter<A, B>>::vcvtps2pd_mask_sae(self, op0, op1);
    }
    /// `VCVTPS2PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2pd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2pdMaskzEmitter<A, B>,
    {
        <Self as Vcvtps2pdMaskzEmitter<A, B>>::vcvtps2pd_maskz(self, op0, op1);
    }
    /// `VCVTPS2PD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2pd_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2pdMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvtps2pdMaskzSaeEmitter<A, B>>::vcvtps2pd_maskz_sae(self, op0, op1);
    }
    /// `VCVTPS2PD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2pd_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2pdSaeEmitter<A, B>,
    {
        <Self as Vcvtps2pdSaeEmitter<A, B>>::vcvtps2pd_sae(self, op0, op1);
    }
    /// `VCVTPS2PH`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Xmm, Imm |
    /// | 2 | Mem, Ymm, Imm |
    /// | 3 | Mem, Zmm, Imm |
    /// | 4 | Xmm, Xmm, Imm |
    /// | 5 | Xmm, Ymm, Imm |
    /// | 6 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtps2ph<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtps2phEmitter<A, B, C>,
    {
        <Self as Vcvtps2phEmitter<A, B, C>>::vcvtps2ph(self, op0, op1, op2);
    }
    /// `VCVTPS2PH_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Xmm, Imm |
    /// | 2 | Mem, Ymm, Imm |
    /// | 3 | Mem, Zmm, Imm |
    /// | 4 | Xmm, Xmm, Imm |
    /// | 5 | Xmm, Ymm, Imm |
    /// | 6 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtps2ph_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtps2phMaskEmitter<A, B, C>,
    {
        <Self as Vcvtps2phMaskEmitter<A, B, C>>::vcvtps2ph_mask(self, op0, op1, op2);
    }
    /// `VCVTPS2PH_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtps2ph_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtps2phMaskSaeEmitter<A, B, C>,
    {
        <Self as Vcvtps2phMaskSaeEmitter<A, B, C>>::vcvtps2ph_mask_sae(self, op0, op1, op2);
    }
    /// `VCVTPS2PH_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Imm |
    /// | 2 | Xmm, Ymm, Imm |
    /// | 3 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtps2ph_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtps2phMaskzEmitter<A, B, C>,
    {
        <Self as Vcvtps2phMaskzEmitter<A, B, C>>::vcvtps2ph_maskz(self, op0, op1, op2);
    }
    /// `VCVTPS2PH_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtps2ph_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtps2phMaskzSaeEmitter<A, B, C>,
    {
        <Self as Vcvtps2phMaskzSaeEmitter<A, B, C>>::vcvtps2ph_maskz_sae(self, op0, op1, op2);
    }
    /// `VCVTPS2PH_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtps2ph_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtps2phSaeEmitter<A, B, C>,
    {
        <Self as Vcvtps2phSaeEmitter<A, B, C>>::vcvtps2ph_sae(self, op0, op1, op2);
    }
    /// `VCVTPS2UDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2udq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2udqEmitter<A, B>,
    {
        <Self as Vcvtps2udqEmitter<A, B>>::vcvtps2udq(self, op0, op1);
    }
    /// `VCVTPS2UDQ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2udq_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2udqErEmitter<A, B>,
    {
        <Self as Vcvtps2udqErEmitter<A, B>>::vcvtps2udq_er(self, op0, op1);
    }
    /// `VCVTPS2UDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2udq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2udqMaskEmitter<A, B>,
    {
        <Self as Vcvtps2udqMaskEmitter<A, B>>::vcvtps2udq_mask(self, op0, op1);
    }
    /// `VCVTPS2UDQ_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2udq_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2udqMaskErEmitter<A, B>,
    {
        <Self as Vcvtps2udqMaskErEmitter<A, B>>::vcvtps2udq_mask_er(self, op0, op1);
    }
    /// `VCVTPS2UDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2udq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2udqMaskzEmitter<A, B>,
    {
        <Self as Vcvtps2udqMaskzEmitter<A, B>>::vcvtps2udq_maskz(self, op0, op1);
    }
    /// `VCVTPS2UDQ_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2udq_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2udqMaskzErEmitter<A, B>,
    {
        <Self as Vcvtps2udqMaskzErEmitter<A, B>>::vcvtps2udq_maskz_er(self, op0, op1);
    }
    /// `VCVTPS2UQQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2uqq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2uqqEmitter<A, B>,
    {
        <Self as Vcvtps2uqqEmitter<A, B>>::vcvtps2uqq(self, op0, op1);
    }
    /// `VCVTPS2UQQ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2uqq_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2uqqErEmitter<A, B>,
    {
        <Self as Vcvtps2uqqErEmitter<A, B>>::vcvtps2uqq_er(self, op0, op1);
    }
    /// `VCVTPS2UQQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2uqq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2uqqMaskEmitter<A, B>,
    {
        <Self as Vcvtps2uqqMaskEmitter<A, B>>::vcvtps2uqq_mask(self, op0, op1);
    }
    /// `VCVTPS2UQQ_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2uqq_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2uqqMaskErEmitter<A, B>,
    {
        <Self as Vcvtps2uqqMaskErEmitter<A, B>>::vcvtps2uqq_mask_er(self, op0, op1);
    }
    /// `VCVTPS2UQQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2uqq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2uqqMaskzEmitter<A, B>,
    {
        <Self as Vcvtps2uqqMaskzEmitter<A, B>>::vcvtps2uqq_maskz(self, op0, op1);
    }
    /// `VCVTPS2UQQ_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtps2uqq_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtps2uqqMaskzErEmitter<A, B>,
    {
        <Self as Vcvtps2uqqMaskzErEmitter<A, B>>::vcvtps2uqq_maskz_er(self, op0, op1);
    }
    /// `VCVTSD2SI`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Mem |
    /// | 2 | Gpd, Xmm |
    /// | 3 | Gpq, Mem |
    /// | 4 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtsd2si<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtsd2siEmitter<A, B>,
    {
        <Self as Vcvtsd2siEmitter<A, B>>::vcvtsd2si(self, op0, op1);
    }
    /// `VCVTSD2SI_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Xmm |
    /// | 2 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtsd2si_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtsd2siErEmitter<A, B>,
    {
        <Self as Vcvtsd2siErEmitter<A, B>>::vcvtsd2si_er(self, op0, op1);
    }
    /// `VCVTSD2SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsd2ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsd2ssEmitter<A, B, C>,
    {
        <Self as Vcvtsd2ssEmitter<A, B, C>>::vcvtsd2ss(self, op0, op1, op2);
    }
    /// `VCVTSD2SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsd2ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsd2ssErEmitter<A, B, C>,
    {
        <Self as Vcvtsd2ssErEmitter<A, B, C>>::vcvtsd2ss_er(self, op0, op1, op2);
    }
    /// `VCVTSD2SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsd2ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsd2ssMaskEmitter<A, B, C>,
    {
        <Self as Vcvtsd2ssMaskEmitter<A, B, C>>::vcvtsd2ss_mask(self, op0, op1, op2);
    }
    /// `VCVTSD2SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsd2ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsd2ssMaskErEmitter<A, B, C>,
    {
        <Self as Vcvtsd2ssMaskErEmitter<A, B, C>>::vcvtsd2ss_mask_er(self, op0, op1, op2);
    }
    /// `VCVTSD2SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsd2ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsd2ssMaskzEmitter<A, B, C>,
    {
        <Self as Vcvtsd2ssMaskzEmitter<A, B, C>>::vcvtsd2ss_maskz(self, op0, op1, op2);
    }
    /// `VCVTSD2SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsd2ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsd2ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vcvtsd2ssMaskzErEmitter<A, B, C>>::vcvtsd2ss_maskz_er(self, op0, op1, op2);
    }
    /// `VCVTSD2USI`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Mem |
    /// | 2 | Gpd, Xmm |
    /// | 3 | Gpq, Mem |
    /// | 4 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtsd2usi<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtsd2usiEmitter<A, B>,
    {
        <Self as Vcvtsd2usiEmitter<A, B>>::vcvtsd2usi(self, op0, op1);
    }
    /// `VCVTSD2USI_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Xmm |
    /// | 2 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtsd2usi_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtsd2usiErEmitter<A, B>,
    {
        <Self as Vcvtsd2usiErEmitter<A, B>>::vcvtsd2usi_er(self, op0, op1);
    }
    /// `VCVTSI2SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Gpd |
    /// | 2 | Xmm, Xmm, Gpq |
    /// | 3 | Xmm, Xmm, Mem |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsi2sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsi2sdEmitter<A, B, C>,
    {
        <Self as Vcvtsi2sdEmitter<A, B, C>>::vcvtsi2sd(self, op0, op1, op2);
    }
    /// `VCVTSI2SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Gpd |
    /// | 2 | Xmm, Xmm, Gpq |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsi2sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsi2sdErEmitter<A, B, C>,
    {
        <Self as Vcvtsi2sdErEmitter<A, B, C>>::vcvtsi2sd_er(self, op0, op1, op2);
    }
    /// `VCVTSI2SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Gpd |
    /// | 2 | Xmm, Xmm, Gpq |
    /// | 3 | Xmm, Xmm, Mem |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsi2ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsi2ssEmitter<A, B, C>,
    {
        <Self as Vcvtsi2ssEmitter<A, B, C>>::vcvtsi2ss(self, op0, op1, op2);
    }
    /// `VCVTSI2SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Gpd |
    /// | 2 | Xmm, Xmm, Gpq |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtsi2ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtsi2ssErEmitter<A, B, C>,
    {
        <Self as Vcvtsi2ssErEmitter<A, B, C>>::vcvtsi2ss_er(self, op0, op1, op2);
    }
    /// `VCVTSS2SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtss2sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtss2sdEmitter<A, B, C>,
    {
        <Self as Vcvtss2sdEmitter<A, B, C>>::vcvtss2sd(self, op0, op1, op2);
    }
    /// `VCVTSS2SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtss2sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtss2sdMaskEmitter<A, B, C>,
    {
        <Self as Vcvtss2sdMaskEmitter<A, B, C>>::vcvtss2sd_mask(self, op0, op1, op2);
    }
    /// `VCVTSS2SD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtss2sd_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtss2sdMaskSaeEmitter<A, B, C>,
    {
        <Self as Vcvtss2sdMaskSaeEmitter<A, B, C>>::vcvtss2sd_mask_sae(self, op0, op1, op2);
    }
    /// `VCVTSS2SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtss2sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtss2sdMaskzEmitter<A, B, C>,
    {
        <Self as Vcvtss2sdMaskzEmitter<A, B, C>>::vcvtss2sd_maskz(self, op0, op1, op2);
    }
    /// `VCVTSS2SD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtss2sd_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtss2sdMaskzSaeEmitter<A, B, C>,
    {
        <Self as Vcvtss2sdMaskzSaeEmitter<A, B, C>>::vcvtss2sd_maskz_sae(self, op0, op1, op2);
    }
    /// `VCVTSS2SD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtss2sd_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtss2sdSaeEmitter<A, B, C>,
    {
        <Self as Vcvtss2sdSaeEmitter<A, B, C>>::vcvtss2sd_sae(self, op0, op1, op2);
    }
    /// `VCVTSS2SI`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Mem |
    /// | 2 | Gpd, Xmm |
    /// | 3 | Gpq, Mem |
    /// | 4 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtss2si<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtss2siEmitter<A, B>,
    {
        <Self as Vcvtss2siEmitter<A, B>>::vcvtss2si(self, op0, op1);
    }
    /// `VCVTSS2SI_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Xmm |
    /// | 2 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtss2si_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtss2siErEmitter<A, B>,
    {
        <Self as Vcvtss2siErEmitter<A, B>>::vcvtss2si_er(self, op0, op1);
    }
    /// `VCVTSS2USI`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Mem |
    /// | 2 | Gpd, Xmm |
    /// | 3 | Gpq, Mem |
    /// | 4 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtss2usi<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtss2usiEmitter<A, B>,
    {
        <Self as Vcvtss2usiEmitter<A, B>>::vcvtss2usi(self, op0, op1);
    }
    /// `VCVTSS2USI_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Xmm |
    /// | 2 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtss2usi_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtss2usiErEmitter<A, B>,
    {
        <Self as Vcvtss2usiErEmitter<A, B>>::vcvtss2usi_er(self, op0, op1);
    }
    /// `VCVTTPD2DQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2dq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2dqEmitter<A, B>,
    {
        <Self as Vcvttpd2dqEmitter<A, B>>::vcvttpd2dq(self, op0, op1);
    }
    /// `VCVTTPD2DQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2dq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2dqMaskEmitter<A, B>,
    {
        <Self as Vcvttpd2dqMaskEmitter<A, B>>::vcvttpd2dq_mask(self, op0, op1);
    }
    /// `VCVTTPD2DQ_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2dq_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2dqMaskSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2dqMaskSaeEmitter<A, B>>::vcvttpd2dq_mask_sae(self, op0, op1);
    }
    /// `VCVTTPD2DQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2dq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2dqMaskzEmitter<A, B>,
    {
        <Self as Vcvttpd2dqMaskzEmitter<A, B>>::vcvttpd2dq_maskz(self, op0, op1);
    }
    /// `VCVTTPD2DQ_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2dq_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2dqMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2dqMaskzSaeEmitter<A, B>>::vcvttpd2dq_maskz_sae(self, op0, op1);
    }
    /// `VCVTTPD2DQ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2dq_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2dqSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2dqSaeEmitter<A, B>>::vcvttpd2dq_sae(self, op0, op1);
    }
    /// `VCVTTPD2UDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2udq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2udqEmitter<A, B>,
    {
        <Self as Vcvttpd2udqEmitter<A, B>>::vcvttpd2udq(self, op0, op1);
    }
    /// `VCVTTPD2UDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2udq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2udqMaskEmitter<A, B>,
    {
        <Self as Vcvttpd2udqMaskEmitter<A, B>>::vcvttpd2udq_mask(self, op0, op1);
    }
    /// `VCVTTPD2UDQ_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2udq_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2udqMaskSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2udqMaskSaeEmitter<A, B>>::vcvttpd2udq_mask_sae(self, op0, op1);
    }
    /// `VCVTTPD2UDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2udq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2udqMaskzEmitter<A, B>,
    {
        <Self as Vcvttpd2udqMaskzEmitter<A, B>>::vcvttpd2udq_maskz(self, op0, op1);
    }
    /// `VCVTTPD2UDQ_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2udq_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2udqMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2udqMaskzSaeEmitter<A, B>>::vcvttpd2udq_maskz_sae(self, op0, op1);
    }
    /// `VCVTTPD2UDQ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2udq_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2udqSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2udqSaeEmitter<A, B>>::vcvttpd2udq_sae(self, op0, op1);
    }
    /// `VCVTTPD2UQQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2uqq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2uqqEmitter<A, B>,
    {
        <Self as Vcvttpd2uqqEmitter<A, B>>::vcvttpd2uqq(self, op0, op1);
    }
    /// `VCVTTPD2UQQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2uqq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2uqqMaskEmitter<A, B>,
    {
        <Self as Vcvttpd2uqqMaskEmitter<A, B>>::vcvttpd2uqq_mask(self, op0, op1);
    }
    /// `VCVTTPD2UQQ_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2uqq_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2uqqMaskSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2uqqMaskSaeEmitter<A, B>>::vcvttpd2uqq_mask_sae(self, op0, op1);
    }
    /// `VCVTTPD2UQQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2uqq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2uqqMaskzEmitter<A, B>,
    {
        <Self as Vcvttpd2uqqMaskzEmitter<A, B>>::vcvttpd2uqq_maskz(self, op0, op1);
    }
    /// `VCVTTPD2UQQ_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2uqq_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2uqqMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2uqqMaskzSaeEmitter<A, B>>::vcvttpd2uqq_maskz_sae(self, op0, op1);
    }
    /// `VCVTTPD2UQQ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttpd2uqq_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttpd2uqqSaeEmitter<A, B>,
    {
        <Self as Vcvttpd2uqqSaeEmitter<A, B>>::vcvttpd2uqq_sae(self, op0, op1);
    }
    /// `VCVTTPS2DQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2dq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2dqEmitter<A, B>,
    {
        <Self as Vcvttps2dqEmitter<A, B>>::vcvttps2dq(self, op0, op1);
    }
    /// `VCVTTPS2DQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2dq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2dqMaskEmitter<A, B>,
    {
        <Self as Vcvttps2dqMaskEmitter<A, B>>::vcvttps2dq_mask(self, op0, op1);
    }
    /// `VCVTTPS2DQ_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2dq_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2dqMaskSaeEmitter<A, B>,
    {
        <Self as Vcvttps2dqMaskSaeEmitter<A, B>>::vcvttps2dq_mask_sae(self, op0, op1);
    }
    /// `VCVTTPS2DQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2dq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2dqMaskzEmitter<A, B>,
    {
        <Self as Vcvttps2dqMaskzEmitter<A, B>>::vcvttps2dq_maskz(self, op0, op1);
    }
    /// `VCVTTPS2DQ_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2dq_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2dqMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvttps2dqMaskzSaeEmitter<A, B>>::vcvttps2dq_maskz_sae(self, op0, op1);
    }
    /// `VCVTTPS2DQ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2dq_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2dqSaeEmitter<A, B>,
    {
        <Self as Vcvttps2dqSaeEmitter<A, B>>::vcvttps2dq_sae(self, op0, op1);
    }
    /// `VCVTTPS2UDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2udq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2udqEmitter<A, B>,
    {
        <Self as Vcvttps2udqEmitter<A, B>>::vcvttps2udq(self, op0, op1);
    }
    /// `VCVTTPS2UDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2udq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2udqMaskEmitter<A, B>,
    {
        <Self as Vcvttps2udqMaskEmitter<A, B>>::vcvttps2udq_mask(self, op0, op1);
    }
    /// `VCVTTPS2UDQ_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2udq_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2udqMaskSaeEmitter<A, B>,
    {
        <Self as Vcvttps2udqMaskSaeEmitter<A, B>>::vcvttps2udq_mask_sae(self, op0, op1);
    }
    /// `VCVTTPS2UDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2udq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2udqMaskzEmitter<A, B>,
    {
        <Self as Vcvttps2udqMaskzEmitter<A, B>>::vcvttps2udq_maskz(self, op0, op1);
    }
    /// `VCVTTPS2UDQ_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2udq_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2udqMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvttps2udqMaskzSaeEmitter<A, B>>::vcvttps2udq_maskz_sae(self, op0, op1);
    }
    /// `VCVTTPS2UDQ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2udq_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2udqSaeEmitter<A, B>,
    {
        <Self as Vcvttps2udqSaeEmitter<A, B>>::vcvttps2udq_sae(self, op0, op1);
    }
    /// `VCVTTPS2UQQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2uqq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2uqqEmitter<A, B>,
    {
        <Self as Vcvttps2uqqEmitter<A, B>>::vcvttps2uqq(self, op0, op1);
    }
    /// `VCVTTPS2UQQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2uqq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2uqqMaskEmitter<A, B>,
    {
        <Self as Vcvttps2uqqMaskEmitter<A, B>>::vcvttps2uqq_mask(self, op0, op1);
    }
    /// `VCVTTPS2UQQ_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2uqq_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2uqqMaskSaeEmitter<A, B>,
    {
        <Self as Vcvttps2uqqMaskSaeEmitter<A, B>>::vcvttps2uqq_mask_sae(self, op0, op1);
    }
    /// `VCVTTPS2UQQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2uqq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2uqqMaskzEmitter<A, B>,
    {
        <Self as Vcvttps2uqqMaskzEmitter<A, B>>::vcvttps2uqq_maskz(self, op0, op1);
    }
    /// `VCVTTPS2UQQ_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2uqq_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2uqqMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvttps2uqqMaskzSaeEmitter<A, B>>::vcvttps2uqq_maskz_sae(self, op0, op1);
    }
    /// `VCVTTPS2UQQ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttps2uqq_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttps2uqqSaeEmitter<A, B>,
    {
        <Self as Vcvttps2uqqSaeEmitter<A, B>>::vcvttps2uqq_sae(self, op0, op1);
    }
    /// `VCVTTSD2SI`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Mem |
    /// | 2 | Gpd, Xmm |
    /// | 3 | Gpq, Mem |
    /// | 4 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttsd2si<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttsd2siEmitter<A, B>,
    {
        <Self as Vcvttsd2siEmitter<A, B>>::vcvttsd2si(self, op0, op1);
    }
    /// `VCVTTSD2SI_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Xmm |
    /// | 2 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttsd2si_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttsd2siSaeEmitter<A, B>,
    {
        <Self as Vcvttsd2siSaeEmitter<A, B>>::vcvttsd2si_sae(self, op0, op1);
    }
    /// `VCVTTSD2USI`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Mem |
    /// | 2 | Gpd, Xmm |
    /// | 3 | Gpq, Mem |
    /// | 4 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttsd2usi<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttsd2usiEmitter<A, B>,
    {
        <Self as Vcvttsd2usiEmitter<A, B>>::vcvttsd2usi(self, op0, op1);
    }
    /// `VCVTTSD2USI_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Xmm |
    /// | 2 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttsd2usi_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttsd2usiSaeEmitter<A, B>,
    {
        <Self as Vcvttsd2usiSaeEmitter<A, B>>::vcvttsd2usi_sae(self, op0, op1);
    }
    /// `VCVTTSS2SI`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Mem |
    /// | 2 | Gpd, Xmm |
    /// | 3 | Gpq, Mem |
    /// | 4 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttss2si<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttss2siEmitter<A, B>,
    {
        <Self as Vcvttss2siEmitter<A, B>>::vcvttss2si(self, op0, op1);
    }
    /// `VCVTTSS2SI_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Xmm |
    /// | 2 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttss2si_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttss2siSaeEmitter<A, B>,
    {
        <Self as Vcvttss2siSaeEmitter<A, B>>::vcvttss2si_sae(self, op0, op1);
    }
    /// `VCVTTSS2USI`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Mem |
    /// | 2 | Gpd, Xmm |
    /// | 3 | Gpq, Mem |
    /// | 4 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttss2usi<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttss2usiEmitter<A, B>,
    {
        <Self as Vcvttss2usiEmitter<A, B>>::vcvttss2usi(self, op0, op1);
    }
    /// `VCVTTSS2USI_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Gpd, Xmm |
    /// | 2 | Gpq, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvttss2usi_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvttss2usiSaeEmitter<A, B>,
    {
        <Self as Vcvttss2usiSaeEmitter<A, B>>::vcvttss2usi_sae(self, op0, op1);
    }
    /// `VCVTUDQ2PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2pd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2pdEmitter<A, B>,
    {
        <Self as Vcvtudq2pdEmitter<A, B>>::vcvtudq2pd(self, op0, op1);
    }
    /// `VCVTUDQ2PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2pd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2pdMaskEmitter<A, B>,
    {
        <Self as Vcvtudq2pdMaskEmitter<A, B>>::vcvtudq2pd_mask(self, op0, op1);
    }
    /// `VCVTUDQ2PD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2pd_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2pdMaskSaeEmitter<A, B>,
    {
        <Self as Vcvtudq2pdMaskSaeEmitter<A, B>>::vcvtudq2pd_mask_sae(self, op0, op1);
    }
    /// `VCVTUDQ2PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2pd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2pdMaskzEmitter<A, B>,
    {
        <Self as Vcvtudq2pdMaskzEmitter<A, B>>::vcvtudq2pd_maskz(self, op0, op1);
    }
    /// `VCVTUDQ2PD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2pd_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2pdMaskzSaeEmitter<A, B>,
    {
        <Self as Vcvtudq2pdMaskzSaeEmitter<A, B>>::vcvtudq2pd_maskz_sae(self, op0, op1);
    }
    /// `VCVTUDQ2PD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2pd_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2pdSaeEmitter<A, B>,
    {
        <Self as Vcvtudq2pdSaeEmitter<A, B>>::vcvtudq2pd_sae(self, op0, op1);
    }
    /// `VCVTUDQ2PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2ps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2psEmitter<A, B>,
    {
        <Self as Vcvtudq2psEmitter<A, B>>::vcvtudq2ps(self, op0, op1);
    }
    /// `VCVTUDQ2PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2ps_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2psErEmitter<A, B>,
    {
        <Self as Vcvtudq2psErEmitter<A, B>>::vcvtudq2ps_er(self, op0, op1);
    }
    /// `VCVTUDQ2PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2ps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2psMaskEmitter<A, B>,
    {
        <Self as Vcvtudq2psMaskEmitter<A, B>>::vcvtudq2ps_mask(self, op0, op1);
    }
    /// `VCVTUDQ2PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2ps_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2psMaskErEmitter<A, B>,
    {
        <Self as Vcvtudq2psMaskErEmitter<A, B>>::vcvtudq2ps_mask_er(self, op0, op1);
    }
    /// `VCVTUDQ2PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2ps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2psMaskzEmitter<A, B>,
    {
        <Self as Vcvtudq2psMaskzEmitter<A, B>>::vcvtudq2ps_maskz(self, op0, op1);
    }
    /// `VCVTUDQ2PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtudq2ps_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtudq2psMaskzErEmitter<A, B>,
    {
        <Self as Vcvtudq2psMaskzErEmitter<A, B>>::vcvtudq2ps_maskz_er(self, op0, op1);
    }
    /// `VCVTUQQ2PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2pd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2pdEmitter<A, B>,
    {
        <Self as Vcvtuqq2pdEmitter<A, B>>::vcvtuqq2pd(self, op0, op1);
    }
    /// `VCVTUQQ2PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2pd_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2pdErEmitter<A, B>,
    {
        <Self as Vcvtuqq2pdErEmitter<A, B>>::vcvtuqq2pd_er(self, op0, op1);
    }
    /// `VCVTUQQ2PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2pd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2pdMaskEmitter<A, B>,
    {
        <Self as Vcvtuqq2pdMaskEmitter<A, B>>::vcvtuqq2pd_mask(self, op0, op1);
    }
    /// `VCVTUQQ2PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2pd_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2pdMaskErEmitter<A, B>,
    {
        <Self as Vcvtuqq2pdMaskErEmitter<A, B>>::vcvtuqq2pd_mask_er(self, op0, op1);
    }
    /// `VCVTUQQ2PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2pd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2pdMaskzEmitter<A, B>,
    {
        <Self as Vcvtuqq2pdMaskzEmitter<A, B>>::vcvtuqq2pd_maskz(self, op0, op1);
    }
    /// `VCVTUQQ2PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2pd_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2pdMaskzErEmitter<A, B>,
    {
        <Self as Vcvtuqq2pdMaskzErEmitter<A, B>>::vcvtuqq2pd_maskz_er(self, op0, op1);
    }
    /// `VCVTUQQ2PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2ps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2psEmitter<A, B>,
    {
        <Self as Vcvtuqq2psEmitter<A, B>>::vcvtuqq2ps(self, op0, op1);
    }
    /// `VCVTUQQ2PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2ps_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2psErEmitter<A, B>,
    {
        <Self as Vcvtuqq2psErEmitter<A, B>>::vcvtuqq2ps_er(self, op0, op1);
    }
    /// `VCVTUQQ2PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2ps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2psMaskEmitter<A, B>,
    {
        <Self as Vcvtuqq2psMaskEmitter<A, B>>::vcvtuqq2ps_mask(self, op0, op1);
    }
    /// `VCVTUQQ2PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2ps_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2psMaskErEmitter<A, B>,
    {
        <Self as Vcvtuqq2psMaskErEmitter<A, B>>::vcvtuqq2ps_mask_er(self, op0, op1);
    }
    /// `VCVTUQQ2PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Xmm, Ymm |
    /// | 4 | Ymm, Mem |
    /// | 5 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2ps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2psMaskzEmitter<A, B>,
    {
        <Self as Vcvtuqq2psMaskzEmitter<A, B>>::vcvtuqq2ps_maskz(self, op0, op1);
    }
    /// `VCVTUQQ2PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vcvtuqq2ps_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vcvtuqq2psMaskzErEmitter<A, B>,
    {
        <Self as Vcvtuqq2psMaskzErEmitter<A, B>>::vcvtuqq2ps_maskz_er(self, op0, op1);
    }
    /// `VCVTUSI2SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Gpd |
    /// | 2 | Xmm, Xmm, Gpq |
    /// | 3 | Xmm, Xmm, Mem |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtusi2sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtusi2sdEmitter<A, B, C>,
    {
        <Self as Vcvtusi2sdEmitter<A, B, C>>::vcvtusi2sd(self, op0, op1, op2);
    }
    /// `VCVTUSI2SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Gpd |
    /// | 2 | Xmm, Xmm, Gpq |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtusi2sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtusi2sdErEmitter<A, B, C>,
    {
        <Self as Vcvtusi2sdErEmitter<A, B, C>>::vcvtusi2sd_er(self, op0, op1, op2);
    }
    /// `VCVTUSI2SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Gpd |
    /// | 2 | Xmm, Xmm, Gpq |
    /// | 3 | Xmm, Xmm, Mem |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtusi2ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtusi2ssEmitter<A, B, C>,
    {
        <Self as Vcvtusi2ssEmitter<A, B, C>>::vcvtusi2ss(self, op0, op1, op2);
    }
    /// `VCVTUSI2SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Gpd |
    /// | 2 | Xmm, Xmm, Gpq |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vcvtusi2ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vcvtusi2ssErEmitter<A, B, C>,
    {
        <Self as Vcvtusi2ssErEmitter<A, B, C>>::vcvtusi2ss_er(self, op0, op1, op2);
    }
    /// `VDIVPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpdEmitter<A, B, C>,
    {
        <Self as VdivpdEmitter<A, B, C>>::vdivpd(self, op0, op1, op2);
    }
    /// `VDIVPD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivpd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpdErEmitter<A, B, C>,
    {
        <Self as VdivpdErEmitter<A, B, C>>::vdivpd_er(self, op0, op1, op2);
    }
    /// `VDIVPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpdMaskEmitter<A, B, C>,
    {
        <Self as VdivpdMaskEmitter<A, B, C>>::vdivpd_mask(self, op0, op1, op2);
    }
    /// `VDIVPD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivpd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpdMaskErEmitter<A, B, C>,
    {
        <Self as VdivpdMaskErEmitter<A, B, C>>::vdivpd_mask_er(self, op0, op1, op2);
    }
    /// `VDIVPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpdMaskzEmitter<A, B, C>,
    {
        <Self as VdivpdMaskzEmitter<A, B, C>>::vdivpd_maskz(self, op0, op1, op2);
    }
    /// `VDIVPD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivpd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpdMaskzErEmitter<A, B, C>,
    {
        <Self as VdivpdMaskzErEmitter<A, B, C>>::vdivpd_maskz_er(self, op0, op1, op2);
    }
    /// `VDIVPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpsEmitter<A, B, C>,
    {
        <Self as VdivpsEmitter<A, B, C>>::vdivps(self, op0, op1, op2);
    }
    /// `VDIVPS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpsErEmitter<A, B, C>,
    {
        <Self as VdivpsErEmitter<A, B, C>>::vdivps_er(self, op0, op1, op2);
    }
    /// `VDIVPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpsMaskEmitter<A, B, C>,
    {
        <Self as VdivpsMaskEmitter<A, B, C>>::vdivps_mask(self, op0, op1, op2);
    }
    /// `VDIVPS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpsMaskErEmitter<A, B, C>,
    {
        <Self as VdivpsMaskErEmitter<A, B, C>>::vdivps_mask_er(self, op0, op1, op2);
    }
    /// `VDIVPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpsMaskzEmitter<A, B, C>,
    {
        <Self as VdivpsMaskzEmitter<A, B, C>>::vdivps_maskz(self, op0, op1, op2);
    }
    /// `VDIVPS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivpsMaskzErEmitter<A, B, C>,
    {
        <Self as VdivpsMaskzErEmitter<A, B, C>>::vdivps_maskz_er(self, op0, op1, op2);
    }
    /// `VDIVSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivsdEmitter<A, B, C>,
    {
        <Self as VdivsdEmitter<A, B, C>>::vdivsd(self, op0, op1, op2);
    }
    /// `VDIVSD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivsd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivsdErEmitter<A, B, C>,
    {
        <Self as VdivsdErEmitter<A, B, C>>::vdivsd_er(self, op0, op1, op2);
    }
    /// `VDIVSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivsdMaskEmitter<A, B, C>,
    {
        <Self as VdivsdMaskEmitter<A, B, C>>::vdivsd_mask(self, op0, op1, op2);
    }
    /// `VDIVSD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivsd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivsdMaskErEmitter<A, B, C>,
    {
        <Self as VdivsdMaskErEmitter<A, B, C>>::vdivsd_mask_er(self, op0, op1, op2);
    }
    /// `VDIVSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivsdMaskzEmitter<A, B, C>,
    {
        <Self as VdivsdMaskzEmitter<A, B, C>>::vdivsd_maskz(self, op0, op1, op2);
    }
    /// `VDIVSD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivsd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivsdMaskzErEmitter<A, B, C>,
    {
        <Self as VdivsdMaskzErEmitter<A, B, C>>::vdivsd_maskz_er(self, op0, op1, op2);
    }
    /// `VDIVSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivssEmitter<A, B, C>,
    {
        <Self as VdivssEmitter<A, B, C>>::vdivss(self, op0, op1, op2);
    }
    /// `VDIVSS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivssErEmitter<A, B, C>,
    {
        <Self as VdivssErEmitter<A, B, C>>::vdivss_er(self, op0, op1, op2);
    }
    /// `VDIVSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivssMaskEmitter<A, B, C>,
    {
        <Self as VdivssMaskEmitter<A, B, C>>::vdivss_mask(self, op0, op1, op2);
    }
    /// `VDIVSS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivssMaskErEmitter<A, B, C>,
    {
        <Self as VdivssMaskErEmitter<A, B, C>>::vdivss_mask_er(self, op0, op1, op2);
    }
    /// `VDIVSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivssMaskzEmitter<A, B, C>,
    {
        <Self as VdivssMaskzEmitter<A, B, C>>::vdivss_maskz(self, op0, op1, op2);
    }
    /// `VDIVSS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vdivss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VdivssMaskzErEmitter<A, B, C>,
    {
        <Self as VdivssMaskzErEmitter<A, B, C>>::vdivss_maskz_er(self, op0, op1, op2);
    }
    /// `VEXPANDPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vexpandpd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VexpandpdEmitter<A, B>,
    {
        <Self as VexpandpdEmitter<A, B>>::vexpandpd(self, op0, op1);
    }
    /// `VEXPANDPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vexpandpd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VexpandpdMaskEmitter<A, B>,
    {
        <Self as VexpandpdMaskEmitter<A, B>>::vexpandpd_mask(self, op0, op1);
    }
    /// `VEXPANDPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vexpandpd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VexpandpdMaskzEmitter<A, B>,
    {
        <Self as VexpandpdMaskzEmitter<A, B>>::vexpandpd_maskz(self, op0, op1);
    }
    /// `VEXPANDPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vexpandps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VexpandpsEmitter<A, B>,
    {
        <Self as VexpandpsEmitter<A, B>>::vexpandps(self, op0, op1);
    }
    /// `VEXPANDPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vexpandps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VexpandpsMaskEmitter<A, B>,
    {
        <Self as VexpandpsMaskEmitter<A, B>>::vexpandps_mask(self, op0, op1);
    }
    /// `VEXPANDPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vexpandps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VexpandpsMaskzEmitter<A, B>,
    {
        <Self as VexpandpsMaskzEmitter<A, B>>::vexpandps_maskz(self, op0, op1);
    }
    /// `VEXTRACTF32X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Ymm, Imm |
    /// | 2 | Mem, Zmm, Imm |
    /// | 3 | Xmm, Ymm, Imm |
    /// | 4 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf32x4<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf32x4Emitter<A, B, C>,
    {
        <Self as Vextractf32x4Emitter<A, B, C>>::vextractf32x4(self, op0, op1, op2);
    }
    /// `VEXTRACTF32X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Ymm, Imm |
    /// | 2 | Mem, Zmm, Imm |
    /// | 3 | Xmm, Ymm, Imm |
    /// | 4 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf32x4_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf32x4MaskEmitter<A, B, C>,
    {
        <Self as Vextractf32x4MaskEmitter<A, B, C>>::vextractf32x4_mask(self, op0, op1, op2);
    }
    /// `VEXTRACTF32X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Ymm, Imm |
    /// | 2 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf32x4_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf32x4MaskzEmitter<A, B, C>,
    {
        <Self as Vextractf32x4MaskzEmitter<A, B, C>>::vextractf32x4_maskz(self, op0, op1, op2);
    }
    /// `VEXTRACTF32X8`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Zmm, Imm |
    /// | 2 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf32x8<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf32x8Emitter<A, B, C>,
    {
        <Self as Vextractf32x8Emitter<A, B, C>>::vextractf32x8(self, op0, op1, op2);
    }
    /// `VEXTRACTF32X8_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Zmm, Imm |
    /// | 2 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf32x8_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf32x8MaskEmitter<A, B, C>,
    {
        <Self as Vextractf32x8MaskEmitter<A, B, C>>::vextractf32x8_mask(self, op0, op1, op2);
    }
    /// `VEXTRACTF32X8_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf32x8_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf32x8MaskzEmitter<A, B, C>,
    {
        <Self as Vextractf32x8MaskzEmitter<A, B, C>>::vextractf32x8_maskz(self, op0, op1, op2);
    }
    /// `VEXTRACTF64X2`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Ymm, Imm |
    /// | 2 | Mem, Zmm, Imm |
    /// | 3 | Xmm, Ymm, Imm |
    /// | 4 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf64x2<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf64x2Emitter<A, B, C>,
    {
        <Self as Vextractf64x2Emitter<A, B, C>>::vextractf64x2(self, op0, op1, op2);
    }
    /// `VEXTRACTF64X2_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Ymm, Imm |
    /// | 2 | Mem, Zmm, Imm |
    /// | 3 | Xmm, Ymm, Imm |
    /// | 4 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf64x2_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf64x2MaskEmitter<A, B, C>,
    {
        <Self as Vextractf64x2MaskEmitter<A, B, C>>::vextractf64x2_mask(self, op0, op1, op2);
    }
    /// `VEXTRACTF64X2_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Ymm, Imm |
    /// | 2 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf64x2_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf64x2MaskzEmitter<A, B, C>,
    {
        <Self as Vextractf64x2MaskzEmitter<A, B, C>>::vextractf64x2_maskz(self, op0, op1, op2);
    }
    /// `VEXTRACTF64X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Zmm, Imm |
    /// | 2 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf64x4<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf64x4Emitter<A, B, C>,
    {
        <Self as Vextractf64x4Emitter<A, B, C>>::vextractf64x4(self, op0, op1, op2);
    }
    /// `VEXTRACTF64X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Zmm, Imm |
    /// | 2 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf64x4_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf64x4MaskEmitter<A, B, C>,
    {
        <Self as Vextractf64x4MaskEmitter<A, B, C>>::vextractf64x4_mask(self, op0, op1, op2);
    }
    /// `VEXTRACTF64X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractf64x4_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextractf64x4MaskzEmitter<A, B, C>,
    {
        <Self as Vextractf64x4MaskzEmitter<A, B, C>>::vextractf64x4_maskz(self, op0, op1, op2);
    }
    /// `VEXTRACTI32X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Ymm, Imm |
    /// | 2 | Mem, Zmm, Imm |
    /// | 3 | Xmm, Ymm, Imm |
    /// | 4 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti32x4<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti32x4Emitter<A, B, C>,
    {
        <Self as Vextracti32x4Emitter<A, B, C>>::vextracti32x4(self, op0, op1, op2);
    }
    /// `VEXTRACTI32X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Ymm, Imm |
    /// | 2 | Mem, Zmm, Imm |
    /// | 3 | Xmm, Ymm, Imm |
    /// | 4 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti32x4_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti32x4MaskEmitter<A, B, C>,
    {
        <Self as Vextracti32x4MaskEmitter<A, B, C>>::vextracti32x4_mask(self, op0, op1, op2);
    }
    /// `VEXTRACTI32X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Ymm, Imm |
    /// | 2 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti32x4_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti32x4MaskzEmitter<A, B, C>,
    {
        <Self as Vextracti32x4MaskzEmitter<A, B, C>>::vextracti32x4_maskz(self, op0, op1, op2);
    }
    /// `VEXTRACTI32X8`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Zmm, Imm |
    /// | 2 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti32x8<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti32x8Emitter<A, B, C>,
    {
        <Self as Vextracti32x8Emitter<A, B, C>>::vextracti32x8(self, op0, op1, op2);
    }
    /// `VEXTRACTI32X8_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Zmm, Imm |
    /// | 2 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti32x8_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti32x8MaskEmitter<A, B, C>,
    {
        <Self as Vextracti32x8MaskEmitter<A, B, C>>::vextracti32x8_mask(self, op0, op1, op2);
    }
    /// `VEXTRACTI32X8_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti32x8_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti32x8MaskzEmitter<A, B, C>,
    {
        <Self as Vextracti32x8MaskzEmitter<A, B, C>>::vextracti32x8_maskz(self, op0, op1, op2);
    }
    /// `VEXTRACTI64X2`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Ymm, Imm |
    /// | 2 | Mem, Zmm, Imm |
    /// | 3 | Xmm, Ymm, Imm |
    /// | 4 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti64x2<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti64x2Emitter<A, B, C>,
    {
        <Self as Vextracti64x2Emitter<A, B, C>>::vextracti64x2(self, op0, op1, op2);
    }
    /// `VEXTRACTI64X2_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Ymm, Imm |
    /// | 2 | Mem, Zmm, Imm |
    /// | 3 | Xmm, Ymm, Imm |
    /// | 4 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti64x2_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti64x2MaskEmitter<A, B, C>,
    {
        <Self as Vextracti64x2MaskEmitter<A, B, C>>::vextracti64x2_mask(self, op0, op1, op2);
    }
    /// `VEXTRACTI64X2_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Ymm, Imm |
    /// | 2 | Xmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti64x2_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti64x2MaskzEmitter<A, B, C>,
    {
        <Self as Vextracti64x2MaskzEmitter<A, B, C>>::vextracti64x2_maskz(self, op0, op1, op2);
    }
    /// `VEXTRACTI64X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Zmm, Imm |
    /// | 2 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti64x4<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti64x4Emitter<A, B, C>,
    {
        <Self as Vextracti64x4Emitter<A, B, C>>::vextracti64x4(self, op0, op1, op2);
    }
    /// `VEXTRACTI64X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Mem, Zmm, Imm |
    /// | 2 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti64x4_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti64x4MaskEmitter<A, B, C>,
    {
        <Self as Vextracti64x4MaskEmitter<A, B, C>>::vextracti64x4_mask(self, op0, op1, op2);
    }
    /// `VEXTRACTI64X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextracti64x4_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vextracti64x4MaskzEmitter<A, B, C>,
    {
        <Self as Vextracti64x4MaskzEmitter<A, B, C>>::vextracti64x4_maskz(self, op0, op1, op2);
    }
    /// `VEXTRACTPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Gpd, Xmm, Imm |
    /// | 2 | Mem, Xmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vextractps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VextractpsEmitter<A, B, C>,
    {
        <Self as VextractpsEmitter<A, B, C>>::vextractps(self, op0, op1, op2);
    }
    /// `VFIXUPIMMPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmpd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpdEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpdEmitter<A, B, C, D>>::vfixupimmpd(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmpd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpdMaskEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpdMaskEmitter<A, B, C, D>>::vfixupimmpd_mask(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMPD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmpd_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpdMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpdMaskSaeEmitter<A, B, C, D>>::vfixupimmpd_mask_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VFIXUPIMMPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmpd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpdMaskzEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpdMaskzEmitter<A, B, C, D>>::vfixupimmpd_maskz(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMPD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmpd_maskz_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpdMaskzSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpdMaskzSaeEmitter<A, B, C, D>>::vfixupimmpd_maskz_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VFIXUPIMMPD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmpd_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpdSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpdSaeEmitter<A, B, C, D>>::vfixupimmpd_sae(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmps<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpsEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpsEmitter<A, B, C, D>>::vfixupimmps(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmps_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpsMaskEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpsMaskEmitter<A, B, C, D>>::vfixupimmps_mask(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMPS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmps_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpsMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpsMaskSaeEmitter<A, B, C, D>>::vfixupimmps_mask_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VFIXUPIMMPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmps_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpsMaskzEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpsMaskzEmitter<A, B, C, D>>::vfixupimmps_maskz(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMPS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmps_maskz_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpsMaskzSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpsMaskzSaeEmitter<A, B, C, D>>::vfixupimmps_maskz_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VFIXUPIMMPS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmps_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmpsSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmpsSaeEmitter<A, B, C, D>>::vfixupimmps_sae(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmsd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmsdEmitter<A, B, C, D>,
    {
        <Self as VfixupimmsdEmitter<A, B, C, D>>::vfixupimmsd(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmsd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmsdMaskEmitter<A, B, C, D>,
    {
        <Self as VfixupimmsdMaskEmitter<A, B, C, D>>::vfixupimmsd_mask(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMSD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmsd_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmsdMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmsdMaskSaeEmitter<A, B, C, D>>::vfixupimmsd_mask_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VFIXUPIMMSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmsd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmsdMaskzEmitter<A, B, C, D>,
    {
        <Self as VfixupimmsdMaskzEmitter<A, B, C, D>>::vfixupimmsd_maskz(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMSD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmsd_maskz_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmsdMaskzSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmsdMaskzSaeEmitter<A, B, C, D>>::vfixupimmsd_maskz_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VFIXUPIMMSD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmsd_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmsdSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmsdSaeEmitter<A, B, C, D>>::vfixupimmsd_sae(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmss<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmssEmitter<A, B, C, D>,
    {
        <Self as VfixupimmssEmitter<A, B, C, D>>::vfixupimmss(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmss_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmssMaskEmitter<A, B, C, D>,
    {
        <Self as VfixupimmssMaskEmitter<A, B, C, D>>::vfixupimmss_mask(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMSS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmss_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmssMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmssMaskSaeEmitter<A, B, C, D>>::vfixupimmss_mask_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VFIXUPIMMSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmss_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmssMaskzEmitter<A, B, C, D>,
    {
        <Self as VfixupimmssMaskzEmitter<A, B, C, D>>::vfixupimmss_maskz(self, op0, op1, op2, op3);
    }
    /// `VFIXUPIMMSS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmss_maskz_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmssMaskzSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmssMaskzSaeEmitter<A, B, C, D>>::vfixupimmss_maskz_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VFIXUPIMMSS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vfixupimmss_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VfixupimmssSaeEmitter<A, B, C, D>,
    {
        <Self as VfixupimmssSaeEmitter<A, B, C, D>>::vfixupimmss_sae(self, op0, op1, op2, op3);
    }
    /// `VFMADD132PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132pdEmitter<A, B, C>,
    {
        <Self as Vfmadd132pdEmitter<A, B, C>>::vfmadd132pd(self, op0, op1, op2);
    }
    /// `VFMADD132PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132pdErEmitter<A, B, C>,
    {
        <Self as Vfmadd132pdErEmitter<A, B, C>>::vfmadd132pd_er(self, op0, op1, op2);
    }
    /// `VFMADD132PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd132pdMaskEmitter<A, B, C>>::vfmadd132pd_mask(self, op0, op1, op2);
    }
    /// `VFMADD132PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd132pdMaskErEmitter<A, B, C>>::vfmadd132pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD132PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd132pdMaskzEmitter<A, B, C>>::vfmadd132pd_maskz(self, op0, op1, op2);
    }
    /// `VFMADD132PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd132pdMaskzErEmitter<A, B, C>>::vfmadd132pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD132PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132psEmitter<A, B, C>,
    {
        <Self as Vfmadd132psEmitter<A, B, C>>::vfmadd132ps(self, op0, op1, op2);
    }
    /// `VFMADD132PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132psErEmitter<A, B, C>,
    {
        <Self as Vfmadd132psErEmitter<A, B, C>>::vfmadd132ps_er(self, op0, op1, op2);
    }
    /// `VFMADD132PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132psMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd132psMaskEmitter<A, B, C>>::vfmadd132ps_mask(self, op0, op1, op2);
    }
    /// `VFMADD132PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd132psMaskErEmitter<A, B, C>>::vfmadd132ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD132PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd132psMaskzEmitter<A, B, C>>::vfmadd132ps_maskz(self, op0, op1, op2);
    }
    /// `VFMADD132PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd132psMaskzErEmitter<A, B, C>>::vfmadd132ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD132SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132sdEmitter<A, B, C>,
    {
        <Self as Vfmadd132sdEmitter<A, B, C>>::vfmadd132sd(self, op0, op1, op2);
    }
    /// `VFMADD132SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132sdErEmitter<A, B, C>,
    {
        <Self as Vfmadd132sdErEmitter<A, B, C>>::vfmadd132sd_er(self, op0, op1, op2);
    }
    /// `VFMADD132SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132sdMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd132sdMaskEmitter<A, B, C>>::vfmadd132sd_mask(self, op0, op1, op2);
    }
    /// `VFMADD132SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd132sdMaskErEmitter<A, B, C>>::vfmadd132sd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD132SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd132sdMaskzEmitter<A, B, C>>::vfmadd132sd_maskz(self, op0, op1, op2);
    }
    /// `VFMADD132SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd132sdMaskzErEmitter<A, B, C>>::vfmadd132sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD132SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132ssEmitter<A, B, C>,
    {
        <Self as Vfmadd132ssEmitter<A, B, C>>::vfmadd132ss(self, op0, op1, op2);
    }
    /// `VFMADD132SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132ssErEmitter<A, B, C>,
    {
        <Self as Vfmadd132ssErEmitter<A, B, C>>::vfmadd132ss_er(self, op0, op1, op2);
    }
    /// `VFMADD132SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132ssMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd132ssMaskEmitter<A, B, C>>::vfmadd132ss_mask(self, op0, op1, op2);
    }
    /// `VFMADD132SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd132ssMaskErEmitter<A, B, C>>::vfmadd132ss_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD132SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd132ssMaskzEmitter<A, B, C>>::vfmadd132ss_maskz(self, op0, op1, op2);
    }
    /// `VFMADD132SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd132ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd132ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd132ssMaskzErEmitter<A, B, C>>::vfmadd132ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD213PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213pdEmitter<A, B, C>,
    {
        <Self as Vfmadd213pdEmitter<A, B, C>>::vfmadd213pd(self, op0, op1, op2);
    }
    /// `VFMADD213PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213pdErEmitter<A, B, C>,
    {
        <Self as Vfmadd213pdErEmitter<A, B, C>>::vfmadd213pd_er(self, op0, op1, op2);
    }
    /// `VFMADD213PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd213pdMaskEmitter<A, B, C>>::vfmadd213pd_mask(self, op0, op1, op2);
    }
    /// `VFMADD213PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd213pdMaskErEmitter<A, B, C>>::vfmadd213pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD213PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd213pdMaskzEmitter<A, B, C>>::vfmadd213pd_maskz(self, op0, op1, op2);
    }
    /// `VFMADD213PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd213pdMaskzErEmitter<A, B, C>>::vfmadd213pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD213PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213psEmitter<A, B, C>,
    {
        <Self as Vfmadd213psEmitter<A, B, C>>::vfmadd213ps(self, op0, op1, op2);
    }
    /// `VFMADD213PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213psErEmitter<A, B, C>,
    {
        <Self as Vfmadd213psErEmitter<A, B, C>>::vfmadd213ps_er(self, op0, op1, op2);
    }
    /// `VFMADD213PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213psMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd213psMaskEmitter<A, B, C>>::vfmadd213ps_mask(self, op0, op1, op2);
    }
    /// `VFMADD213PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd213psMaskErEmitter<A, B, C>>::vfmadd213ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD213PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd213psMaskzEmitter<A, B, C>>::vfmadd213ps_maskz(self, op0, op1, op2);
    }
    /// `VFMADD213PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd213psMaskzErEmitter<A, B, C>>::vfmadd213ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD213SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213sdEmitter<A, B, C>,
    {
        <Self as Vfmadd213sdEmitter<A, B, C>>::vfmadd213sd(self, op0, op1, op2);
    }
    /// `VFMADD213SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213sdErEmitter<A, B, C>,
    {
        <Self as Vfmadd213sdErEmitter<A, B, C>>::vfmadd213sd_er(self, op0, op1, op2);
    }
    /// `VFMADD213SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213sdMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd213sdMaskEmitter<A, B, C>>::vfmadd213sd_mask(self, op0, op1, op2);
    }
    /// `VFMADD213SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd213sdMaskErEmitter<A, B, C>>::vfmadd213sd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD213SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd213sdMaskzEmitter<A, B, C>>::vfmadd213sd_maskz(self, op0, op1, op2);
    }
    /// `VFMADD213SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd213sdMaskzErEmitter<A, B, C>>::vfmadd213sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD213SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213ssEmitter<A, B, C>,
    {
        <Self as Vfmadd213ssEmitter<A, B, C>>::vfmadd213ss(self, op0, op1, op2);
    }
    /// `VFMADD213SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213ssErEmitter<A, B, C>,
    {
        <Self as Vfmadd213ssErEmitter<A, B, C>>::vfmadd213ss_er(self, op0, op1, op2);
    }
    /// `VFMADD213SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213ssMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd213ssMaskEmitter<A, B, C>>::vfmadd213ss_mask(self, op0, op1, op2);
    }
    /// `VFMADD213SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd213ssMaskErEmitter<A, B, C>>::vfmadd213ss_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD213SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd213ssMaskzEmitter<A, B, C>>::vfmadd213ss_maskz(self, op0, op1, op2);
    }
    /// `VFMADD213SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd213ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd213ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd213ssMaskzErEmitter<A, B, C>>::vfmadd213ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD231PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231pdEmitter<A, B, C>,
    {
        <Self as Vfmadd231pdEmitter<A, B, C>>::vfmadd231pd(self, op0, op1, op2);
    }
    /// `VFMADD231PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231pdErEmitter<A, B, C>,
    {
        <Self as Vfmadd231pdErEmitter<A, B, C>>::vfmadd231pd_er(self, op0, op1, op2);
    }
    /// `VFMADD231PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd231pdMaskEmitter<A, B, C>>::vfmadd231pd_mask(self, op0, op1, op2);
    }
    /// `VFMADD231PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd231pdMaskErEmitter<A, B, C>>::vfmadd231pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD231PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd231pdMaskzEmitter<A, B, C>>::vfmadd231pd_maskz(self, op0, op1, op2);
    }
    /// `VFMADD231PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd231pdMaskzErEmitter<A, B, C>>::vfmadd231pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD231PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231psEmitter<A, B, C>,
    {
        <Self as Vfmadd231psEmitter<A, B, C>>::vfmadd231ps(self, op0, op1, op2);
    }
    /// `VFMADD231PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231psErEmitter<A, B, C>,
    {
        <Self as Vfmadd231psErEmitter<A, B, C>>::vfmadd231ps_er(self, op0, op1, op2);
    }
    /// `VFMADD231PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231psMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd231psMaskEmitter<A, B, C>>::vfmadd231ps_mask(self, op0, op1, op2);
    }
    /// `VFMADD231PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd231psMaskErEmitter<A, B, C>>::vfmadd231ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD231PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd231psMaskzEmitter<A, B, C>>::vfmadd231ps_maskz(self, op0, op1, op2);
    }
    /// `VFMADD231PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd231psMaskzErEmitter<A, B, C>>::vfmadd231ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD231SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231sdEmitter<A, B, C>,
    {
        <Self as Vfmadd231sdEmitter<A, B, C>>::vfmadd231sd(self, op0, op1, op2);
    }
    /// `VFMADD231SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231sdErEmitter<A, B, C>,
    {
        <Self as Vfmadd231sdErEmitter<A, B, C>>::vfmadd231sd_er(self, op0, op1, op2);
    }
    /// `VFMADD231SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231sdMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd231sdMaskEmitter<A, B, C>>::vfmadd231sd_mask(self, op0, op1, op2);
    }
    /// `VFMADD231SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd231sdMaskErEmitter<A, B, C>>::vfmadd231sd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD231SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd231sdMaskzEmitter<A, B, C>>::vfmadd231sd_maskz(self, op0, op1, op2);
    }
    /// `VFMADD231SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd231sdMaskzErEmitter<A, B, C>>::vfmadd231sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADD231SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231ssEmitter<A, B, C>,
    {
        <Self as Vfmadd231ssEmitter<A, B, C>>::vfmadd231ss(self, op0, op1, op2);
    }
    /// `VFMADD231SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231ssErEmitter<A, B, C>,
    {
        <Self as Vfmadd231ssErEmitter<A, B, C>>::vfmadd231ss_er(self, op0, op1, op2);
    }
    /// `VFMADD231SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231ssMaskEmitter<A, B, C>,
    {
        <Self as Vfmadd231ssMaskEmitter<A, B, C>>::vfmadd231ss_mask(self, op0, op1, op2);
    }
    /// `VFMADD231SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfmadd231ssMaskErEmitter<A, B, C>>::vfmadd231ss_mask_er(self, op0, op1, op2);
    }
    /// `VFMADD231SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfmadd231ssMaskzEmitter<A, B, C>>::vfmadd231ss_maskz(self, op0, op1, op2);
    }
    /// `VFMADD231SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmadd231ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmadd231ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmadd231ssMaskzErEmitter<A, B, C>>::vfmadd231ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132pdEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132pdEmitter<A, B, C>>::vfmaddsub132pd(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132pdErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132pdErEmitter<A, B, C>>::vfmaddsub132pd_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132pdMaskEmitter<A, B, C>>::vfmaddsub132pd_mask(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132pdMaskErEmitter<A, B, C>>::vfmaddsub132pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132pdMaskzEmitter<A, B, C>>::vfmaddsub132pd_maskz(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132pdMaskzErEmitter<A, B, C>>::vfmaddsub132pd_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMADDSUB132PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132psEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132psEmitter<A, B, C>>::vfmaddsub132ps(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132psErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132psErEmitter<A, B, C>>::vfmaddsub132ps_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132psMaskEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132psMaskEmitter<A, B, C>>::vfmaddsub132ps_mask(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132psMaskErEmitter<A, B, C>>::vfmaddsub132ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132psMaskzEmitter<A, B, C>>::vfmaddsub132ps_maskz(self, op0, op1, op2);
    }
    /// `VFMADDSUB132PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub132ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub132psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub132psMaskzErEmitter<A, B, C>>::vfmaddsub132ps_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMADDSUB213PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213pdEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213pdEmitter<A, B, C>>::vfmaddsub213pd(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213pdErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213pdErEmitter<A, B, C>>::vfmaddsub213pd_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213pdMaskEmitter<A, B, C>>::vfmaddsub213pd_mask(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213pdMaskErEmitter<A, B, C>>::vfmaddsub213pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213pdMaskzEmitter<A, B, C>>::vfmaddsub213pd_maskz(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213pdMaskzErEmitter<A, B, C>>::vfmaddsub213pd_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMADDSUB213PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213psEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213psEmitter<A, B, C>>::vfmaddsub213ps(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213psErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213psErEmitter<A, B, C>>::vfmaddsub213ps_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213psMaskEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213psMaskEmitter<A, B, C>>::vfmaddsub213ps_mask(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213psMaskErEmitter<A, B, C>>::vfmaddsub213ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213psMaskzEmitter<A, B, C>>::vfmaddsub213ps_maskz(self, op0, op1, op2);
    }
    /// `VFMADDSUB213PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub213ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub213psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub213psMaskzErEmitter<A, B, C>>::vfmaddsub213ps_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMADDSUB231PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231pdEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231pdEmitter<A, B, C>>::vfmaddsub231pd(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231pdErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231pdErEmitter<A, B, C>>::vfmaddsub231pd_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231pdMaskEmitter<A, B, C>>::vfmaddsub231pd_mask(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231pdMaskErEmitter<A, B, C>>::vfmaddsub231pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231pdMaskzEmitter<A, B, C>>::vfmaddsub231pd_maskz(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231pdMaskzErEmitter<A, B, C>>::vfmaddsub231pd_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMADDSUB231PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231psEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231psEmitter<A, B, C>>::vfmaddsub231ps(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231psErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231psErEmitter<A, B, C>>::vfmaddsub231ps_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231psMaskEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231psMaskEmitter<A, B, C>>::vfmaddsub231ps_mask(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231psMaskErEmitter<A, B, C>>::vfmaddsub231ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231psMaskzEmitter<A, B, C>>::vfmaddsub231ps_maskz(self, op0, op1, op2);
    }
    /// `VFMADDSUB231PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmaddsub231ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmaddsub231psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmaddsub231psMaskzErEmitter<A, B, C>>::vfmaddsub231ps_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMSUB132PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132pdEmitter<A, B, C>,
    {
        <Self as Vfmsub132pdEmitter<A, B, C>>::vfmsub132pd(self, op0, op1, op2);
    }
    /// `VFMSUB132PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132pdErEmitter<A, B, C>,
    {
        <Self as Vfmsub132pdErEmitter<A, B, C>>::vfmsub132pd_er(self, op0, op1, op2);
    }
    /// `VFMSUB132PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub132pdMaskEmitter<A, B, C>>::vfmsub132pd_mask(self, op0, op1, op2);
    }
    /// `VFMSUB132PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub132pdMaskErEmitter<A, B, C>>::vfmsub132pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB132PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub132pdMaskzEmitter<A, B, C>>::vfmsub132pd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB132PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub132pdMaskzErEmitter<A, B, C>>::vfmsub132pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB132PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132psEmitter<A, B, C>,
    {
        <Self as Vfmsub132psEmitter<A, B, C>>::vfmsub132ps(self, op0, op1, op2);
    }
    /// `VFMSUB132PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132psErEmitter<A, B, C>,
    {
        <Self as Vfmsub132psErEmitter<A, B, C>>::vfmsub132ps_er(self, op0, op1, op2);
    }
    /// `VFMSUB132PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132psMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub132psMaskEmitter<A, B, C>>::vfmsub132ps_mask(self, op0, op1, op2);
    }
    /// `VFMSUB132PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub132psMaskErEmitter<A, B, C>>::vfmsub132ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB132PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub132psMaskzEmitter<A, B, C>>::vfmsub132ps_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB132PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub132psMaskzErEmitter<A, B, C>>::vfmsub132ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB132SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132sdEmitter<A, B, C>,
    {
        <Self as Vfmsub132sdEmitter<A, B, C>>::vfmsub132sd(self, op0, op1, op2);
    }
    /// `VFMSUB132SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132sdErEmitter<A, B, C>,
    {
        <Self as Vfmsub132sdErEmitter<A, B, C>>::vfmsub132sd_er(self, op0, op1, op2);
    }
    /// `VFMSUB132SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132sdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub132sdMaskEmitter<A, B, C>>::vfmsub132sd_mask(self, op0, op1, op2);
    }
    /// `VFMSUB132SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub132sdMaskErEmitter<A, B, C>>::vfmsub132sd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB132SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub132sdMaskzEmitter<A, B, C>>::vfmsub132sd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB132SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub132sdMaskzErEmitter<A, B, C>>::vfmsub132sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB132SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132ssEmitter<A, B, C>,
    {
        <Self as Vfmsub132ssEmitter<A, B, C>>::vfmsub132ss(self, op0, op1, op2);
    }
    /// `VFMSUB132SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132ssErEmitter<A, B, C>,
    {
        <Self as Vfmsub132ssErEmitter<A, B, C>>::vfmsub132ss_er(self, op0, op1, op2);
    }
    /// `VFMSUB132SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132ssMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub132ssMaskEmitter<A, B, C>>::vfmsub132ss_mask(self, op0, op1, op2);
    }
    /// `VFMSUB132SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub132ssMaskErEmitter<A, B, C>>::vfmsub132ss_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB132SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub132ssMaskzEmitter<A, B, C>>::vfmsub132ss_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB132SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub132ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub132ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub132ssMaskzErEmitter<A, B, C>>::vfmsub132ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB213PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213pdEmitter<A, B, C>,
    {
        <Self as Vfmsub213pdEmitter<A, B, C>>::vfmsub213pd(self, op0, op1, op2);
    }
    /// `VFMSUB213PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213pdErEmitter<A, B, C>,
    {
        <Self as Vfmsub213pdErEmitter<A, B, C>>::vfmsub213pd_er(self, op0, op1, op2);
    }
    /// `VFMSUB213PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub213pdMaskEmitter<A, B, C>>::vfmsub213pd_mask(self, op0, op1, op2);
    }
    /// `VFMSUB213PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub213pdMaskErEmitter<A, B, C>>::vfmsub213pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB213PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub213pdMaskzEmitter<A, B, C>>::vfmsub213pd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB213PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub213pdMaskzErEmitter<A, B, C>>::vfmsub213pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB213PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213psEmitter<A, B, C>,
    {
        <Self as Vfmsub213psEmitter<A, B, C>>::vfmsub213ps(self, op0, op1, op2);
    }
    /// `VFMSUB213PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213psErEmitter<A, B, C>,
    {
        <Self as Vfmsub213psErEmitter<A, B, C>>::vfmsub213ps_er(self, op0, op1, op2);
    }
    /// `VFMSUB213PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213psMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub213psMaskEmitter<A, B, C>>::vfmsub213ps_mask(self, op0, op1, op2);
    }
    /// `VFMSUB213PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub213psMaskErEmitter<A, B, C>>::vfmsub213ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB213PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub213psMaskzEmitter<A, B, C>>::vfmsub213ps_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB213PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub213psMaskzErEmitter<A, B, C>>::vfmsub213ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB213SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213sdEmitter<A, B, C>,
    {
        <Self as Vfmsub213sdEmitter<A, B, C>>::vfmsub213sd(self, op0, op1, op2);
    }
    /// `VFMSUB213SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213sdErEmitter<A, B, C>,
    {
        <Self as Vfmsub213sdErEmitter<A, B, C>>::vfmsub213sd_er(self, op0, op1, op2);
    }
    /// `VFMSUB213SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213sdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub213sdMaskEmitter<A, B, C>>::vfmsub213sd_mask(self, op0, op1, op2);
    }
    /// `VFMSUB213SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub213sdMaskErEmitter<A, B, C>>::vfmsub213sd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB213SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub213sdMaskzEmitter<A, B, C>>::vfmsub213sd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB213SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub213sdMaskzErEmitter<A, B, C>>::vfmsub213sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB213SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213ssEmitter<A, B, C>,
    {
        <Self as Vfmsub213ssEmitter<A, B, C>>::vfmsub213ss(self, op0, op1, op2);
    }
    /// `VFMSUB213SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213ssErEmitter<A, B, C>,
    {
        <Self as Vfmsub213ssErEmitter<A, B, C>>::vfmsub213ss_er(self, op0, op1, op2);
    }
    /// `VFMSUB213SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213ssMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub213ssMaskEmitter<A, B, C>>::vfmsub213ss_mask(self, op0, op1, op2);
    }
    /// `VFMSUB213SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub213ssMaskErEmitter<A, B, C>>::vfmsub213ss_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB213SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub213ssMaskzEmitter<A, B, C>>::vfmsub213ss_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB213SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub213ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub213ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub213ssMaskzErEmitter<A, B, C>>::vfmsub213ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB231PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231pdEmitter<A, B, C>,
    {
        <Self as Vfmsub231pdEmitter<A, B, C>>::vfmsub231pd(self, op0, op1, op2);
    }
    /// `VFMSUB231PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231pdErEmitter<A, B, C>,
    {
        <Self as Vfmsub231pdErEmitter<A, B, C>>::vfmsub231pd_er(self, op0, op1, op2);
    }
    /// `VFMSUB231PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub231pdMaskEmitter<A, B, C>>::vfmsub231pd_mask(self, op0, op1, op2);
    }
    /// `VFMSUB231PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub231pdMaskErEmitter<A, B, C>>::vfmsub231pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB231PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub231pdMaskzEmitter<A, B, C>>::vfmsub231pd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB231PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub231pdMaskzErEmitter<A, B, C>>::vfmsub231pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB231PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231psEmitter<A, B, C>,
    {
        <Self as Vfmsub231psEmitter<A, B, C>>::vfmsub231ps(self, op0, op1, op2);
    }
    /// `VFMSUB231PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231psErEmitter<A, B, C>,
    {
        <Self as Vfmsub231psErEmitter<A, B, C>>::vfmsub231ps_er(self, op0, op1, op2);
    }
    /// `VFMSUB231PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231psMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub231psMaskEmitter<A, B, C>>::vfmsub231ps_mask(self, op0, op1, op2);
    }
    /// `VFMSUB231PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub231psMaskErEmitter<A, B, C>>::vfmsub231ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB231PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub231psMaskzEmitter<A, B, C>>::vfmsub231ps_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB231PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub231psMaskzErEmitter<A, B, C>>::vfmsub231ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB231SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231sdEmitter<A, B, C>,
    {
        <Self as Vfmsub231sdEmitter<A, B, C>>::vfmsub231sd(self, op0, op1, op2);
    }
    /// `VFMSUB231SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231sdErEmitter<A, B, C>,
    {
        <Self as Vfmsub231sdErEmitter<A, B, C>>::vfmsub231sd_er(self, op0, op1, op2);
    }
    /// `VFMSUB231SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231sdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub231sdMaskEmitter<A, B, C>>::vfmsub231sd_mask(self, op0, op1, op2);
    }
    /// `VFMSUB231SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub231sdMaskErEmitter<A, B, C>>::vfmsub231sd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB231SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub231sdMaskzEmitter<A, B, C>>::vfmsub231sd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB231SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub231sdMaskzErEmitter<A, B, C>>::vfmsub231sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUB231SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231ssEmitter<A, B, C>,
    {
        <Self as Vfmsub231ssEmitter<A, B, C>>::vfmsub231ss(self, op0, op1, op2);
    }
    /// `VFMSUB231SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231ssErEmitter<A, B, C>,
    {
        <Self as Vfmsub231ssErEmitter<A, B, C>>::vfmsub231ss_er(self, op0, op1, op2);
    }
    /// `VFMSUB231SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231ssMaskEmitter<A, B, C>,
    {
        <Self as Vfmsub231ssMaskEmitter<A, B, C>>::vfmsub231ss_mask(self, op0, op1, op2);
    }
    /// `VFMSUB231SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsub231ssMaskErEmitter<A, B, C>>::vfmsub231ss_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUB231SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsub231ssMaskzEmitter<A, B, C>>::vfmsub231ss_maskz(self, op0, op1, op2);
    }
    /// `VFMSUB231SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsub231ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsub231ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsub231ssMaskzErEmitter<A, B, C>>::vfmsub231ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132pdEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132pdEmitter<A, B, C>>::vfmsubadd132pd(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132pdErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132pdErEmitter<A, B, C>>::vfmsubadd132pd_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132pdMaskEmitter<A, B, C>>::vfmsubadd132pd_mask(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132pdMaskErEmitter<A, B, C>>::vfmsubadd132pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132pdMaskzEmitter<A, B, C>>::vfmsubadd132pd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132pdMaskzErEmitter<A, B, C>>::vfmsubadd132pd_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMSUBADD132PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132psEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132psEmitter<A, B, C>>::vfmsubadd132ps(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132psErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132psErEmitter<A, B, C>>::vfmsubadd132ps_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132psMaskEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132psMaskEmitter<A, B, C>>::vfmsubadd132ps_mask(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132psMaskErEmitter<A, B, C>>::vfmsubadd132ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132psMaskzEmitter<A, B, C>>::vfmsubadd132ps_maskz(self, op0, op1, op2);
    }
    /// `VFMSUBADD132PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd132ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd132psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd132psMaskzErEmitter<A, B, C>>::vfmsubadd132ps_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMSUBADD213PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213pdEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213pdEmitter<A, B, C>>::vfmsubadd213pd(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213pdErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213pdErEmitter<A, B, C>>::vfmsubadd213pd_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213pdMaskEmitter<A, B, C>>::vfmsubadd213pd_mask(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213pdMaskErEmitter<A, B, C>>::vfmsubadd213pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213pdMaskzEmitter<A, B, C>>::vfmsubadd213pd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213pdMaskzErEmitter<A, B, C>>::vfmsubadd213pd_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMSUBADD213PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213psEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213psEmitter<A, B, C>>::vfmsubadd213ps(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213psErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213psErEmitter<A, B, C>>::vfmsubadd213ps_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213psMaskEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213psMaskEmitter<A, B, C>>::vfmsubadd213ps_mask(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213psMaskErEmitter<A, B, C>>::vfmsubadd213ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213psMaskzEmitter<A, B, C>>::vfmsubadd213ps_maskz(self, op0, op1, op2);
    }
    /// `VFMSUBADD213PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd213ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd213psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd213psMaskzErEmitter<A, B, C>>::vfmsubadd213ps_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMSUBADD231PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231pdEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231pdEmitter<A, B, C>>::vfmsubadd231pd(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231pdErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231pdErEmitter<A, B, C>>::vfmsubadd231pd_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231pdMaskEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231pdMaskEmitter<A, B, C>>::vfmsubadd231pd_mask(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231pdMaskErEmitter<A, B, C>>::vfmsubadd231pd_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231pdMaskzEmitter<A, B, C>>::vfmsubadd231pd_maskz(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231pdMaskzErEmitter<A, B, C>>::vfmsubadd231pd_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFMSUBADD231PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231psEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231psEmitter<A, B, C>>::vfmsubadd231ps(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231psErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231psErEmitter<A, B, C>>::vfmsubadd231ps_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231psMaskEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231psMaskEmitter<A, B, C>>::vfmsubadd231ps_mask(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231psMaskErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231psMaskErEmitter<A, B, C>>::vfmsubadd231ps_mask_er(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231psMaskzEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231psMaskzEmitter<A, B, C>>::vfmsubadd231ps_maskz(self, op0, op1, op2);
    }
    /// `VFMSUBADD231PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfmsubadd231ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfmsubadd231psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfmsubadd231psMaskzErEmitter<A, B, C>>::vfmsubadd231ps_maskz_er(
            self, op0, op1, op2,
        );
    }
    /// `VFNMADD132PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132pdEmitter<A, B, C>,
    {
        <Self as Vfnmadd132pdEmitter<A, B, C>>::vfnmadd132pd(self, op0, op1, op2);
    }
    /// `VFNMADD132PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132pdErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132pdErEmitter<A, B, C>>::vfnmadd132pd_er(self, op0, op1, op2);
    }
    /// `VFNMADD132PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132pdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd132pdMaskEmitter<A, B, C>>::vfnmadd132pd_mask(self, op0, op1, op2);
    }
    /// `VFNMADD132PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132pdMaskErEmitter<A, B, C>>::vfnmadd132pd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD132PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd132pdMaskzEmitter<A, B, C>>::vfnmadd132pd_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD132PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132pdMaskzErEmitter<A, B, C>>::vfnmadd132pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD132PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132psEmitter<A, B, C>,
    {
        <Self as Vfnmadd132psEmitter<A, B, C>>::vfnmadd132ps(self, op0, op1, op2);
    }
    /// `VFNMADD132PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132psErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132psErEmitter<A, B, C>>::vfnmadd132ps_er(self, op0, op1, op2);
    }
    /// `VFNMADD132PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132psMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd132psMaskEmitter<A, B, C>>::vfnmadd132ps_mask(self, op0, op1, op2);
    }
    /// `VFNMADD132PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132psMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132psMaskErEmitter<A, B, C>>::vfnmadd132ps_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD132PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132psMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd132psMaskzEmitter<A, B, C>>::vfnmadd132ps_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD132PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132psMaskzErEmitter<A, B, C>>::vfnmadd132ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD132SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132sdEmitter<A, B, C>,
    {
        <Self as Vfnmadd132sdEmitter<A, B, C>>::vfnmadd132sd(self, op0, op1, op2);
    }
    /// `VFNMADD132SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132sdErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132sdErEmitter<A, B, C>>::vfnmadd132sd_er(self, op0, op1, op2);
    }
    /// `VFNMADD132SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132sdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd132sdMaskEmitter<A, B, C>>::vfnmadd132sd_mask(self, op0, op1, op2);
    }
    /// `VFNMADD132SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132sdMaskErEmitter<A, B, C>>::vfnmadd132sd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD132SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd132sdMaskzEmitter<A, B, C>>::vfnmadd132sd_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD132SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132sdMaskzErEmitter<A, B, C>>::vfnmadd132sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD132SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132ssEmitter<A, B, C>,
    {
        <Self as Vfnmadd132ssEmitter<A, B, C>>::vfnmadd132ss(self, op0, op1, op2);
    }
    /// `VFNMADD132SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132ssErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132ssErEmitter<A, B, C>>::vfnmadd132ss_er(self, op0, op1, op2);
    }
    /// `VFNMADD132SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132ssMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd132ssMaskEmitter<A, B, C>>::vfnmadd132ss_mask(self, op0, op1, op2);
    }
    /// `VFNMADD132SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132ssMaskErEmitter<A, B, C>>::vfnmadd132ss_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD132SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd132ssMaskzEmitter<A, B, C>>::vfnmadd132ss_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD132SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd132ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd132ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd132ssMaskzErEmitter<A, B, C>>::vfnmadd132ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD213PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213pdEmitter<A, B, C>,
    {
        <Self as Vfnmadd213pdEmitter<A, B, C>>::vfnmadd213pd(self, op0, op1, op2);
    }
    /// `VFNMADD213PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213pdErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213pdErEmitter<A, B, C>>::vfnmadd213pd_er(self, op0, op1, op2);
    }
    /// `VFNMADD213PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213pdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd213pdMaskEmitter<A, B, C>>::vfnmadd213pd_mask(self, op0, op1, op2);
    }
    /// `VFNMADD213PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213pdMaskErEmitter<A, B, C>>::vfnmadd213pd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD213PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd213pdMaskzEmitter<A, B, C>>::vfnmadd213pd_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD213PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213pdMaskzErEmitter<A, B, C>>::vfnmadd213pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD213PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213psEmitter<A, B, C>,
    {
        <Self as Vfnmadd213psEmitter<A, B, C>>::vfnmadd213ps(self, op0, op1, op2);
    }
    /// `VFNMADD213PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213psErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213psErEmitter<A, B, C>>::vfnmadd213ps_er(self, op0, op1, op2);
    }
    /// `VFNMADD213PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213psMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd213psMaskEmitter<A, B, C>>::vfnmadd213ps_mask(self, op0, op1, op2);
    }
    /// `VFNMADD213PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213psMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213psMaskErEmitter<A, B, C>>::vfnmadd213ps_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD213PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213psMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd213psMaskzEmitter<A, B, C>>::vfnmadd213ps_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD213PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213psMaskzErEmitter<A, B, C>>::vfnmadd213ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD213SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213sdEmitter<A, B, C>,
    {
        <Self as Vfnmadd213sdEmitter<A, B, C>>::vfnmadd213sd(self, op0, op1, op2);
    }
    /// `VFNMADD213SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213sdErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213sdErEmitter<A, B, C>>::vfnmadd213sd_er(self, op0, op1, op2);
    }
    /// `VFNMADD213SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213sdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd213sdMaskEmitter<A, B, C>>::vfnmadd213sd_mask(self, op0, op1, op2);
    }
    /// `VFNMADD213SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213sdMaskErEmitter<A, B, C>>::vfnmadd213sd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD213SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd213sdMaskzEmitter<A, B, C>>::vfnmadd213sd_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD213SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213sdMaskzErEmitter<A, B, C>>::vfnmadd213sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD213SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213ssEmitter<A, B, C>,
    {
        <Self as Vfnmadd213ssEmitter<A, B, C>>::vfnmadd213ss(self, op0, op1, op2);
    }
    /// `VFNMADD213SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213ssErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213ssErEmitter<A, B, C>>::vfnmadd213ss_er(self, op0, op1, op2);
    }
    /// `VFNMADD213SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213ssMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd213ssMaskEmitter<A, B, C>>::vfnmadd213ss_mask(self, op0, op1, op2);
    }
    /// `VFNMADD213SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213ssMaskErEmitter<A, B, C>>::vfnmadd213ss_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD213SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd213ssMaskzEmitter<A, B, C>>::vfnmadd213ss_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD213SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd213ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd213ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd213ssMaskzErEmitter<A, B, C>>::vfnmadd213ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD231PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231pdEmitter<A, B, C>,
    {
        <Self as Vfnmadd231pdEmitter<A, B, C>>::vfnmadd231pd(self, op0, op1, op2);
    }
    /// `VFNMADD231PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231pdErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231pdErEmitter<A, B, C>>::vfnmadd231pd_er(self, op0, op1, op2);
    }
    /// `VFNMADD231PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231pdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd231pdMaskEmitter<A, B, C>>::vfnmadd231pd_mask(self, op0, op1, op2);
    }
    /// `VFNMADD231PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231pdMaskErEmitter<A, B, C>>::vfnmadd231pd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD231PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd231pdMaskzEmitter<A, B, C>>::vfnmadd231pd_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD231PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231pdMaskzErEmitter<A, B, C>>::vfnmadd231pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD231PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231psEmitter<A, B, C>,
    {
        <Self as Vfnmadd231psEmitter<A, B, C>>::vfnmadd231ps(self, op0, op1, op2);
    }
    /// `VFNMADD231PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231psErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231psErEmitter<A, B, C>>::vfnmadd231ps_er(self, op0, op1, op2);
    }
    /// `VFNMADD231PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231psMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd231psMaskEmitter<A, B, C>>::vfnmadd231ps_mask(self, op0, op1, op2);
    }
    /// `VFNMADD231PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231psMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231psMaskErEmitter<A, B, C>>::vfnmadd231ps_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD231PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231psMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd231psMaskzEmitter<A, B, C>>::vfnmadd231ps_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD231PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231psMaskzErEmitter<A, B, C>>::vfnmadd231ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD231SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231sdEmitter<A, B, C>,
    {
        <Self as Vfnmadd231sdEmitter<A, B, C>>::vfnmadd231sd(self, op0, op1, op2);
    }
    /// `VFNMADD231SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231sdErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231sdErEmitter<A, B, C>>::vfnmadd231sd_er(self, op0, op1, op2);
    }
    /// `VFNMADD231SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231sdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd231sdMaskEmitter<A, B, C>>::vfnmadd231sd_mask(self, op0, op1, op2);
    }
    /// `VFNMADD231SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231sdMaskErEmitter<A, B, C>>::vfnmadd231sd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD231SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd231sdMaskzEmitter<A, B, C>>::vfnmadd231sd_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD231SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231sdMaskzErEmitter<A, B, C>>::vfnmadd231sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMADD231SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231ssEmitter<A, B, C>,
    {
        <Self as Vfnmadd231ssEmitter<A, B, C>>::vfnmadd231ss(self, op0, op1, op2);
    }
    /// `VFNMADD231SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231ssErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231ssErEmitter<A, B, C>>::vfnmadd231ss_er(self, op0, op1, op2);
    }
    /// `VFNMADD231SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231ssMaskEmitter<A, B, C>,
    {
        <Self as Vfnmadd231ssMaskEmitter<A, B, C>>::vfnmadd231ss_mask(self, op0, op1, op2);
    }
    /// `VFNMADD231SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231ssMaskErEmitter<A, B, C>>::vfnmadd231ss_mask_er(self, op0, op1, op2);
    }
    /// `VFNMADD231SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmadd231ssMaskzEmitter<A, B, C>>::vfnmadd231ss_maskz(self, op0, op1, op2);
    }
    /// `VFNMADD231SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmadd231ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmadd231ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmadd231ssMaskzErEmitter<A, B, C>>::vfnmadd231ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132pdEmitter<A, B, C>,
    {
        <Self as Vfnmsub132pdEmitter<A, B, C>>::vfnmsub132pd(self, op0, op1, op2);
    }
    /// `VFNMSUB132PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132pdErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132pdErEmitter<A, B, C>>::vfnmsub132pd_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132pdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub132pdMaskEmitter<A, B, C>>::vfnmsub132pd_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB132PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132pdMaskErEmitter<A, B, C>>::vfnmsub132pd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub132pdMaskzEmitter<A, B, C>>::vfnmsub132pd_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB132PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132pdMaskzErEmitter<A, B, C>>::vfnmsub132pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132psEmitter<A, B, C>,
    {
        <Self as Vfnmsub132psEmitter<A, B, C>>::vfnmsub132ps(self, op0, op1, op2);
    }
    /// `VFNMSUB132PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132psErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132psErEmitter<A, B, C>>::vfnmsub132ps_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132psMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub132psMaskEmitter<A, B, C>>::vfnmsub132ps_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB132PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132psMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132psMaskErEmitter<A, B, C>>::vfnmsub132ps_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132psMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub132psMaskzEmitter<A, B, C>>::vfnmsub132ps_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB132PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132psMaskzErEmitter<A, B, C>>::vfnmsub132ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132sdEmitter<A, B, C>,
    {
        <Self as Vfnmsub132sdEmitter<A, B, C>>::vfnmsub132sd(self, op0, op1, op2);
    }
    /// `VFNMSUB132SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132sdErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132sdErEmitter<A, B, C>>::vfnmsub132sd_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132sdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub132sdMaskEmitter<A, B, C>>::vfnmsub132sd_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB132SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132sdMaskErEmitter<A, B, C>>::vfnmsub132sd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub132sdMaskzEmitter<A, B, C>>::vfnmsub132sd_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB132SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132sdMaskzErEmitter<A, B, C>>::vfnmsub132sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132ssEmitter<A, B, C>,
    {
        <Self as Vfnmsub132ssEmitter<A, B, C>>::vfnmsub132ss(self, op0, op1, op2);
    }
    /// `VFNMSUB132SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132ssErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132ssErEmitter<A, B, C>>::vfnmsub132ss_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132ssMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub132ssMaskEmitter<A, B, C>>::vfnmsub132ss_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB132SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132ssMaskErEmitter<A, B, C>>::vfnmsub132ss_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB132SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub132ssMaskzEmitter<A, B, C>>::vfnmsub132ss_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB132SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub132ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub132ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub132ssMaskzErEmitter<A, B, C>>::vfnmsub132ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213pdEmitter<A, B, C>,
    {
        <Self as Vfnmsub213pdEmitter<A, B, C>>::vfnmsub213pd(self, op0, op1, op2);
    }
    /// `VFNMSUB213PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213pdErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213pdErEmitter<A, B, C>>::vfnmsub213pd_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213pdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub213pdMaskEmitter<A, B, C>>::vfnmsub213pd_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB213PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213pdMaskErEmitter<A, B, C>>::vfnmsub213pd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub213pdMaskzEmitter<A, B, C>>::vfnmsub213pd_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB213PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213pdMaskzErEmitter<A, B, C>>::vfnmsub213pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213psEmitter<A, B, C>,
    {
        <Self as Vfnmsub213psEmitter<A, B, C>>::vfnmsub213ps(self, op0, op1, op2);
    }
    /// `VFNMSUB213PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213psErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213psErEmitter<A, B, C>>::vfnmsub213ps_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213psMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub213psMaskEmitter<A, B, C>>::vfnmsub213ps_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB213PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213psMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213psMaskErEmitter<A, B, C>>::vfnmsub213ps_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213psMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub213psMaskzEmitter<A, B, C>>::vfnmsub213ps_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB213PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213psMaskzErEmitter<A, B, C>>::vfnmsub213ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213sdEmitter<A, B, C>,
    {
        <Self as Vfnmsub213sdEmitter<A, B, C>>::vfnmsub213sd(self, op0, op1, op2);
    }
    /// `VFNMSUB213SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213sdErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213sdErEmitter<A, B, C>>::vfnmsub213sd_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213sdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub213sdMaskEmitter<A, B, C>>::vfnmsub213sd_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB213SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213sdMaskErEmitter<A, B, C>>::vfnmsub213sd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub213sdMaskzEmitter<A, B, C>>::vfnmsub213sd_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB213SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213sdMaskzErEmitter<A, B, C>>::vfnmsub213sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213ssEmitter<A, B, C>,
    {
        <Self as Vfnmsub213ssEmitter<A, B, C>>::vfnmsub213ss(self, op0, op1, op2);
    }
    /// `VFNMSUB213SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213ssErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213ssErEmitter<A, B, C>>::vfnmsub213ss_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213ssMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub213ssMaskEmitter<A, B, C>>::vfnmsub213ss_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB213SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213ssMaskErEmitter<A, B, C>>::vfnmsub213ss_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB213SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub213ssMaskzEmitter<A, B, C>>::vfnmsub213ss_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB213SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub213ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub213ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub213ssMaskzErEmitter<A, B, C>>::vfnmsub213ss_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231pdEmitter<A, B, C>,
    {
        <Self as Vfnmsub231pdEmitter<A, B, C>>::vfnmsub231pd(self, op0, op1, op2);
    }
    /// `VFNMSUB231PD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231pd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231pdErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231pdErEmitter<A, B, C>>::vfnmsub231pd_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231pdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub231pdMaskEmitter<A, B, C>>::vfnmsub231pd_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB231PD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231pd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231pdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231pdMaskErEmitter<A, B, C>>::vfnmsub231pd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231pdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub231pdMaskzEmitter<A, B, C>>::vfnmsub231pd_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB231PD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231pd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231pdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231pdMaskzErEmitter<A, B, C>>::vfnmsub231pd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231psEmitter<A, B, C>,
    {
        <Self as Vfnmsub231psEmitter<A, B, C>>::vfnmsub231ps(self, op0, op1, op2);
    }
    /// `VFNMSUB231PS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231psErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231psErEmitter<A, B, C>>::vfnmsub231ps_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231psMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub231psMaskEmitter<A, B, C>>::vfnmsub231ps_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB231PS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231psMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231psMaskErEmitter<A, B, C>>::vfnmsub231ps_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231psMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub231psMaskzEmitter<A, B, C>>::vfnmsub231ps_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB231PS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231psMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231psMaskzErEmitter<A, B, C>>::vfnmsub231ps_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231sdEmitter<A, B, C>,
    {
        <Self as Vfnmsub231sdEmitter<A, B, C>>::vfnmsub231sd(self, op0, op1, op2);
    }
    /// `VFNMSUB231SD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231sd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231sdErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231sdErEmitter<A, B, C>>::vfnmsub231sd_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231sdMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub231sdMaskEmitter<A, B, C>>::vfnmsub231sd_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB231SD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231sd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231sdMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231sdMaskErEmitter<A, B, C>>::vfnmsub231sd_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231sdMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub231sdMaskzEmitter<A, B, C>>::vfnmsub231sd_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB231SD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231sd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231sdMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231sdMaskzErEmitter<A, B, C>>::vfnmsub231sd_maskz_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231ssEmitter<A, B, C>,
    {
        <Self as Vfnmsub231ssEmitter<A, B, C>>::vfnmsub231ss(self, op0, op1, op2);
    }
    /// `VFNMSUB231SS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231ssErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231ssErEmitter<A, B, C>>::vfnmsub231ss_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231ssMaskEmitter<A, B, C>,
    {
        <Self as Vfnmsub231ssMaskEmitter<A, B, C>>::vfnmsub231ss_mask(self, op0, op1, op2);
    }
    /// `VFNMSUB231SS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231ssMaskErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231ssMaskErEmitter<A, B, C>>::vfnmsub231ss_mask_er(self, op0, op1, op2);
    }
    /// `VFNMSUB231SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231ssMaskzEmitter<A, B, C>,
    {
        <Self as Vfnmsub231ssMaskzEmitter<A, B, C>>::vfnmsub231ss_maskz(self, op0, op1, op2);
    }
    /// `VFNMSUB231SS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vfnmsub231ss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vfnmsub231ssMaskzErEmitter<A, B, C>,
    {
        <Self as Vfnmsub231ssMaskzErEmitter<A, B, C>>::vfnmsub231ss_maskz_er(self, op0, op1, op2);
    }
    /// `VGATHERDPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// | 3 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgatherdpd_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgatherdpdEmitter_2<A, B>,
    {
        <Self as VgatherdpdEmitter_2<A, B>>::vgatherdpd_2(self, op0, op1);
    }
    /// `VGATHERDPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// | 3 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgatherdps_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgatherdpsEmitter_2<A, B>,
    {
        <Self as VgatherdpsEmitter_2<A, B>>::vgatherdps_2(self, op0, op1);
    }
    /// `VGATHERQPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// | 3 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgatherqpd_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgatherqpdEmitter_2<A, B>,
    {
        <Self as VgatherqpdEmitter_2<A, B>>::vgatherqpd_2(self, op0, op1);
    }
    /// `VGATHERQPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgatherqps_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgatherqpsEmitter_2<A, B>,
    {
        <Self as VgatherqpsEmitter_2<A, B>>::vgatherqps_2(self, op0, op1);
    }
    /// `VGETEXPPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexppd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppdEmitter<A, B>,
    {
        <Self as VgetexppdEmitter<A, B>>::vgetexppd(self, op0, op1);
    }
    /// `VGETEXPPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexppd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppdMaskEmitter<A, B>,
    {
        <Self as VgetexppdMaskEmitter<A, B>>::vgetexppd_mask(self, op0, op1);
    }
    /// `VGETEXPPD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexppd_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppdMaskSaeEmitter<A, B>,
    {
        <Self as VgetexppdMaskSaeEmitter<A, B>>::vgetexppd_mask_sae(self, op0, op1);
    }
    /// `VGETEXPPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexppd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppdMaskzEmitter<A, B>,
    {
        <Self as VgetexppdMaskzEmitter<A, B>>::vgetexppd_maskz(self, op0, op1);
    }
    /// `VGETEXPPD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexppd_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppdMaskzSaeEmitter<A, B>,
    {
        <Self as VgetexppdMaskzSaeEmitter<A, B>>::vgetexppd_maskz_sae(self, op0, op1);
    }
    /// `VGETEXPPD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexppd_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppdSaeEmitter<A, B>,
    {
        <Self as VgetexppdSaeEmitter<A, B>>::vgetexppd_sae(self, op0, op1);
    }
    /// `VGETEXPPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexpps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppsEmitter<A, B>,
    {
        <Self as VgetexppsEmitter<A, B>>::vgetexpps(self, op0, op1);
    }
    /// `VGETEXPPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexpps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppsMaskEmitter<A, B>,
    {
        <Self as VgetexppsMaskEmitter<A, B>>::vgetexpps_mask(self, op0, op1);
    }
    /// `VGETEXPPS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexpps_mask_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppsMaskSaeEmitter<A, B>,
    {
        <Self as VgetexppsMaskSaeEmitter<A, B>>::vgetexpps_mask_sae(self, op0, op1);
    }
    /// `VGETEXPPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexpps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppsMaskzEmitter<A, B>,
    {
        <Self as VgetexppsMaskzEmitter<A, B>>::vgetexpps_maskz(self, op0, op1);
    }
    /// `VGETEXPPS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexpps_maskz_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppsMaskzSaeEmitter<A, B>,
    {
        <Self as VgetexppsMaskzSaeEmitter<A, B>>::vgetexpps_maskz_sae(self, op0, op1);
    }
    /// `VGETEXPPS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vgetexpps_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VgetexppsSaeEmitter<A, B>,
    {
        <Self as VgetexppsSaeEmitter<A, B>>::vgetexpps_sae(self, op0, op1);
    }
    /// `VGETEXPSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpsdEmitter<A, B, C>,
    {
        <Self as VgetexpsdEmitter<A, B, C>>::vgetexpsd(self, op0, op1, op2);
    }
    /// `VGETEXPSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpsdMaskEmitter<A, B, C>,
    {
        <Self as VgetexpsdMaskEmitter<A, B, C>>::vgetexpsd_mask(self, op0, op1, op2);
    }
    /// `VGETEXPSD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpsd_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpsdMaskSaeEmitter<A, B, C>,
    {
        <Self as VgetexpsdMaskSaeEmitter<A, B, C>>::vgetexpsd_mask_sae(self, op0, op1, op2);
    }
    /// `VGETEXPSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpsdMaskzEmitter<A, B, C>,
    {
        <Self as VgetexpsdMaskzEmitter<A, B, C>>::vgetexpsd_maskz(self, op0, op1, op2);
    }
    /// `VGETEXPSD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpsd_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpsdMaskzSaeEmitter<A, B, C>,
    {
        <Self as VgetexpsdMaskzSaeEmitter<A, B, C>>::vgetexpsd_maskz_sae(self, op0, op1, op2);
    }
    /// `VGETEXPSD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpsd_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpsdSaeEmitter<A, B, C>,
    {
        <Self as VgetexpsdSaeEmitter<A, B, C>>::vgetexpsd_sae(self, op0, op1, op2);
    }
    /// `VGETEXPSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpssEmitter<A, B, C>,
    {
        <Self as VgetexpssEmitter<A, B, C>>::vgetexpss(self, op0, op1, op2);
    }
    /// `VGETEXPSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpssMaskEmitter<A, B, C>,
    {
        <Self as VgetexpssMaskEmitter<A, B, C>>::vgetexpss_mask(self, op0, op1, op2);
    }
    /// `VGETEXPSS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpss_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpssMaskSaeEmitter<A, B, C>,
    {
        <Self as VgetexpssMaskSaeEmitter<A, B, C>>::vgetexpss_mask_sae(self, op0, op1, op2);
    }
    /// `VGETEXPSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpssMaskzEmitter<A, B, C>,
    {
        <Self as VgetexpssMaskzEmitter<A, B, C>>::vgetexpss_maskz(self, op0, op1, op2);
    }
    /// `VGETEXPSS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpss_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpssMaskzSaeEmitter<A, B, C>,
    {
        <Self as VgetexpssMaskzSaeEmitter<A, B, C>>::vgetexpss_maskz_sae(self, op0, op1, op2);
    }
    /// `VGETEXPSS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetexpss_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetexpssSaeEmitter<A, B, C>,
    {
        <Self as VgetexpssSaeEmitter<A, B, C>>::vgetexpss_sae(self, op0, op1, op2);
    }
    /// `VGETMANTPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpdEmitter<A, B, C>,
    {
        <Self as VgetmantpdEmitter<A, B, C>>::vgetmantpd(self, op0, op1, op2);
    }
    /// `VGETMANTPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpdMaskEmitter<A, B, C>,
    {
        <Self as VgetmantpdMaskEmitter<A, B, C>>::vgetmantpd_mask(self, op0, op1, op2);
    }
    /// `VGETMANTPD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantpd_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpdMaskSaeEmitter<A, B, C>,
    {
        <Self as VgetmantpdMaskSaeEmitter<A, B, C>>::vgetmantpd_mask_sae(self, op0, op1, op2);
    }
    /// `VGETMANTPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpdMaskzEmitter<A, B, C>,
    {
        <Self as VgetmantpdMaskzEmitter<A, B, C>>::vgetmantpd_maskz(self, op0, op1, op2);
    }
    /// `VGETMANTPD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantpd_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpdMaskzSaeEmitter<A, B, C>,
    {
        <Self as VgetmantpdMaskzSaeEmitter<A, B, C>>::vgetmantpd_maskz_sae(self, op0, op1, op2);
    }
    /// `VGETMANTPD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantpd_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpdSaeEmitter<A, B, C>,
    {
        <Self as VgetmantpdSaeEmitter<A, B, C>>::vgetmantpd_sae(self, op0, op1, op2);
    }
    /// `VGETMANTPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpsEmitter<A, B, C>,
    {
        <Self as VgetmantpsEmitter<A, B, C>>::vgetmantps(self, op0, op1, op2);
    }
    /// `VGETMANTPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpsMaskEmitter<A, B, C>,
    {
        <Self as VgetmantpsMaskEmitter<A, B, C>>::vgetmantps_mask(self, op0, op1, op2);
    }
    /// `VGETMANTPS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantps_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpsMaskSaeEmitter<A, B, C>,
    {
        <Self as VgetmantpsMaskSaeEmitter<A, B, C>>::vgetmantps_mask_sae(self, op0, op1, op2);
    }
    /// `VGETMANTPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpsMaskzEmitter<A, B, C>,
    {
        <Self as VgetmantpsMaskzEmitter<A, B, C>>::vgetmantps_maskz(self, op0, op1, op2);
    }
    /// `VGETMANTPS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantps_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpsMaskzSaeEmitter<A, B, C>,
    {
        <Self as VgetmantpsMaskzSaeEmitter<A, B, C>>::vgetmantps_maskz_sae(self, op0, op1, op2);
    }
    /// `VGETMANTPS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vgetmantps_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VgetmantpsSaeEmitter<A, B, C>,
    {
        <Self as VgetmantpsSaeEmitter<A, B, C>>::vgetmantps_sae(self, op0, op1, op2);
    }
    /// `VGETMANTSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantsd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantsdEmitter<A, B, C, D>,
    {
        <Self as VgetmantsdEmitter<A, B, C, D>>::vgetmantsd(self, op0, op1, op2, op3);
    }
    /// `VGETMANTSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantsd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantsdMaskEmitter<A, B, C, D>,
    {
        <Self as VgetmantsdMaskEmitter<A, B, C, D>>::vgetmantsd_mask(self, op0, op1, op2, op3);
    }
    /// `VGETMANTSD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantsd_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantsdMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VgetmantsdMaskSaeEmitter<A, B, C, D>>::vgetmantsd_mask_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VGETMANTSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantsd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantsdMaskzEmitter<A, B, C, D>,
    {
        <Self as VgetmantsdMaskzEmitter<A, B, C, D>>::vgetmantsd_maskz(self, op0, op1, op2, op3);
    }
    /// `VGETMANTSD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantsd_maskz_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantsdMaskzSaeEmitter<A, B, C, D>,
    {
        <Self as VgetmantsdMaskzSaeEmitter<A, B, C, D>>::vgetmantsd_maskz_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VGETMANTSD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantsd_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantsdSaeEmitter<A, B, C, D>,
    {
        <Self as VgetmantsdSaeEmitter<A, B, C, D>>::vgetmantsd_sae(self, op0, op1, op2, op3);
    }
    /// `VGETMANTSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantss<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantssEmitter<A, B, C, D>,
    {
        <Self as VgetmantssEmitter<A, B, C, D>>::vgetmantss(self, op0, op1, op2, op3);
    }
    /// `VGETMANTSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantss_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantssMaskEmitter<A, B, C, D>,
    {
        <Self as VgetmantssMaskEmitter<A, B, C, D>>::vgetmantss_mask(self, op0, op1, op2, op3);
    }
    /// `VGETMANTSS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantss_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantssMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VgetmantssMaskSaeEmitter<A, B, C, D>>::vgetmantss_mask_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VGETMANTSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantss_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantssMaskzEmitter<A, B, C, D>,
    {
        <Self as VgetmantssMaskzEmitter<A, B, C, D>>::vgetmantss_maskz(self, op0, op1, op2, op3);
    }
    /// `VGETMANTSS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantss_maskz_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantssMaskzSaeEmitter<A, B, C, D>,
    {
        <Self as VgetmantssMaskzSaeEmitter<A, B, C, D>>::vgetmantss_maskz_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VGETMANTSS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vgetmantss_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VgetmantssSaeEmitter<A, B, C, D>,
    {
        <Self as VgetmantssSaeEmitter<A, B, C, D>>::vgetmantss_sae(self, op0, op1, op2, op3);
    }
    /// `VINSERTF32X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Xmm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinsertf32x4<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinsertf32x4Emitter<A, B, C, D>,
    {
        <Self as Vinsertf32x4Emitter<A, B, C, D>>::vinsertf32x4(self, op0, op1, op2, op3);
    }
    /// `VINSERTF32X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Xmm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinsertf32x4_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinsertf32x4MaskEmitter<A, B, C, D>,
    {
        <Self as Vinsertf32x4MaskEmitter<A, B, C, D>>::vinsertf32x4_mask(self, op0, op1, op2, op3);
    }
    /// `VINSERTF32X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Xmm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinsertf32x4_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinsertf32x4MaskzEmitter<A, B, C, D>,
    {
        <Self as Vinsertf32x4MaskzEmitter<A, B, C, D>>::vinsertf32x4_maskz(
            self, op0, op1, op2, op3,
        );
    }
    /// `VINSERTF64X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Mem, Imm |
    /// | 2 | Zmm, Zmm, Ymm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinsertf64x4<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinsertf64x4Emitter<A, B, C, D>,
    {
        <Self as Vinsertf64x4Emitter<A, B, C, D>>::vinsertf64x4(self, op0, op1, op2, op3);
    }
    /// `VINSERTF64X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Mem, Imm |
    /// | 2 | Zmm, Zmm, Ymm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinsertf64x4_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinsertf64x4MaskEmitter<A, B, C, D>,
    {
        <Self as Vinsertf64x4MaskEmitter<A, B, C, D>>::vinsertf64x4_mask(self, op0, op1, op2, op3);
    }
    /// `VINSERTF64X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Mem, Imm |
    /// | 2 | Zmm, Zmm, Ymm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinsertf64x4_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinsertf64x4MaskzEmitter<A, B, C, D>,
    {
        <Self as Vinsertf64x4MaskzEmitter<A, B, C, D>>::vinsertf64x4_maskz(
            self, op0, op1, op2, op3,
        );
    }
    /// `VINSERTI32X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Xmm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinserti32x4<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinserti32x4Emitter<A, B, C, D>,
    {
        <Self as Vinserti32x4Emitter<A, B, C, D>>::vinserti32x4(self, op0, op1, op2, op3);
    }
    /// `VINSERTI32X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Xmm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinserti32x4_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinserti32x4MaskEmitter<A, B, C, D>,
    {
        <Self as Vinserti32x4MaskEmitter<A, B, C, D>>::vinserti32x4_mask(self, op0, op1, op2, op3);
    }
    /// `VINSERTI32X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Xmm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinserti32x4_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinserti32x4MaskzEmitter<A, B, C, D>,
    {
        <Self as Vinserti32x4MaskzEmitter<A, B, C, D>>::vinserti32x4_maskz(
            self, op0, op1, op2, op3,
        );
    }
    /// `VINSERTI64X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Mem, Imm |
    /// | 2 | Zmm, Zmm, Ymm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinserti64x4<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinserti64x4Emitter<A, B, C, D>,
    {
        <Self as Vinserti64x4Emitter<A, B, C, D>>::vinserti64x4(self, op0, op1, op2, op3);
    }
    /// `VINSERTI64X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Mem, Imm |
    /// | 2 | Zmm, Zmm, Ymm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinserti64x4_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinserti64x4MaskEmitter<A, B, C, D>,
    {
        <Self as Vinserti64x4MaskEmitter<A, B, C, D>>::vinserti64x4_mask(self, op0, op1, op2, op3);
    }
    /// `VINSERTI64X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Zmm, Zmm, Mem, Imm |
    /// | 2 | Zmm, Zmm, Ymm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinserti64x4_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vinserti64x4MaskzEmitter<A, B, C, D>,
    {
        <Self as Vinserti64x4MaskzEmitter<A, B, C, D>>::vinserti64x4_maskz(
            self, op0, op1, op2, op3,
        );
    }
    /// `VINSERTPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vinsertps<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VinsertpsEmitter<A, B, C, D>,
    {
        <Self as VinsertpsEmitter<A, B, C, D>>::vinsertps(self, op0, op1, op2, op3);
    }
    /// `VMAXPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpdEmitter<A, B, C>,
    {
        <Self as VmaxpdEmitter<A, B, C>>::vmaxpd(self, op0, op1, op2);
    }
    /// `VMAXPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpdMaskEmitter<A, B, C>,
    {
        <Self as VmaxpdMaskEmitter<A, B, C>>::vmaxpd_mask(self, op0, op1, op2);
    }
    /// `VMAXPD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxpd_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpdMaskSaeEmitter<A, B, C>,
    {
        <Self as VmaxpdMaskSaeEmitter<A, B, C>>::vmaxpd_mask_sae(self, op0, op1, op2);
    }
    /// `VMAXPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpdMaskzEmitter<A, B, C>,
    {
        <Self as VmaxpdMaskzEmitter<A, B, C>>::vmaxpd_maskz(self, op0, op1, op2);
    }
    /// `VMAXPD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxpd_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpdMaskzSaeEmitter<A, B, C>,
    {
        <Self as VmaxpdMaskzSaeEmitter<A, B, C>>::vmaxpd_maskz_sae(self, op0, op1, op2);
    }
    /// `VMAXPD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxpd_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpdSaeEmitter<A, B, C>,
    {
        <Self as VmaxpdSaeEmitter<A, B, C>>::vmaxpd_sae(self, op0, op1, op2);
    }
    /// `VMAXPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpsEmitter<A, B, C>,
    {
        <Self as VmaxpsEmitter<A, B, C>>::vmaxps(self, op0, op1, op2);
    }
    /// `VMAXPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpsMaskEmitter<A, B, C>,
    {
        <Self as VmaxpsMaskEmitter<A, B, C>>::vmaxps_mask(self, op0, op1, op2);
    }
    /// `VMAXPS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxps_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpsMaskSaeEmitter<A, B, C>,
    {
        <Self as VmaxpsMaskSaeEmitter<A, B, C>>::vmaxps_mask_sae(self, op0, op1, op2);
    }
    /// `VMAXPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpsMaskzEmitter<A, B, C>,
    {
        <Self as VmaxpsMaskzEmitter<A, B, C>>::vmaxps_maskz(self, op0, op1, op2);
    }
    /// `VMAXPS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxps_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpsMaskzSaeEmitter<A, B, C>,
    {
        <Self as VmaxpsMaskzSaeEmitter<A, B, C>>::vmaxps_maskz_sae(self, op0, op1, op2);
    }
    /// `VMAXPS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxps_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxpsSaeEmitter<A, B, C>,
    {
        <Self as VmaxpsSaeEmitter<A, B, C>>::vmaxps_sae(self, op0, op1, op2);
    }
    /// `VMAXSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxsdEmitter<A, B, C>,
    {
        <Self as VmaxsdEmitter<A, B, C>>::vmaxsd(self, op0, op1, op2);
    }
    /// `VMAXSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxsdMaskEmitter<A, B, C>,
    {
        <Self as VmaxsdMaskEmitter<A, B, C>>::vmaxsd_mask(self, op0, op1, op2);
    }
    /// `VMAXSD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxsd_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxsdMaskSaeEmitter<A, B, C>,
    {
        <Self as VmaxsdMaskSaeEmitter<A, B, C>>::vmaxsd_mask_sae(self, op0, op1, op2);
    }
    /// `VMAXSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxsdMaskzEmitter<A, B, C>,
    {
        <Self as VmaxsdMaskzEmitter<A, B, C>>::vmaxsd_maskz(self, op0, op1, op2);
    }
    /// `VMAXSD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxsd_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxsdMaskzSaeEmitter<A, B, C>,
    {
        <Self as VmaxsdMaskzSaeEmitter<A, B, C>>::vmaxsd_maskz_sae(self, op0, op1, op2);
    }
    /// `VMAXSD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxsd_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxsdSaeEmitter<A, B, C>,
    {
        <Self as VmaxsdSaeEmitter<A, B, C>>::vmaxsd_sae(self, op0, op1, op2);
    }
    /// `VMAXSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxssEmitter<A, B, C>,
    {
        <Self as VmaxssEmitter<A, B, C>>::vmaxss(self, op0, op1, op2);
    }
    /// `VMAXSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxssMaskEmitter<A, B, C>,
    {
        <Self as VmaxssMaskEmitter<A, B, C>>::vmaxss_mask(self, op0, op1, op2);
    }
    /// `VMAXSS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxss_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxssMaskSaeEmitter<A, B, C>,
    {
        <Self as VmaxssMaskSaeEmitter<A, B, C>>::vmaxss_mask_sae(self, op0, op1, op2);
    }
    /// `VMAXSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxssMaskzEmitter<A, B, C>,
    {
        <Self as VmaxssMaskzEmitter<A, B, C>>::vmaxss_maskz(self, op0, op1, op2);
    }
    /// `VMAXSS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxss_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxssMaskzSaeEmitter<A, B, C>,
    {
        <Self as VmaxssMaskzSaeEmitter<A, B, C>>::vmaxss_maskz_sae(self, op0, op1, op2);
    }
    /// `VMAXSS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmaxss_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmaxssSaeEmitter<A, B, C>,
    {
        <Self as VmaxssSaeEmitter<A, B, C>>::vmaxss_sae(self, op0, op1, op2);
    }
    /// `VMINPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpdEmitter<A, B, C>,
    {
        <Self as VminpdEmitter<A, B, C>>::vminpd(self, op0, op1, op2);
    }
    /// `VMINPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpdMaskEmitter<A, B, C>,
    {
        <Self as VminpdMaskEmitter<A, B, C>>::vminpd_mask(self, op0, op1, op2);
    }
    /// `VMINPD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminpd_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpdMaskSaeEmitter<A, B, C>,
    {
        <Self as VminpdMaskSaeEmitter<A, B, C>>::vminpd_mask_sae(self, op0, op1, op2);
    }
    /// `VMINPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpdMaskzEmitter<A, B, C>,
    {
        <Self as VminpdMaskzEmitter<A, B, C>>::vminpd_maskz(self, op0, op1, op2);
    }
    /// `VMINPD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminpd_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpdMaskzSaeEmitter<A, B, C>,
    {
        <Self as VminpdMaskzSaeEmitter<A, B, C>>::vminpd_maskz_sae(self, op0, op1, op2);
    }
    /// `VMINPD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminpd_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpdSaeEmitter<A, B, C>,
    {
        <Self as VminpdSaeEmitter<A, B, C>>::vminpd_sae(self, op0, op1, op2);
    }
    /// `VMINPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpsEmitter<A, B, C>,
    {
        <Self as VminpsEmitter<A, B, C>>::vminps(self, op0, op1, op2);
    }
    /// `VMINPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpsMaskEmitter<A, B, C>,
    {
        <Self as VminpsMaskEmitter<A, B, C>>::vminps_mask(self, op0, op1, op2);
    }
    /// `VMINPS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminps_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpsMaskSaeEmitter<A, B, C>,
    {
        <Self as VminpsMaskSaeEmitter<A, B, C>>::vminps_mask_sae(self, op0, op1, op2);
    }
    /// `VMINPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpsMaskzEmitter<A, B, C>,
    {
        <Self as VminpsMaskzEmitter<A, B, C>>::vminps_maskz(self, op0, op1, op2);
    }
    /// `VMINPS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminps_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpsMaskzSaeEmitter<A, B, C>,
    {
        <Self as VminpsMaskzSaeEmitter<A, B, C>>::vminps_maskz_sae(self, op0, op1, op2);
    }
    /// `VMINPS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminps_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminpsSaeEmitter<A, B, C>,
    {
        <Self as VminpsSaeEmitter<A, B, C>>::vminps_sae(self, op0, op1, op2);
    }
    /// `VMINSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminsdEmitter<A, B, C>,
    {
        <Self as VminsdEmitter<A, B, C>>::vminsd(self, op0, op1, op2);
    }
    /// `VMINSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminsdMaskEmitter<A, B, C>,
    {
        <Self as VminsdMaskEmitter<A, B, C>>::vminsd_mask(self, op0, op1, op2);
    }
    /// `VMINSD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminsd_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminsdMaskSaeEmitter<A, B, C>,
    {
        <Self as VminsdMaskSaeEmitter<A, B, C>>::vminsd_mask_sae(self, op0, op1, op2);
    }
    /// `VMINSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminsdMaskzEmitter<A, B, C>,
    {
        <Self as VminsdMaskzEmitter<A, B, C>>::vminsd_maskz(self, op0, op1, op2);
    }
    /// `VMINSD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminsd_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminsdMaskzSaeEmitter<A, B, C>,
    {
        <Self as VminsdMaskzSaeEmitter<A, B, C>>::vminsd_maskz_sae(self, op0, op1, op2);
    }
    /// `VMINSD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminsd_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminsdSaeEmitter<A, B, C>,
    {
        <Self as VminsdSaeEmitter<A, B, C>>::vminsd_sae(self, op0, op1, op2);
    }
    /// `VMINSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminssEmitter<A, B, C>,
    {
        <Self as VminssEmitter<A, B, C>>::vminss(self, op0, op1, op2);
    }
    /// `VMINSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminssMaskEmitter<A, B, C>,
    {
        <Self as VminssMaskEmitter<A, B, C>>::vminss_mask(self, op0, op1, op2);
    }
    /// `VMINSS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminss_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminssMaskSaeEmitter<A, B, C>,
    {
        <Self as VminssMaskSaeEmitter<A, B, C>>::vminss_mask_sae(self, op0, op1, op2);
    }
    /// `VMINSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminssMaskzEmitter<A, B, C>,
    {
        <Self as VminssMaskzEmitter<A, B, C>>::vminss_maskz(self, op0, op1, op2);
    }
    /// `VMINSS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminss_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminssMaskzSaeEmitter<A, B, C>,
    {
        <Self as VminssMaskzSaeEmitter<A, B, C>>::vminss_maskz_sae(self, op0, op1, op2);
    }
    /// `VMINSS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vminss_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VminssSaeEmitter<A, B, C>,
    {
        <Self as VminssSaeEmitter<A, B, C>>::vminss_sae(self, op0, op1, op2);
    }
    /// `VMOVAPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovapd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovapdEmitter<A, B>,
    {
        <Self as VmovapdEmitter<A, B>>::vmovapd(self, op0, op1);
    }
    /// `VMOVAPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovapd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovapdMaskEmitter<A, B>,
    {
        <Self as VmovapdMaskEmitter<A, B>>::vmovapd_mask(self, op0, op1);
    }
    /// `VMOVAPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovapd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovapdMaskzEmitter<A, B>,
    {
        <Self as VmovapdMaskzEmitter<A, B>>::vmovapd_maskz(self, op0, op1);
    }
    /// `VMOVAPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovaps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovapsEmitter<A, B>,
    {
        <Self as VmovapsEmitter<A, B>>::vmovaps(self, op0, op1);
    }
    /// `VMOVAPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovaps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovapsMaskEmitter<A, B>,
    {
        <Self as VmovapsMaskEmitter<A, B>>::vmovaps_mask(self, op0, op1);
    }
    /// `VMOVAPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovaps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovapsMaskzEmitter<A, B>,
    {
        <Self as VmovapsMaskzEmitter<A, B>>::vmovaps_maskz(self, op0, op1);
    }
    /// `VMOVDDUP`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovddup<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovddupEmitter<A, B>,
    {
        <Self as VmovddupEmitter<A, B>>::vmovddup(self, op0, op1);
    }
    /// `VMOVDDUP_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovddup_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovddupMaskEmitter<A, B>,
    {
        <Self as VmovddupMaskEmitter<A, B>>::vmovddup_mask(self, op0, op1);
    }
    /// `VMOVDDUP_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovddup_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovddupMaskzEmitter<A, B>,
    {
        <Self as VmovddupMaskzEmitter<A, B>>::vmovddup_maskz(self, op0, op1);
    }
    /// `VMOVDQA32`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqa32<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqa32Emitter<A, B>,
    {
        <Self as Vmovdqa32Emitter<A, B>>::vmovdqa32(self, op0, op1);
    }
    /// `VMOVDQA32_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqa32_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqa32MaskEmitter<A, B>,
    {
        <Self as Vmovdqa32MaskEmitter<A, B>>::vmovdqa32_mask(self, op0, op1);
    }
    /// `VMOVDQA32_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqa32_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqa32MaskzEmitter<A, B>,
    {
        <Self as Vmovdqa32MaskzEmitter<A, B>>::vmovdqa32_maskz(self, op0, op1);
    }
    /// `VMOVDQA64`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqa64<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqa64Emitter<A, B>,
    {
        <Self as Vmovdqa64Emitter<A, B>>::vmovdqa64(self, op0, op1);
    }
    /// `VMOVDQA64_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqa64_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqa64MaskEmitter<A, B>,
    {
        <Self as Vmovdqa64MaskEmitter<A, B>>::vmovdqa64_mask(self, op0, op1);
    }
    /// `VMOVDQA64_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqa64_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqa64MaskzEmitter<A, B>,
    {
        <Self as Vmovdqa64MaskzEmitter<A, B>>::vmovdqa64_maskz(self, op0, op1);
    }
    /// `VMOVDQU32`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqu32<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqu32Emitter<A, B>,
    {
        <Self as Vmovdqu32Emitter<A, B>>::vmovdqu32(self, op0, op1);
    }
    /// `VMOVDQU32_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqu32_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqu32MaskEmitter<A, B>,
    {
        <Self as Vmovdqu32MaskEmitter<A, B>>::vmovdqu32_mask(self, op0, op1);
    }
    /// `VMOVDQU32_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqu32_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqu32MaskzEmitter<A, B>,
    {
        <Self as Vmovdqu32MaskzEmitter<A, B>>::vmovdqu32_maskz(self, op0, op1);
    }
    /// `VMOVDQU64`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqu64<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqu64Emitter<A, B>,
    {
        <Self as Vmovdqu64Emitter<A, B>>::vmovdqu64(self, op0, op1);
    }
    /// `VMOVDQU64_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqu64_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqu64MaskEmitter<A, B>,
    {
        <Self as Vmovdqu64MaskEmitter<A, B>>::vmovdqu64_mask(self, op0, op1);
    }
    /// `VMOVDQU64_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovdqu64_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vmovdqu64MaskzEmitter<A, B>,
    {
        <Self as Vmovdqu64MaskzEmitter<A, B>>::vmovdqu64_maskz(self, op0, op1);
    }
    /// `VMOVHLPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovhlps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovhlpsEmitter<A, B, C>,
    {
        <Self as VmovhlpsEmitter<A, B, C>>::vmovhlps(self, op0, op1, op2);
    }
    /// `VMOVHPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovhpd_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovhpdEmitter_2<A, B>,
    {
        <Self as VmovhpdEmitter_2<A, B>>::vmovhpd_2(self, op0, op1);
    }
    /// `VMOVHPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovhpd_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovhpdEmitter_3<A, B, C>,
    {
        <Self as VmovhpdEmitter_3<A, B, C>>::vmovhpd_3(self, op0, op1, op2);
    }
    /// `VMOVHPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovhps_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovhpsEmitter_2<A, B>,
    {
        <Self as VmovhpsEmitter_2<A, B>>::vmovhps_2(self, op0, op1);
    }
    /// `VMOVHPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovhps_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovhpsEmitter_3<A, B, C>,
    {
        <Self as VmovhpsEmitter_3<A, B, C>>::vmovhps_3(self, op0, op1, op2);
    }
    /// `VMOVLHPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovlhps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovlhpsEmitter<A, B, C>,
    {
        <Self as VmovlhpsEmitter<A, B, C>>::vmovlhps(self, op0, op1, op2);
    }
    /// `VMOVLPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovlpd_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovlpdEmitter_2<A, B>,
    {
        <Self as VmovlpdEmitter_2<A, B>>::vmovlpd_2(self, op0, op1);
    }
    /// `VMOVLPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovlpd_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovlpdEmitter_3<A, B, C>,
    {
        <Self as VmovlpdEmitter_3<A, B, C>>::vmovlpd_3(self, op0, op1, op2);
    }
    /// `VMOVLPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovlps_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovlpsEmitter_2<A, B>,
    {
        <Self as VmovlpsEmitter_2<A, B>>::vmovlps_2(self, op0, op1);
    }
    /// `VMOVLPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovlps_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovlpsEmitter_3<A, B, C>,
    {
        <Self as VmovlpsEmitter_3<A, B, C>>::vmovlps_3(self, op0, op1, op2);
    }
    /// `VMOVNTDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovntdq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovntdqEmitter<A, B>,
    {
        <Self as VmovntdqEmitter<A, B>>::vmovntdq(self, op0, op1);
    }
    /// `VMOVNTDQA`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// | 3 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovntdqa<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovntdqaEmitter<A, B>,
    {
        <Self as VmovntdqaEmitter<A, B>>::vmovntdqa(self, op0, op1);
    }
    /// `VMOVNTPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovntpd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovntpdEmitter<A, B>,
    {
        <Self as VmovntpdEmitter<A, B>>::vmovntpd(self, op0, op1);
    }
    /// `VMOVNTPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovntps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovntpsEmitter<A, B>,
    {
        <Self as VmovntpsEmitter<A, B>>::vmovntps(self, op0, op1);
    }
    /// `VMOVQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Xmm, Mem |
    /// | 3 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovqEmitter<A, B>,
    {
        <Self as VmovqEmitter<A, B>>::vmovq(self, op0, op1);
    }
    /// `VMOVSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Xmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovsd_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovsdEmitter_2<A, B>,
    {
        <Self as VmovsdEmitter_2<A, B>>::vmovsd_2(self, op0, op1);
    }
    /// `VMOVSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovsd_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovsdEmitter_3<A, B, C>,
    {
        <Self as VmovsdEmitter_3<A, B, C>>::vmovsd_3(self, op0, op1, op2);
    }
    /// `VMOVSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Xmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovsd_mask_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovsdMaskEmitter_2<A, B>,
    {
        <Self as VmovsdMaskEmitter_2<A, B>>::vmovsd_mask_2(self, op0, op1);
    }
    /// `VMOVSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovsd_mask_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovsdMaskEmitter_3<A, B, C>,
    {
        <Self as VmovsdMaskEmitter_3<A, B, C>>::vmovsd_mask_3(self, op0, op1, op2);
    }
    /// `VMOVSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovsd_maskz_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovsdMaskzEmitter_2<A, B>,
    {
        <Self as VmovsdMaskzEmitter_2<A, B>>::vmovsd_maskz_2(self, op0, op1);
    }
    /// `VMOVSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovsd_maskz_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovsdMaskzEmitter_3<A, B, C>,
    {
        <Self as VmovsdMaskzEmitter_3<A, B, C>>::vmovsd_maskz_3(self, op0, op1, op2);
    }
    /// `VMOVSHDUP`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovshdup<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovshdupEmitter<A, B>,
    {
        <Self as VmovshdupEmitter<A, B>>::vmovshdup(self, op0, op1);
    }
    /// `VMOVSHDUP_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovshdup_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovshdupMaskEmitter<A, B>,
    {
        <Self as VmovshdupMaskEmitter<A, B>>::vmovshdup_mask(self, op0, op1);
    }
    /// `VMOVSHDUP_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovshdup_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovshdupMaskzEmitter<A, B>,
    {
        <Self as VmovshdupMaskzEmitter<A, B>>::vmovshdup_maskz(self, op0, op1);
    }
    /// `VMOVSLDUP`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovsldup<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovsldupEmitter<A, B>,
    {
        <Self as VmovsldupEmitter<A, B>>::vmovsldup(self, op0, op1);
    }
    /// `VMOVSLDUP_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovsldup_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovsldupMaskEmitter<A, B>,
    {
        <Self as VmovsldupMaskEmitter<A, B>>::vmovsldup_mask(self, op0, op1);
    }
    /// `VMOVSLDUP_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovsldup_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovsldupMaskzEmitter<A, B>,
    {
        <Self as VmovsldupMaskzEmitter<A, B>>::vmovsldup_maskz(self, op0, op1);
    }
    /// `VMOVSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Xmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovss_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovssEmitter_2<A, B>,
    {
        <Self as VmovssEmitter_2<A, B>>::vmovss_2(self, op0, op1);
    }
    /// `VMOVSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovss_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovssEmitter_3<A, B, C>,
    {
        <Self as VmovssEmitter_3<A, B, C>>::vmovss_3(self, op0, op1, op2);
    }
    /// `VMOVSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Xmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovss_mask_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovssMaskEmitter_2<A, B>,
    {
        <Self as VmovssMaskEmitter_2<A, B>>::vmovss_mask_2(self, op0, op1);
    }
    /// `VMOVSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovss_mask_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovssMaskEmitter_3<A, B, C>,
    {
        <Self as VmovssMaskEmitter_3<A, B, C>>::vmovss_mask_3(self, op0, op1, op2);
    }
    /// `VMOVSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovss_maskz_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovssMaskzEmitter_2<A, B>,
    {
        <Self as VmovssMaskzEmitter_2<A, B>>::vmovss_maskz_2(self, op0, op1);
    }
    /// `VMOVSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmovss_maskz_3<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmovssMaskzEmitter_3<A, B, C>,
    {
        <Self as VmovssMaskzEmitter_3<A, B, C>>::vmovss_maskz_3(self, op0, op1, op2);
    }
    /// `VMOVUPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovupd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovupdEmitter<A, B>,
    {
        <Self as VmovupdEmitter<A, B>>::vmovupd(self, op0, op1);
    }
    /// `VMOVUPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovupd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovupdMaskEmitter<A, B>,
    {
        <Self as VmovupdMaskEmitter<A, B>>::vmovupd_mask(self, op0, op1);
    }
    /// `VMOVUPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovupd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovupdMaskzEmitter<A, B>,
    {
        <Self as VmovupdMaskzEmitter<A, B>>::vmovupd_maskz(self, op0, op1);
    }
    /// `VMOVUPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovups<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovupsEmitter<A, B>,
    {
        <Self as VmovupsEmitter<A, B>>::vmovups(self, op0, op1);
    }
    /// `VMOVUPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Mem |
    /// | 5 | Xmm, Xmm |
    /// | 6 | Ymm, Mem |
    /// | 7 | Ymm, Ymm |
    /// | 8 | Zmm, Mem |
    /// | 9 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovups_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovupsMaskEmitter<A, B>,
    {
        <Self as VmovupsMaskEmitter<A, B>>::vmovups_mask(self, op0, op1);
    }
    /// `VMOVUPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vmovups_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VmovupsMaskzEmitter<A, B>,
    {
        <Self as VmovupsMaskzEmitter<A, B>>::vmovups_maskz(self, op0, op1);
    }
    /// `VMULPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpdEmitter<A, B, C>,
    {
        <Self as VmulpdEmitter<A, B, C>>::vmulpd(self, op0, op1, op2);
    }
    /// `VMULPD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulpd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpdErEmitter<A, B, C>,
    {
        <Self as VmulpdErEmitter<A, B, C>>::vmulpd_er(self, op0, op1, op2);
    }
    /// `VMULPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpdMaskEmitter<A, B, C>,
    {
        <Self as VmulpdMaskEmitter<A, B, C>>::vmulpd_mask(self, op0, op1, op2);
    }
    /// `VMULPD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulpd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpdMaskErEmitter<A, B, C>,
    {
        <Self as VmulpdMaskErEmitter<A, B, C>>::vmulpd_mask_er(self, op0, op1, op2);
    }
    /// `VMULPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpdMaskzEmitter<A, B, C>,
    {
        <Self as VmulpdMaskzEmitter<A, B, C>>::vmulpd_maskz(self, op0, op1, op2);
    }
    /// `VMULPD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulpd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpdMaskzErEmitter<A, B, C>,
    {
        <Self as VmulpdMaskzErEmitter<A, B, C>>::vmulpd_maskz_er(self, op0, op1, op2);
    }
    /// `VMULPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpsEmitter<A, B, C>,
    {
        <Self as VmulpsEmitter<A, B, C>>::vmulps(self, op0, op1, op2);
    }
    /// `VMULPS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpsErEmitter<A, B, C>,
    {
        <Self as VmulpsErEmitter<A, B, C>>::vmulps_er(self, op0, op1, op2);
    }
    /// `VMULPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpsMaskEmitter<A, B, C>,
    {
        <Self as VmulpsMaskEmitter<A, B, C>>::vmulps_mask(self, op0, op1, op2);
    }
    /// `VMULPS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpsMaskErEmitter<A, B, C>,
    {
        <Self as VmulpsMaskErEmitter<A, B, C>>::vmulps_mask_er(self, op0, op1, op2);
    }
    /// `VMULPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpsMaskzEmitter<A, B, C>,
    {
        <Self as VmulpsMaskzEmitter<A, B, C>>::vmulps_maskz(self, op0, op1, op2);
    }
    /// `VMULPS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulpsMaskzErEmitter<A, B, C>,
    {
        <Self as VmulpsMaskzErEmitter<A, B, C>>::vmulps_maskz_er(self, op0, op1, op2);
    }
    /// `VMULSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulsdEmitter<A, B, C>,
    {
        <Self as VmulsdEmitter<A, B, C>>::vmulsd(self, op0, op1, op2);
    }
    /// `VMULSD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulsd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulsdErEmitter<A, B, C>,
    {
        <Self as VmulsdErEmitter<A, B, C>>::vmulsd_er(self, op0, op1, op2);
    }
    /// `VMULSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulsdMaskEmitter<A, B, C>,
    {
        <Self as VmulsdMaskEmitter<A, B, C>>::vmulsd_mask(self, op0, op1, op2);
    }
    /// `VMULSD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulsd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulsdMaskErEmitter<A, B, C>,
    {
        <Self as VmulsdMaskErEmitter<A, B, C>>::vmulsd_mask_er(self, op0, op1, op2);
    }
    /// `VMULSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulsdMaskzEmitter<A, B, C>,
    {
        <Self as VmulsdMaskzEmitter<A, B, C>>::vmulsd_maskz(self, op0, op1, op2);
    }
    /// `VMULSD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulsd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulsdMaskzErEmitter<A, B, C>,
    {
        <Self as VmulsdMaskzErEmitter<A, B, C>>::vmulsd_maskz_er(self, op0, op1, op2);
    }
    /// `VMULSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulssEmitter<A, B, C>,
    {
        <Self as VmulssEmitter<A, B, C>>::vmulss(self, op0, op1, op2);
    }
    /// `VMULSS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulssErEmitter<A, B, C>,
    {
        <Self as VmulssErEmitter<A, B, C>>::vmulss_er(self, op0, op1, op2);
    }
    /// `VMULSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulssMaskEmitter<A, B, C>,
    {
        <Self as VmulssMaskEmitter<A, B, C>>::vmulss_mask(self, op0, op1, op2);
    }
    /// `VMULSS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulssMaskErEmitter<A, B, C>,
    {
        <Self as VmulssMaskErEmitter<A, B, C>>::vmulss_mask_er(self, op0, op1, op2);
    }
    /// `VMULSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulssMaskzEmitter<A, B, C>,
    {
        <Self as VmulssMaskzEmitter<A, B, C>>::vmulss_maskz(self, op0, op1, op2);
    }
    /// `VMULSS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vmulss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VmulssMaskzErEmitter<A, B, C>,
    {
        <Self as VmulssMaskzErEmitter<A, B, C>>::vmulss_maskz_er(self, op0, op1, op2);
    }
    /// `VPABSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpabsd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpabsdEmitter<A, B>,
    {
        <Self as VpabsdEmitter<A, B>>::vpabsd(self, op0, op1);
    }
    /// `VPABSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpabsd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpabsdMaskEmitter<A, B>,
    {
        <Self as VpabsdMaskEmitter<A, B>>::vpabsd_mask(self, op0, op1);
    }
    /// `VPABSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpabsd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpabsdMaskzEmitter<A, B>,
    {
        <Self as VpabsdMaskzEmitter<A, B>>::vpabsd_maskz(self, op0, op1);
    }
    /// `VPABSQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpabsq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpabsqEmitter<A, B>,
    {
        <Self as VpabsqEmitter<A, B>>::vpabsq(self, op0, op1);
    }
    /// `VPABSQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpabsq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpabsqMaskEmitter<A, B>,
    {
        <Self as VpabsqMaskEmitter<A, B>>::vpabsq_mask(self, op0, op1);
    }
    /// `VPABSQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpabsq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpabsqMaskzEmitter<A, B>,
    {
        <Self as VpabsqMaskzEmitter<A, B>>::vpabsq_maskz(self, op0, op1);
    }
    /// `VPADDD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpaddd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpadddEmitter<A, B, C>,
    {
        <Self as VpadddEmitter<A, B, C>>::vpaddd(self, op0, op1, op2);
    }
    /// `VPADDD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpaddd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpadddMaskEmitter<A, B, C>,
    {
        <Self as VpadddMaskEmitter<A, B, C>>::vpaddd_mask(self, op0, op1, op2);
    }
    /// `VPADDD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpaddd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpadddMaskzEmitter<A, B, C>,
    {
        <Self as VpadddMaskzEmitter<A, B, C>>::vpaddd_maskz(self, op0, op1, op2);
    }
    /// `VPADDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpaddq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpaddqEmitter<A, B, C>,
    {
        <Self as VpaddqEmitter<A, B, C>>::vpaddq(self, op0, op1, op2);
    }
    /// `VPADDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpaddq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpaddqMaskEmitter<A, B, C>,
    {
        <Self as VpaddqMaskEmitter<A, B, C>>::vpaddq_mask(self, op0, op1, op2);
    }
    /// `VPADDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpaddq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpaddqMaskzEmitter<A, B, C>,
    {
        <Self as VpaddqMaskzEmitter<A, B, C>>::vpaddq_maskz(self, op0, op1, op2);
    }
    /// `VPANDD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpanddEmitter<A, B, C>,
    {
        <Self as VpanddEmitter<A, B, C>>::vpandd(self, op0, op1, op2);
    }
    /// `VPANDD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpanddMaskEmitter<A, B, C>,
    {
        <Self as VpanddMaskEmitter<A, B, C>>::vpandd_mask(self, op0, op1, op2);
    }
    /// `VPANDD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpanddMaskzEmitter<A, B, C>,
    {
        <Self as VpanddMaskzEmitter<A, B, C>>::vpandd_maskz(self, op0, op1, op2);
    }
    /// `VPANDND`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandnd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandndEmitter<A, B, C>,
    {
        <Self as VpandndEmitter<A, B, C>>::vpandnd(self, op0, op1, op2);
    }
    /// `VPANDND_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandnd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandndMaskEmitter<A, B, C>,
    {
        <Self as VpandndMaskEmitter<A, B, C>>::vpandnd_mask(self, op0, op1, op2);
    }
    /// `VPANDND_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandnd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandndMaskzEmitter<A, B, C>,
    {
        <Self as VpandndMaskzEmitter<A, B, C>>::vpandnd_maskz(self, op0, op1, op2);
    }
    /// `VPANDNQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandnq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandnqEmitter<A, B, C>,
    {
        <Self as VpandnqEmitter<A, B, C>>::vpandnq(self, op0, op1, op2);
    }
    /// `VPANDNQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandnq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandnqMaskEmitter<A, B, C>,
    {
        <Self as VpandnqMaskEmitter<A, B, C>>::vpandnq_mask(self, op0, op1, op2);
    }
    /// `VPANDNQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandnq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandnqMaskzEmitter<A, B, C>,
    {
        <Self as VpandnqMaskzEmitter<A, B, C>>::vpandnq_maskz(self, op0, op1, op2);
    }
    /// `VPANDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandqEmitter<A, B, C>,
    {
        <Self as VpandqEmitter<A, B, C>>::vpandq(self, op0, op1, op2);
    }
    /// `VPANDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandqMaskEmitter<A, B, C>,
    {
        <Self as VpandqMaskEmitter<A, B, C>>::vpandq_mask(self, op0, op1, op2);
    }
    /// `VPANDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpandq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpandqMaskzEmitter<A, B, C>,
    {
        <Self as VpandqMaskzEmitter<A, B, C>>::vpandq_maskz(self, op0, op1, op2);
    }
    /// `VPBLENDMD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpblendmd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpblendmdEmitter<A, B, C>,
    {
        <Self as VpblendmdEmitter<A, B, C>>::vpblendmd(self, op0, op1, op2);
    }
    /// `VPBLENDMD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpblendmd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpblendmdMaskEmitter<A, B, C>,
    {
        <Self as VpblendmdMaskEmitter<A, B, C>>::vpblendmd_mask(self, op0, op1, op2);
    }
    /// `VPBLENDMD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpblendmd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpblendmdMaskzEmitter<A, B, C>,
    {
        <Self as VpblendmdMaskzEmitter<A, B, C>>::vpblendmd_maskz(self, op0, op1, op2);
    }
    /// `VPBLENDMQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpblendmq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpblendmqEmitter<A, B, C>,
    {
        <Self as VpblendmqEmitter<A, B, C>>::vpblendmq(self, op0, op1, op2);
    }
    /// `VPBLENDMQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpblendmq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpblendmqMaskEmitter<A, B, C>,
    {
        <Self as VpblendmqMaskEmitter<A, B, C>>::vpblendmq_mask(self, op0, op1, op2);
    }
    /// `VPBLENDMQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpblendmq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpblendmqMaskzEmitter<A, B, C>,
    {
        <Self as VpblendmqMaskzEmitter<A, B, C>>::vpblendmq_maskz(self, op0, op1, op2);
    }
    /// `VPBROADCASTD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastdEmitter<A, B>,
    {
        <Self as VpbroadcastdEmitter<A, B>>::vpbroadcastd(self, op0, op1);
    }
    /// `VPBROADCASTD_GP`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Gpd |
    /// | 2 | Ymm, Gpd |
    /// | 3 | Zmm, Gpd |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastd_gp<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastdGpEmitter<A, B>,
    {
        <Self as VpbroadcastdGpEmitter<A, B>>::vpbroadcastd_gp(self, op0, op1);
    }
    /// `VPBROADCASTD_GP_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Gpd |
    /// | 2 | Ymm, Gpd |
    /// | 3 | Zmm, Gpd |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastd_gp_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastdGpMaskEmitter<A, B>,
    {
        <Self as VpbroadcastdGpMaskEmitter<A, B>>::vpbroadcastd_gp_mask(self, op0, op1);
    }
    /// `VPBROADCASTD_GP_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Gpd |
    /// | 2 | Ymm, Gpd |
    /// | 3 | Zmm, Gpd |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastd_gp_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastdGpMaskzEmitter<A, B>,
    {
        <Self as VpbroadcastdGpMaskzEmitter<A, B>>::vpbroadcastd_gp_maskz(self, op0, op1);
    }
    /// `VPBROADCASTD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastdMaskEmitter<A, B>,
    {
        <Self as VpbroadcastdMaskEmitter<A, B>>::vpbroadcastd_mask(self, op0, op1);
    }
    /// `VPBROADCASTD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastdMaskzEmitter<A, B>,
    {
        <Self as VpbroadcastdMaskzEmitter<A, B>>::vpbroadcastd_maskz(self, op0, op1);
    }
    /// `VPBROADCASTQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastqEmitter<A, B>,
    {
        <Self as VpbroadcastqEmitter<A, B>>::vpbroadcastq(self, op0, op1);
    }
    /// `VPBROADCASTQ_GP`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Gpd |
    /// | 2 | Ymm, Gpd |
    /// | 3 | Zmm, Gpd |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastq_gp<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastqGpEmitter<A, B>,
    {
        <Self as VpbroadcastqGpEmitter<A, B>>::vpbroadcastq_gp(self, op0, op1);
    }
    /// `VPBROADCASTQ_GP_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Gpd |
    /// | 2 | Ymm, Gpd |
    /// | 3 | Zmm, Gpd |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastq_gp_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastqGpMaskEmitter<A, B>,
    {
        <Self as VpbroadcastqGpMaskEmitter<A, B>>::vpbroadcastq_gp_mask(self, op0, op1);
    }
    /// `VPBROADCASTQ_GP_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Gpd |
    /// | 2 | Ymm, Gpd |
    /// | 3 | Zmm, Gpd |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastq_gp_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastqGpMaskzEmitter<A, B>,
    {
        <Self as VpbroadcastqGpMaskzEmitter<A, B>>::vpbroadcastq_gp_maskz(self, op0, op1);
    }
    /// `VPBROADCASTQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastqMaskEmitter<A, B>,
    {
        <Self as VpbroadcastqMaskEmitter<A, B>>::vpbroadcastq_mask(self, op0, op1);
    }
    /// `VPBROADCASTQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpbroadcastq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpbroadcastqMaskzEmitter<A, B>,
    {
        <Self as VpbroadcastqMaskzEmitter<A, B>>::vpbroadcastq_maskz(self, op0, op1);
    }
    /// `VPCMPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vpcmpd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpcmpdEmitter<A, B, C, D>,
    {
        <Self as VpcmpdEmitter<A, B, C, D>>::vpcmpd(self, op0, op1, op2, op3);
    }
    /// `VPCMPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vpcmpd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpcmpdMaskEmitter<A, B, C, D>,
    {
        <Self as VpcmpdMaskEmitter<A, B, C, D>>::vpcmpd_mask(self, op0, op1, op2, op3);
    }
    /// `VPCMPEQB_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vpcmpeqb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpcmpeqbMaskEmitter<A, B, C>,
    {
        <Self as VpcmpeqbMaskEmitter<A, B, C>>::vpcmpeqb_mask(self, op0, op1, op2);
    }
    /// `VPCMPEQD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vpcmpeqd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpcmpeqdMaskEmitter<A, B, C>,
    {
        <Self as VpcmpeqdMaskEmitter<A, B, C>>::vpcmpeqd_mask(self, op0, op1, op2);
    }
    /// `VPCMPEQQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vpcmpeqq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpcmpeqqMaskEmitter<A, B, C>,
    {
        <Self as VpcmpeqqMaskEmitter<A, B, C>>::vpcmpeqq_mask(self, op0, op1, op2);
    }
    /// `VPCMPEQW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vpcmpeqw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpcmpeqwMaskEmitter<A, B, C>,
    {
        <Self as VpcmpeqwMaskEmitter<A, B, C>>::vpcmpeqw_mask(self, op0, op1, op2);
    }
    /// `VPCMPGTB_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vpcmpgtb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpcmpgtbMaskEmitter<A, B, C>,
    {
        <Self as VpcmpgtbMaskEmitter<A, B, C>>::vpcmpgtb_mask(self, op0, op1, op2);
    }
    /// `VPCMPGTD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vpcmpgtd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpcmpgtdMaskEmitter<A, B, C>,
    {
        <Self as VpcmpgtdMaskEmitter<A, B, C>>::vpcmpgtd_mask(self, op0, op1, op2);
    }
    /// `VPCMPGTQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vpcmpgtq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpcmpgtqMaskEmitter<A, B, C>,
    {
        <Self as VpcmpgtqMaskEmitter<A, B, C>>::vpcmpgtq_mask(self, op0, op1, op2);
    }
    /// `VPCMPGTW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vpcmpgtw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpcmpgtwMaskEmitter<A, B, C>,
    {
        <Self as VpcmpgtwMaskEmitter<A, B, C>>::vpcmpgtw_mask(self, op0, op1, op2);
    }
    /// `VPCMPQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vpcmpq<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpcmpqEmitter<A, B, C, D>,
    {
        <Self as VpcmpqEmitter<A, B, C, D>>::vpcmpq(self, op0, op1, op2, op3);
    }
    /// `VPCMPQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vpcmpq_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpcmpqMaskEmitter<A, B, C, D>,
    {
        <Self as VpcmpqMaskEmitter<A, B, C, D>>::vpcmpq_mask(self, op0, op1, op2, op3);
    }
    /// `VPCMPUD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vpcmpud<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpcmpudEmitter<A, B, C, D>,
    {
        <Self as VpcmpudEmitter<A, B, C, D>>::vpcmpud(self, op0, op1, op2, op3);
    }
    /// `VPCMPUD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vpcmpud_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpcmpudMaskEmitter<A, B, C, D>,
    {
        <Self as VpcmpudMaskEmitter<A, B, C, D>>::vpcmpud_mask(self, op0, op1, op2, op3);
    }
    /// `VPCMPUQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vpcmpuq<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpcmpuqEmitter<A, B, C, D>,
    {
        <Self as VpcmpuqEmitter<A, B, C, D>>::vpcmpuq(self, op0, op1, op2, op3);
    }
    /// `VPCMPUQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------------+
    /// | # | Operands            |
    /// +---+---------------------+
    /// | 1 | KReg, Xmm, Mem, Imm |
    /// | 2 | KReg, Xmm, Xmm, Imm |
    /// | 3 | KReg, Ymm, Mem, Imm |
    /// | 4 | KReg, Ymm, Ymm, Imm |
    /// | 5 | KReg, Zmm, Mem, Imm |
    /// | 6 | KReg, Zmm, Zmm, Imm |
    /// +---+---------------------+
    /// ```
    #[inline]
    pub fn vpcmpuq_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpcmpuqMaskEmitter<A, B, C, D>,
    {
        <Self as VpcmpuqMaskEmitter<A, B, C, D>>::vpcmpuq_mask(self, op0, op1, op2, op3);
    }
    /// `VPCOMPRESSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Ymm, Ymm |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpcompressd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpcompressdEmitter<A, B>,
    {
        <Self as VpcompressdEmitter<A, B>>::vpcompressd(self, op0, op1);
    }
    /// `VPCOMPRESSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Ymm, Ymm |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpcompressd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpcompressdMaskEmitter<A, B>,
    {
        <Self as VpcompressdMaskEmitter<A, B>>::vpcompressd_mask(self, op0, op1);
    }
    /// `VPCOMPRESSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Ymm, Ymm |
    /// | 3 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpcompressd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpcompressdMaskzEmitter<A, B>,
    {
        <Self as VpcompressdMaskzEmitter<A, B>>::vpcompressd_maskz(self, op0, op1);
    }
    /// `VPCOMPRESSQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Ymm, Ymm |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpcompressq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpcompressqEmitter<A, B>,
    {
        <Self as VpcompressqEmitter<A, B>>::vpcompressq(self, op0, op1);
    }
    /// `VPCOMPRESSQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Ymm, Ymm |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpcompressq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpcompressqMaskEmitter<A, B>,
    {
        <Self as VpcompressqMaskEmitter<A, B>>::vpcompressq_mask(self, op0, op1);
    }
    /// `VPCOMPRESSQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Ymm, Ymm |
    /// | 3 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpcompressq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpcompressqMaskzEmitter<A, B>,
    {
        <Self as VpcompressqMaskzEmitter<A, B>>::vpcompressq_maskz(self, op0, op1);
    }
    /// `VPERMD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Ymm, Mem |
    /// | 2 | Ymm, Ymm, Ymm |
    /// | 3 | Zmm, Zmm, Mem |
    /// | 4 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermdEmitter<A, B, C>,
    {
        <Self as VpermdEmitter<A, B, C>>::vpermd(self, op0, op1, op2);
    }
    /// `VPERMD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Ymm, Mem |
    /// | 2 | Ymm, Ymm, Ymm |
    /// | 3 | Zmm, Zmm, Mem |
    /// | 4 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermdMaskEmitter<A, B, C>,
    {
        <Self as VpermdMaskEmitter<A, B, C>>::vpermd_mask(self, op0, op1, op2);
    }
    /// `VPERMD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Ymm, Mem |
    /// | 2 | Ymm, Ymm, Ymm |
    /// | 3 | Zmm, Zmm, Mem |
    /// | 4 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermdMaskzEmitter<A, B, C>,
    {
        <Self as VpermdMaskzEmitter<A, B, C>>::vpermd_maskz(self, op0, op1, op2);
    }
    /// `VPERMI2D`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2d<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2dEmitter<A, B, C>,
    {
        <Self as Vpermi2dEmitter<A, B, C>>::vpermi2d(self, op0, op1, op2);
    }
    /// `VPERMI2D_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2d_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2dMaskEmitter<A, B, C>,
    {
        <Self as Vpermi2dMaskEmitter<A, B, C>>::vpermi2d_mask(self, op0, op1, op2);
    }
    /// `VPERMI2D_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2d_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2dMaskzEmitter<A, B, C>,
    {
        <Self as Vpermi2dMaskzEmitter<A, B, C>>::vpermi2d_maskz(self, op0, op1, op2);
    }
    /// `VPERMI2PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2pdEmitter<A, B, C>,
    {
        <Self as Vpermi2pdEmitter<A, B, C>>::vpermi2pd(self, op0, op1, op2);
    }
    /// `VPERMI2PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2pdMaskEmitter<A, B, C>,
    {
        <Self as Vpermi2pdMaskEmitter<A, B, C>>::vpermi2pd_mask(self, op0, op1, op2);
    }
    /// `VPERMI2PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2pdMaskzEmitter<A, B, C>,
    {
        <Self as Vpermi2pdMaskzEmitter<A, B, C>>::vpermi2pd_maskz(self, op0, op1, op2);
    }
    /// `VPERMI2PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2psEmitter<A, B, C>,
    {
        <Self as Vpermi2psEmitter<A, B, C>>::vpermi2ps(self, op0, op1, op2);
    }
    /// `VPERMI2PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2psMaskEmitter<A, B, C>,
    {
        <Self as Vpermi2psMaskEmitter<A, B, C>>::vpermi2ps_mask(self, op0, op1, op2);
    }
    /// `VPERMI2PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2psMaskzEmitter<A, B, C>,
    {
        <Self as Vpermi2psMaskzEmitter<A, B, C>>::vpermi2ps_maskz(self, op0, op1, op2);
    }
    /// `VPERMI2Q`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2q<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2qEmitter<A, B, C>,
    {
        <Self as Vpermi2qEmitter<A, B, C>>::vpermi2q(self, op0, op1, op2);
    }
    /// `VPERMI2Q_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2q_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2qMaskEmitter<A, B, C>,
    {
        <Self as Vpermi2qMaskEmitter<A, B, C>>::vpermi2q_mask(self, op0, op1, op2);
    }
    /// `VPERMI2Q_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermi2q_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermi2qMaskzEmitter<A, B, C>,
    {
        <Self as Vpermi2qMaskzEmitter<A, B, C>>::vpermi2q_maskz(self, op0, op1, op2);
    }
    /// `VPERMILPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Ymm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Zmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpermilpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermilpdEmitter<A, B, C>,
    {
        <Self as VpermilpdEmitter<A, B, C>>::vpermilpd(self, op0, op1, op2);
    }
    /// `VPERMILPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Ymm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Zmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpermilpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermilpdMaskEmitter<A, B, C>,
    {
        <Self as VpermilpdMaskEmitter<A, B, C>>::vpermilpd_mask(self, op0, op1, op2);
    }
    /// `VPERMILPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Ymm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Zmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpermilpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermilpdMaskzEmitter<A, B, C>,
    {
        <Self as VpermilpdMaskzEmitter<A, B, C>>::vpermilpd_maskz(self, op0, op1, op2);
    }
    /// `VPERMILPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Ymm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Zmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpermilps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermilpsEmitter<A, B, C>,
    {
        <Self as VpermilpsEmitter<A, B, C>>::vpermilps(self, op0, op1, op2);
    }
    /// `VPERMILPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Ymm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Zmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpermilps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermilpsMaskEmitter<A, B, C>,
    {
        <Self as VpermilpsMaskEmitter<A, B, C>>::vpermilps_mask(self, op0, op1, op2);
    }
    /// `VPERMILPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Ymm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Zmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpermilps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermilpsMaskzEmitter<A, B, C>,
    {
        <Self as VpermilpsMaskzEmitter<A, B, C>>::vpermilps_maskz(self, op0, op1, op2);
    }
    /// `VPERMPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Imm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// | 7 | Zmm, Zmm, Mem |
    /// | 8 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermpdEmitter<A, B, C>,
    {
        <Self as VpermpdEmitter<A, B, C>>::vpermpd(self, op0, op1, op2);
    }
    /// `VPERMPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Imm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// | 7 | Zmm, Zmm, Mem |
    /// | 8 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermpdMaskEmitter<A, B, C>,
    {
        <Self as VpermpdMaskEmitter<A, B, C>>::vpermpd_mask(self, op0, op1, op2);
    }
    /// `VPERMPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Imm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// | 7 | Zmm, Zmm, Mem |
    /// | 8 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermpdMaskzEmitter<A, B, C>,
    {
        <Self as VpermpdMaskzEmitter<A, B, C>>::vpermpd_maskz(self, op0, op1, op2);
    }
    /// `VPERMPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Ymm, Mem |
    /// | 2 | Ymm, Ymm, Ymm |
    /// | 3 | Zmm, Zmm, Mem |
    /// | 4 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermpsEmitter<A, B, C>,
    {
        <Self as VpermpsEmitter<A, B, C>>::vpermps(self, op0, op1, op2);
    }
    /// `VPERMPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Ymm, Mem |
    /// | 2 | Ymm, Ymm, Ymm |
    /// | 3 | Zmm, Zmm, Mem |
    /// | 4 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermpsMaskEmitter<A, B, C>,
    {
        <Self as VpermpsMaskEmitter<A, B, C>>::vpermps_mask(self, op0, op1, op2);
    }
    /// `VPERMPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Ymm, Mem |
    /// | 2 | Ymm, Ymm, Ymm |
    /// | 3 | Zmm, Zmm, Mem |
    /// | 4 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermpsMaskzEmitter<A, B, C>,
    {
        <Self as VpermpsMaskzEmitter<A, B, C>>::vpermps_maskz(self, op0, op1, op2);
    }
    /// `VPERMQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Imm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// | 7 | Zmm, Zmm, Mem |
    /// | 8 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermqEmitter<A, B, C>,
    {
        <Self as VpermqEmitter<A, B, C>>::vpermq(self, op0, op1, op2);
    }
    /// `VPERMQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Imm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// | 7 | Zmm, Zmm, Mem |
    /// | 8 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermqMaskEmitter<A, B, C>,
    {
        <Self as VpermqMaskEmitter<A, B, C>>::vpermq_mask(self, op0, op1, op2);
    }
    /// `VPERMQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Imm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// | 7 | Zmm, Zmm, Mem |
    /// | 8 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpermqMaskzEmitter<A, B, C>,
    {
        <Self as VpermqMaskzEmitter<A, B, C>>::vpermq_maskz(self, op0, op1, op2);
    }
    /// `VPERMT2D`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2d<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2dEmitter<A, B, C>,
    {
        <Self as Vpermt2dEmitter<A, B, C>>::vpermt2d(self, op0, op1, op2);
    }
    /// `VPERMT2D_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2d_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2dMaskEmitter<A, B, C>,
    {
        <Self as Vpermt2dMaskEmitter<A, B, C>>::vpermt2d_mask(self, op0, op1, op2);
    }
    /// `VPERMT2D_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2d_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2dMaskzEmitter<A, B, C>,
    {
        <Self as Vpermt2dMaskzEmitter<A, B, C>>::vpermt2d_maskz(self, op0, op1, op2);
    }
    /// `VPERMT2PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2pd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2pdEmitter<A, B, C>,
    {
        <Self as Vpermt2pdEmitter<A, B, C>>::vpermt2pd(self, op0, op1, op2);
    }
    /// `VPERMT2PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2pd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2pdMaskEmitter<A, B, C>,
    {
        <Self as Vpermt2pdMaskEmitter<A, B, C>>::vpermt2pd_mask(self, op0, op1, op2);
    }
    /// `VPERMT2PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2pd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2pdMaskzEmitter<A, B, C>,
    {
        <Self as Vpermt2pdMaskzEmitter<A, B, C>>::vpermt2pd_maskz(self, op0, op1, op2);
    }
    /// `VPERMT2PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2psEmitter<A, B, C>,
    {
        <Self as Vpermt2psEmitter<A, B, C>>::vpermt2ps(self, op0, op1, op2);
    }
    /// `VPERMT2PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2psMaskEmitter<A, B, C>,
    {
        <Self as Vpermt2psMaskEmitter<A, B, C>>::vpermt2ps_mask(self, op0, op1, op2);
    }
    /// `VPERMT2PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2psMaskzEmitter<A, B, C>,
    {
        <Self as Vpermt2psMaskzEmitter<A, B, C>>::vpermt2ps_maskz(self, op0, op1, op2);
    }
    /// `VPERMT2Q`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2q<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2qEmitter<A, B, C>,
    {
        <Self as Vpermt2qEmitter<A, B, C>>::vpermt2q(self, op0, op1, op2);
    }
    /// `VPERMT2Q_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2q_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2qMaskEmitter<A, B, C>,
    {
        <Self as Vpermt2qMaskEmitter<A, B, C>>::vpermt2q_mask(self, op0, op1, op2);
    }
    /// `VPERMT2Q_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpermt2q_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vpermt2qMaskzEmitter<A, B, C>,
    {
        <Self as Vpermt2qMaskzEmitter<A, B, C>>::vpermt2q_maskz(self, op0, op1, op2);
    }
    /// `VPEXPANDD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpexpandd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpexpanddEmitter<A, B>,
    {
        <Self as VpexpanddEmitter<A, B>>::vpexpandd(self, op0, op1);
    }
    /// `VPEXPANDD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpexpandd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpexpanddMaskEmitter<A, B>,
    {
        <Self as VpexpanddMaskEmitter<A, B>>::vpexpandd_mask(self, op0, op1);
    }
    /// `VPEXPANDD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpexpandd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpexpanddMaskzEmitter<A, B>,
    {
        <Self as VpexpanddMaskzEmitter<A, B>>::vpexpandd_maskz(self, op0, op1);
    }
    /// `VPEXPANDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpexpandq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpexpandqEmitter<A, B>,
    {
        <Self as VpexpandqEmitter<A, B>>::vpexpandq(self, op0, op1);
    }
    /// `VPEXPANDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpexpandq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpexpandqMaskEmitter<A, B>,
    {
        <Self as VpexpandqMaskEmitter<A, B>>::vpexpandq_mask(self, op0, op1);
    }
    /// `VPEXPANDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpexpandq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpexpandqMaskzEmitter<A, B>,
    {
        <Self as VpexpandqMaskzEmitter<A, B>>::vpexpandq_maskz(self, op0, op1);
    }
    /// `VPGATHERDD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// | 3 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpgatherdd_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpgatherddEmitter_2<A, B>,
    {
        <Self as VpgatherddEmitter_2<A, B>>::vpgatherdd_2(self, op0, op1);
    }
    /// `VPGATHERDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// | 3 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpgatherdq_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpgatherdqEmitter_2<A, B>,
    {
        <Self as VpgatherdqEmitter_2<A, B>>::vpgatherdq_2(self, op0, op1);
    }
    /// `VPGATHERQD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpgatherqd_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpgatherqdEmitter_2<A, B>,
    {
        <Self as VpgatherqdEmitter_2<A, B>>::vpgatherqd_2(self, op0, op1);
    }
    /// `VPGATHERQQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Ymm, Mem |
    /// | 3 | Zmm, Mem |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpgatherqq_2<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpgatherqqEmitter_2<A, B>,
    {
        <Self as VpgatherqqEmitter_2<A, B>>::vpgatherqq_2(self, op0, op1);
    }
    /// `VPMAXSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxsdEmitter<A, B, C>,
    {
        <Self as VpmaxsdEmitter<A, B, C>>::vpmaxsd(self, op0, op1, op2);
    }
    /// `VPMAXSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxsdMaskEmitter<A, B, C>,
    {
        <Self as VpmaxsdMaskEmitter<A, B, C>>::vpmaxsd_mask(self, op0, op1, op2);
    }
    /// `VPMAXSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxsdMaskzEmitter<A, B, C>,
    {
        <Self as VpmaxsdMaskzEmitter<A, B, C>>::vpmaxsd_maskz(self, op0, op1, op2);
    }
    /// `VPMAXSQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxsq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxsqEmitter<A, B, C>,
    {
        <Self as VpmaxsqEmitter<A, B, C>>::vpmaxsq(self, op0, op1, op2);
    }
    /// `VPMAXSQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxsq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxsqMaskEmitter<A, B, C>,
    {
        <Self as VpmaxsqMaskEmitter<A, B, C>>::vpmaxsq_mask(self, op0, op1, op2);
    }
    /// `VPMAXSQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxsq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxsqMaskzEmitter<A, B, C>,
    {
        <Self as VpmaxsqMaskzEmitter<A, B, C>>::vpmaxsq_maskz(self, op0, op1, op2);
    }
    /// `VPMAXUD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxud<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxudEmitter<A, B, C>,
    {
        <Self as VpmaxudEmitter<A, B, C>>::vpmaxud(self, op0, op1, op2);
    }
    /// `VPMAXUD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxud_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxudMaskEmitter<A, B, C>,
    {
        <Self as VpmaxudMaskEmitter<A, B, C>>::vpmaxud_mask(self, op0, op1, op2);
    }
    /// `VPMAXUD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxud_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxudMaskzEmitter<A, B, C>,
    {
        <Self as VpmaxudMaskzEmitter<A, B, C>>::vpmaxud_maskz(self, op0, op1, op2);
    }
    /// `VPMAXUQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxuq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxuqEmitter<A, B, C>,
    {
        <Self as VpmaxuqEmitter<A, B, C>>::vpmaxuq(self, op0, op1, op2);
    }
    /// `VPMAXUQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxuq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxuqMaskEmitter<A, B, C>,
    {
        <Self as VpmaxuqMaskEmitter<A, B, C>>::vpmaxuq_mask(self, op0, op1, op2);
    }
    /// `VPMAXUQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmaxuq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmaxuqMaskzEmitter<A, B, C>,
    {
        <Self as VpmaxuqMaskzEmitter<A, B, C>>::vpmaxuq_maskz(self, op0, op1, op2);
    }
    /// `VPMINSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminsdEmitter<A, B, C>,
    {
        <Self as VpminsdEmitter<A, B, C>>::vpminsd(self, op0, op1, op2);
    }
    /// `VPMINSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminsdMaskEmitter<A, B, C>,
    {
        <Self as VpminsdMaskEmitter<A, B, C>>::vpminsd_mask(self, op0, op1, op2);
    }
    /// `VPMINSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminsdMaskzEmitter<A, B, C>,
    {
        <Self as VpminsdMaskzEmitter<A, B, C>>::vpminsd_maskz(self, op0, op1, op2);
    }
    /// `VPMINSQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminsq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminsqEmitter<A, B, C>,
    {
        <Self as VpminsqEmitter<A, B, C>>::vpminsq(self, op0, op1, op2);
    }
    /// `VPMINSQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminsq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminsqMaskEmitter<A, B, C>,
    {
        <Self as VpminsqMaskEmitter<A, B, C>>::vpminsq_mask(self, op0, op1, op2);
    }
    /// `VPMINSQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminsq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminsqMaskzEmitter<A, B, C>,
    {
        <Self as VpminsqMaskzEmitter<A, B, C>>::vpminsq_maskz(self, op0, op1, op2);
    }
    /// `VPMINUD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminud<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminudEmitter<A, B, C>,
    {
        <Self as VpminudEmitter<A, B, C>>::vpminud(self, op0, op1, op2);
    }
    /// `VPMINUD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminud_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminudMaskEmitter<A, B, C>,
    {
        <Self as VpminudMaskEmitter<A, B, C>>::vpminud_mask(self, op0, op1, op2);
    }
    /// `VPMINUD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminud_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminudMaskzEmitter<A, B, C>,
    {
        <Self as VpminudMaskzEmitter<A, B, C>>::vpminud_maskz(self, op0, op1, op2);
    }
    /// `VPMINUQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminuq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminuqEmitter<A, B, C>,
    {
        <Self as VpminuqEmitter<A, B, C>>::vpminuq(self, op0, op1, op2);
    }
    /// `VPMINUQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminuq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminuqMaskEmitter<A, B, C>,
    {
        <Self as VpminuqMaskEmitter<A, B, C>>::vpminuq_mask(self, op0, op1, op2);
    }
    /// `VPMINUQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpminuq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpminuqMaskzEmitter<A, B, C>,
    {
        <Self as VpminuqMaskzEmitter<A, B, C>>::vpminuq_maskz(self, op0, op1, op2);
    }
    /// `VPMOVDB`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovdb<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovdbEmitter<A, B>,
    {
        <Self as VpmovdbEmitter<A, B>>::vpmovdb(self, op0, op1);
    }
    /// `VPMOVDB_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovdb_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovdbMaskEmitter<A, B>,
    {
        <Self as VpmovdbMaskEmitter<A, B>>::vpmovdb_mask(self, op0, op1);
    }
    /// `VPMOVDB_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovdb_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovdbMaskzEmitter<A, B>,
    {
        <Self as VpmovdbMaskzEmitter<A, B>>::vpmovdb_maskz(self, op0, op1);
    }
    /// `VPMOVDW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovdw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovdwEmitter<A, B>,
    {
        <Self as VpmovdwEmitter<A, B>>::vpmovdw(self, op0, op1);
    }
    /// `VPMOVDW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovdw_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovdwMaskEmitter<A, B>,
    {
        <Self as VpmovdwMaskEmitter<A, B>>::vpmovdw_mask(self, op0, op1);
    }
    /// `VPMOVDW_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovdw_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovdwMaskzEmitter<A, B>,
    {
        <Self as VpmovdwMaskzEmitter<A, B>>::vpmovdw_maskz(self, op0, op1);
    }
    /// `VPMOVQB`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqb<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqbEmitter<A, B>,
    {
        <Self as VpmovqbEmitter<A, B>>::vpmovqb(self, op0, op1);
    }
    /// `VPMOVQB_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqb_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqbMaskEmitter<A, B>,
    {
        <Self as VpmovqbMaskEmitter<A, B>>::vpmovqb_mask(self, op0, op1);
    }
    /// `VPMOVQB_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqb_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqbMaskzEmitter<A, B>,
    {
        <Self as VpmovqbMaskzEmitter<A, B>>::vpmovqb_maskz(self, op0, op1);
    }
    /// `VPMOVQD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqdEmitter<A, B>,
    {
        <Self as VpmovqdEmitter<A, B>>::vpmovqd(self, op0, op1);
    }
    /// `VPMOVQD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqdMaskEmitter<A, B>,
    {
        <Self as VpmovqdMaskEmitter<A, B>>::vpmovqd_mask(self, op0, op1);
    }
    /// `VPMOVQD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqdMaskzEmitter<A, B>,
    {
        <Self as VpmovqdMaskzEmitter<A, B>>::vpmovqd_maskz(self, op0, op1);
    }
    /// `VPMOVQW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqwEmitter<A, B>,
    {
        <Self as VpmovqwEmitter<A, B>>::vpmovqw(self, op0, op1);
    }
    /// `VPMOVQW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqw_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqwMaskEmitter<A, B>,
    {
        <Self as VpmovqwMaskEmitter<A, B>>::vpmovqw_mask(self, op0, op1);
    }
    /// `VPMOVQW_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovqw_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovqwMaskzEmitter<A, B>,
    {
        <Self as VpmovqwMaskzEmitter<A, B>>::vpmovqw_maskz(self, op0, op1);
    }
    /// `VPMOVSDB`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsdb<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsdbEmitter<A, B>,
    {
        <Self as VpmovsdbEmitter<A, B>>::vpmovsdb(self, op0, op1);
    }
    /// `VPMOVSDB_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsdb_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsdbMaskEmitter<A, B>,
    {
        <Self as VpmovsdbMaskEmitter<A, B>>::vpmovsdb_mask(self, op0, op1);
    }
    /// `VPMOVSDB_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsdb_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsdbMaskzEmitter<A, B>,
    {
        <Self as VpmovsdbMaskzEmitter<A, B>>::vpmovsdb_maskz(self, op0, op1);
    }
    /// `VPMOVSDW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsdw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsdwEmitter<A, B>,
    {
        <Self as VpmovsdwEmitter<A, B>>::vpmovsdw(self, op0, op1);
    }
    /// `VPMOVSDW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsdw_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsdwMaskEmitter<A, B>,
    {
        <Self as VpmovsdwMaskEmitter<A, B>>::vpmovsdw_mask(self, op0, op1);
    }
    /// `VPMOVSDW_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsdw_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsdwMaskzEmitter<A, B>,
    {
        <Self as VpmovsdwMaskzEmitter<A, B>>::vpmovsdw_maskz(self, op0, op1);
    }
    /// `VPMOVSQB`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqb<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqbEmitter<A, B>,
    {
        <Self as VpmovsqbEmitter<A, B>>::vpmovsqb(self, op0, op1);
    }
    /// `VPMOVSQB_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqb_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqbMaskEmitter<A, B>,
    {
        <Self as VpmovsqbMaskEmitter<A, B>>::vpmovsqb_mask(self, op0, op1);
    }
    /// `VPMOVSQB_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqb_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqbMaskzEmitter<A, B>,
    {
        <Self as VpmovsqbMaskzEmitter<A, B>>::vpmovsqb_maskz(self, op0, op1);
    }
    /// `VPMOVSQD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqdEmitter<A, B>,
    {
        <Self as VpmovsqdEmitter<A, B>>::vpmovsqd(self, op0, op1);
    }
    /// `VPMOVSQD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqdMaskEmitter<A, B>,
    {
        <Self as VpmovsqdMaskEmitter<A, B>>::vpmovsqd_mask(self, op0, op1);
    }
    /// `VPMOVSQD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqdMaskzEmitter<A, B>,
    {
        <Self as VpmovsqdMaskzEmitter<A, B>>::vpmovsqd_maskz(self, op0, op1);
    }
    /// `VPMOVSQW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqwEmitter<A, B>,
    {
        <Self as VpmovsqwEmitter<A, B>>::vpmovsqw(self, op0, op1);
    }
    /// `VPMOVSQW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqw_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqwMaskEmitter<A, B>,
    {
        <Self as VpmovsqwMaskEmitter<A, B>>::vpmovsqw_mask(self, op0, op1);
    }
    /// `VPMOVSQW_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsqw_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsqwMaskzEmitter<A, B>,
    {
        <Self as VpmovsqwMaskzEmitter<A, B>>::vpmovsqw_maskz(self, op0, op1);
    }
    /// `VPMOVSXBD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbdEmitter<A, B>,
    {
        <Self as VpmovsxbdEmitter<A, B>>::vpmovsxbd(self, op0, op1);
    }
    /// `VPMOVSXBD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbdMaskEmitter<A, B>,
    {
        <Self as VpmovsxbdMaskEmitter<A, B>>::vpmovsxbd_mask(self, op0, op1);
    }
    /// `VPMOVSXBD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbdMaskzEmitter<A, B>,
    {
        <Self as VpmovsxbdMaskzEmitter<A, B>>::vpmovsxbd_maskz(self, op0, op1);
    }
    /// `VPMOVSXBQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbqEmitter<A, B>,
    {
        <Self as VpmovsxbqEmitter<A, B>>::vpmovsxbq(self, op0, op1);
    }
    /// `VPMOVSXBQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbqMaskEmitter<A, B>,
    {
        <Self as VpmovsxbqMaskEmitter<A, B>>::vpmovsxbq_mask(self, op0, op1);
    }
    /// `VPMOVSXBQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbqMaskzEmitter<A, B>,
    {
        <Self as VpmovsxbqMaskzEmitter<A, B>>::vpmovsxbq_maskz(self, op0, op1);
    }
    /// `VPMOVSXBW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbwEmitter<A, B>,
    {
        <Self as VpmovsxbwEmitter<A, B>>::vpmovsxbw(self, op0, op1);
    }
    /// `VPMOVSXBW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbw_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbwMaskEmitter<A, B>,
    {
        <Self as VpmovsxbwMaskEmitter<A, B>>::vpmovsxbw_mask(self, op0, op1);
    }
    /// `VPMOVSXBW_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxbw_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxbwMaskzEmitter<A, B>,
    {
        <Self as VpmovsxbwMaskzEmitter<A, B>>::vpmovsxbw_maskz(self, op0, op1);
    }
    /// `VPMOVSXDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxdq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxdqEmitter<A, B>,
    {
        <Self as VpmovsxdqEmitter<A, B>>::vpmovsxdq(self, op0, op1);
    }
    /// `VPMOVSXDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxdq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxdqMaskEmitter<A, B>,
    {
        <Self as VpmovsxdqMaskEmitter<A, B>>::vpmovsxdq_mask(self, op0, op1);
    }
    /// `VPMOVSXDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxdq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxdqMaskzEmitter<A, B>,
    {
        <Self as VpmovsxdqMaskzEmitter<A, B>>::vpmovsxdq_maskz(self, op0, op1);
    }
    /// `VPMOVSXWD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxwd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxwdEmitter<A, B>,
    {
        <Self as VpmovsxwdEmitter<A, B>>::vpmovsxwd(self, op0, op1);
    }
    /// `VPMOVSXWD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxwd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxwdMaskEmitter<A, B>,
    {
        <Self as VpmovsxwdMaskEmitter<A, B>>::vpmovsxwd_mask(self, op0, op1);
    }
    /// `VPMOVSXWD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxwd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxwdMaskzEmitter<A, B>,
    {
        <Self as VpmovsxwdMaskzEmitter<A, B>>::vpmovsxwd_maskz(self, op0, op1);
    }
    /// `VPMOVSXWQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxwq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxwqEmitter<A, B>,
    {
        <Self as VpmovsxwqEmitter<A, B>>::vpmovsxwq(self, op0, op1);
    }
    /// `VPMOVSXWQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxwq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxwqMaskEmitter<A, B>,
    {
        <Self as VpmovsxwqMaskEmitter<A, B>>::vpmovsxwq_mask(self, op0, op1);
    }
    /// `VPMOVSXWQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovsxwq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovsxwqMaskzEmitter<A, B>,
    {
        <Self as VpmovsxwqMaskzEmitter<A, B>>::vpmovsxwq_maskz(self, op0, op1);
    }
    /// `VPMOVUSDB`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusdb<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusdbEmitter<A, B>,
    {
        <Self as VpmovusdbEmitter<A, B>>::vpmovusdb(self, op0, op1);
    }
    /// `VPMOVUSDB_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusdb_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusdbMaskEmitter<A, B>,
    {
        <Self as VpmovusdbMaskEmitter<A, B>>::vpmovusdb_mask(self, op0, op1);
    }
    /// `VPMOVUSDB_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusdb_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusdbMaskzEmitter<A, B>,
    {
        <Self as VpmovusdbMaskzEmitter<A, B>>::vpmovusdb_maskz(self, op0, op1);
    }
    /// `VPMOVUSDW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusdw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusdwEmitter<A, B>,
    {
        <Self as VpmovusdwEmitter<A, B>>::vpmovusdw(self, op0, op1);
    }
    /// `VPMOVUSDW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusdw_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusdwMaskEmitter<A, B>,
    {
        <Self as VpmovusdwMaskEmitter<A, B>>::vpmovusdw_mask(self, op0, op1);
    }
    /// `VPMOVUSDW_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusdw_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusdwMaskzEmitter<A, B>,
    {
        <Self as VpmovusdwMaskzEmitter<A, B>>::vpmovusdw_maskz(self, op0, op1);
    }
    /// `VPMOVUSQB`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqb<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqbEmitter<A, B>,
    {
        <Self as VpmovusqbEmitter<A, B>>::vpmovusqb(self, op0, op1);
    }
    /// `VPMOVUSQB_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqb_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqbMaskEmitter<A, B>,
    {
        <Self as VpmovusqbMaskEmitter<A, B>>::vpmovusqb_mask(self, op0, op1);
    }
    /// `VPMOVUSQB_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqb_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqbMaskzEmitter<A, B>,
    {
        <Self as VpmovusqbMaskzEmitter<A, B>>::vpmovusqb_maskz(self, op0, op1);
    }
    /// `VPMOVUSQD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqdEmitter<A, B>,
    {
        <Self as VpmovusqdEmitter<A, B>>::vpmovusqd(self, op0, op1);
    }
    /// `VPMOVUSQD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqdMaskEmitter<A, B>,
    {
        <Self as VpmovusqdMaskEmitter<A, B>>::vpmovusqd_mask(self, op0, op1);
    }
    /// `VPMOVUSQD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Ymm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqdMaskzEmitter<A, B>,
    {
        <Self as VpmovusqdMaskzEmitter<A, B>>::vpmovusqd_maskz(self, op0, op1);
    }
    /// `VPMOVUSQW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqwEmitter<A, B>,
    {
        <Self as VpmovusqwEmitter<A, B>>::vpmovusqw(self, op0, op1);
    }
    /// `VPMOVUSQW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// | 4 | Xmm, Xmm |
    /// | 5 | Xmm, Ymm |
    /// | 6 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqw_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqwMaskEmitter<A, B>,
    {
        <Self as VpmovusqwMaskEmitter<A, B>>::vpmovusqw_mask(self, op0, op1);
    }
    /// `VPMOVUSQW_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// | 2 | Xmm, Ymm |
    /// | 3 | Xmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovusqw_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovusqwMaskzEmitter<A, B>,
    {
        <Self as VpmovusqwMaskzEmitter<A, B>>::vpmovusqw_maskz(self, op0, op1);
    }
    /// `VPMOVZXBD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbdEmitter<A, B>,
    {
        <Self as VpmovzxbdEmitter<A, B>>::vpmovzxbd(self, op0, op1);
    }
    /// `VPMOVZXBD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbdMaskEmitter<A, B>,
    {
        <Self as VpmovzxbdMaskEmitter<A, B>>::vpmovzxbd_mask(self, op0, op1);
    }
    /// `VPMOVZXBD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbdMaskzEmitter<A, B>,
    {
        <Self as VpmovzxbdMaskzEmitter<A, B>>::vpmovzxbd_maskz(self, op0, op1);
    }
    /// `VPMOVZXBQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbqEmitter<A, B>,
    {
        <Self as VpmovzxbqEmitter<A, B>>::vpmovzxbq(self, op0, op1);
    }
    /// `VPMOVZXBQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbqMaskEmitter<A, B>,
    {
        <Self as VpmovzxbqMaskEmitter<A, B>>::vpmovzxbq_mask(self, op0, op1);
    }
    /// `VPMOVZXBQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbqMaskzEmitter<A, B>,
    {
        <Self as VpmovzxbqMaskzEmitter<A, B>>::vpmovzxbq_maskz(self, op0, op1);
    }
    /// `VPMOVZXBW`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbw<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbwEmitter<A, B>,
    {
        <Self as VpmovzxbwEmitter<A, B>>::vpmovzxbw(self, op0, op1);
    }
    /// `VPMOVZXBW_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbw_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbwMaskEmitter<A, B>,
    {
        <Self as VpmovzxbwMaskEmitter<A, B>>::vpmovzxbw_mask(self, op0, op1);
    }
    /// `VPMOVZXBW_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxbw_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxbwMaskzEmitter<A, B>,
    {
        <Self as VpmovzxbwMaskzEmitter<A, B>>::vpmovzxbw_maskz(self, op0, op1);
    }
    /// `VPMOVZXDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxdq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxdqEmitter<A, B>,
    {
        <Self as VpmovzxdqEmitter<A, B>>::vpmovzxdq(self, op0, op1);
    }
    /// `VPMOVZXDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxdq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxdqMaskEmitter<A, B>,
    {
        <Self as VpmovzxdqMaskEmitter<A, B>>::vpmovzxdq_mask(self, op0, op1);
    }
    /// `VPMOVZXDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxdq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxdqMaskzEmitter<A, B>,
    {
        <Self as VpmovzxdqMaskzEmitter<A, B>>::vpmovzxdq_maskz(self, op0, op1);
    }
    /// `VPMOVZXWD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxwd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxwdEmitter<A, B>,
    {
        <Self as VpmovzxwdEmitter<A, B>>::vpmovzxwd(self, op0, op1);
    }
    /// `VPMOVZXWD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxwd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxwdMaskEmitter<A, B>,
    {
        <Self as VpmovzxwdMaskEmitter<A, B>>::vpmovzxwd_mask(self, op0, op1);
    }
    /// `VPMOVZXWD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxwd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxwdMaskzEmitter<A, B>,
    {
        <Self as VpmovzxwdMaskzEmitter<A, B>>::vpmovzxwd_maskz(self, op0, op1);
    }
    /// `VPMOVZXWQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxwq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxwqEmitter<A, B>,
    {
        <Self as VpmovzxwqEmitter<A, B>>::vpmovzxwq(self, op0, op1);
    }
    /// `VPMOVZXWQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxwq_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxwqMaskEmitter<A, B>,
    {
        <Self as VpmovzxwqMaskEmitter<A, B>>::vpmovzxwq_mask(self, op0, op1);
    }
    /// `VPMOVZXWQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Xmm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpmovzxwq_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpmovzxwqMaskzEmitter<A, B>,
    {
        <Self as VpmovzxwqMaskzEmitter<A, B>>::vpmovzxwq_maskz(self, op0, op1);
    }
    /// `VPMULDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmuldq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmuldqEmitter<A, B, C>,
    {
        <Self as VpmuldqEmitter<A, B, C>>::vpmuldq(self, op0, op1, op2);
    }
    /// `VPMULDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmuldq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmuldqMaskEmitter<A, B, C>,
    {
        <Self as VpmuldqMaskEmitter<A, B, C>>::vpmuldq_mask(self, op0, op1, op2);
    }
    /// `VPMULDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmuldq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmuldqMaskzEmitter<A, B, C>,
    {
        <Self as VpmuldqMaskzEmitter<A, B, C>>::vpmuldq_maskz(self, op0, op1, op2);
    }
    /// `VPMULUDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmuludq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmuludqEmitter<A, B, C>,
    {
        <Self as VpmuludqEmitter<A, B, C>>::vpmuludq(self, op0, op1, op2);
    }
    /// `VPMULUDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmuludq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmuludqMaskEmitter<A, B, C>,
    {
        <Self as VpmuludqMaskEmitter<A, B, C>>::vpmuludq_mask(self, op0, op1, op2);
    }
    /// `VPMULUDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpmuludq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpmuludqMaskzEmitter<A, B, C>,
    {
        <Self as VpmuludqMaskzEmitter<A, B, C>>::vpmuludq_maskz(self, op0, op1, op2);
    }
    /// `VPORD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpord<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpordEmitter<A, B, C>,
    {
        <Self as VpordEmitter<A, B, C>>::vpord(self, op0, op1, op2);
    }
    /// `VPORD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpord_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpordMaskEmitter<A, B, C>,
    {
        <Self as VpordMaskEmitter<A, B, C>>::vpord_mask(self, op0, op1, op2);
    }
    /// `VPORD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpord_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpordMaskzEmitter<A, B, C>,
    {
        <Self as VpordMaskzEmitter<A, B, C>>::vpord_maskz(self, op0, op1, op2);
    }
    /// `VPORQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vporq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VporqEmitter<A, B, C>,
    {
        <Self as VporqEmitter<A, B, C>>::vporq(self, op0, op1, op2);
    }
    /// `VPORQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vporq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VporqMaskEmitter<A, B, C>,
    {
        <Self as VporqMaskEmitter<A, B, C>>::vporq_mask(self, op0, op1, op2);
    }
    /// `VPORQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vporq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VporqMaskzEmitter<A, B, C>,
    {
        <Self as VporqMaskzEmitter<A, B, C>>::vporq_maskz(self, op0, op1, op2);
    }
    /// `VPROLD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprold<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VproldEmitter<A, B, C>,
    {
        <Self as VproldEmitter<A, B, C>>::vprold(self, op0, op1, op2);
    }
    /// `VPROLD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprold_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VproldMaskEmitter<A, B, C>,
    {
        <Self as VproldMaskEmitter<A, B, C>>::vprold_mask(self, op0, op1, op2);
    }
    /// `VPROLD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprold_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VproldMaskzEmitter<A, B, C>,
    {
        <Self as VproldMaskzEmitter<A, B, C>>::vprold_maskz(self, op0, op1, op2);
    }
    /// `VPROLQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolqEmitter<A, B, C>,
    {
        <Self as VprolqEmitter<A, B, C>>::vprolq(self, op0, op1, op2);
    }
    /// `VPROLQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolqMaskEmitter<A, B, C>,
    {
        <Self as VprolqMaskEmitter<A, B, C>>::vprolq_mask(self, op0, op1, op2);
    }
    /// `VPROLQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolqMaskzEmitter<A, B, C>,
    {
        <Self as VprolqMaskzEmitter<A, B, C>>::vprolq_maskz(self, op0, op1, op2);
    }
    /// `VPROLVD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolvd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolvdEmitter<A, B, C>,
    {
        <Self as VprolvdEmitter<A, B, C>>::vprolvd(self, op0, op1, op2);
    }
    /// `VPROLVD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolvd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolvdMaskEmitter<A, B, C>,
    {
        <Self as VprolvdMaskEmitter<A, B, C>>::vprolvd_mask(self, op0, op1, op2);
    }
    /// `VPROLVD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolvd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolvdMaskzEmitter<A, B, C>,
    {
        <Self as VprolvdMaskzEmitter<A, B, C>>::vprolvd_maskz(self, op0, op1, op2);
    }
    /// `VPROLVQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolvq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolvqEmitter<A, B, C>,
    {
        <Self as VprolvqEmitter<A, B, C>>::vprolvq(self, op0, op1, op2);
    }
    /// `VPROLVQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolvq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolvqMaskEmitter<A, B, C>,
    {
        <Self as VprolvqMaskEmitter<A, B, C>>::vprolvq_mask(self, op0, op1, op2);
    }
    /// `VPROLVQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprolvq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprolvqMaskzEmitter<A, B, C>,
    {
        <Self as VprolvqMaskzEmitter<A, B, C>>::vprolvq_maskz(self, op0, op1, op2);
    }
    /// `VPRORD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprord<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprordEmitter<A, B, C>,
    {
        <Self as VprordEmitter<A, B, C>>::vprord(self, op0, op1, op2);
    }
    /// `VPRORD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprord_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprordMaskEmitter<A, B, C>,
    {
        <Self as VprordMaskEmitter<A, B, C>>::vprord_mask(self, op0, op1, op2);
    }
    /// `VPRORD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprord_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprordMaskzEmitter<A, B, C>,
    {
        <Self as VprordMaskzEmitter<A, B, C>>::vprord_maskz(self, op0, op1, op2);
    }
    /// `VPRORQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorqEmitter<A, B, C>,
    {
        <Self as VprorqEmitter<A, B, C>>::vprorq(self, op0, op1, op2);
    }
    /// `VPRORQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorqMaskEmitter<A, B, C>,
    {
        <Self as VprorqMaskEmitter<A, B, C>>::vprorq_mask(self, op0, op1, op2);
    }
    /// `VPRORQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorqMaskzEmitter<A, B, C>,
    {
        <Self as VprorqMaskzEmitter<A, B, C>>::vprorq_maskz(self, op0, op1, op2);
    }
    /// `VPRORVD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorvd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorvdEmitter<A, B, C>,
    {
        <Self as VprorvdEmitter<A, B, C>>::vprorvd(self, op0, op1, op2);
    }
    /// `VPRORVD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorvd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorvdMaskEmitter<A, B, C>,
    {
        <Self as VprorvdMaskEmitter<A, B, C>>::vprorvd_mask(self, op0, op1, op2);
    }
    /// `VPRORVD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorvd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorvdMaskzEmitter<A, B, C>,
    {
        <Self as VprorvdMaskzEmitter<A, B, C>>::vprorvd_maskz(self, op0, op1, op2);
    }
    /// `VPRORVQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorvq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorvqEmitter<A, B, C>,
    {
        <Self as VprorvqEmitter<A, B, C>>::vprorvq(self, op0, op1, op2);
    }
    /// `VPRORVQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorvq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorvqMaskEmitter<A, B, C>,
    {
        <Self as VprorvqMaskEmitter<A, B, C>>::vprorvq_mask(self, op0, op1, op2);
    }
    /// `VPRORVQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vprorvq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VprorvqMaskzEmitter<A, B, C>,
    {
        <Self as VprorvqMaskzEmitter<A, B, C>>::vprorvq_maskz(self, op0, op1, op2);
    }
    /// `VPSCATTERDD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpscatterdd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpscatterddEmitter<A, B>,
    {
        <Self as VpscatterddEmitter<A, B>>::vpscatterdd(self, op0, op1);
    }
    /// `VPSCATTERDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpscatterdq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpscatterdqEmitter<A, B>,
    {
        <Self as VpscatterdqEmitter<A, B>>::vpscatterdq(self, op0, op1);
    }
    /// `VPSCATTERQD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpscatterqd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpscatterqdEmitter<A, B>,
    {
        <Self as VpscatterqdEmitter<A, B>>::vpscatterqd(self, op0, op1);
    }
    /// `VPSCATTERQQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vpscatterqq<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VpscatterqqEmitter<A, B>,
    {
        <Self as VpscatterqqEmitter<A, B>>::vpscatterqq(self, op0, op1);
    }
    /// `VPSHUFD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpshufd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpshufdEmitter<A, B, C>,
    {
        <Self as VpshufdEmitter<A, B, C>>::vpshufd(self, op0, op1, op2);
    }
    /// `VPSHUFD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpshufd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpshufdMaskEmitter<A, B, C>,
    {
        <Self as VpshufdMaskEmitter<A, B, C>>::vpshufd_mask(self, op0, op1, op2);
    }
    /// `VPSHUFD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpshufd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpshufdMaskzEmitter<A, B, C>,
    {
        <Self as VpshufdMaskzEmitter<A, B, C>>::vpshufd_maskz(self, op0, op1, op2);
    }
    /// `VPSLLD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpslld<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpslldEmitter<A, B, C>,
    {
        <Self as VpslldEmitter<A, B, C>>::vpslld(self, op0, op1, op2);
    }
    /// `VPSLLD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpslld_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpslldMaskEmitter<A, B, C>,
    {
        <Self as VpslldMaskEmitter<A, B, C>>::vpslld_mask(self, op0, op1, op2);
    }
    /// `VPSLLD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpslld_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpslldMaskzEmitter<A, B, C>,
    {
        <Self as VpslldMaskzEmitter<A, B, C>>::vpslld_maskz(self, op0, op1, op2);
    }
    /// `VPSLLQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsllq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllqEmitter<A, B, C>,
    {
        <Self as VpsllqEmitter<A, B, C>>::vpsllq(self, op0, op1, op2);
    }
    /// `VPSLLQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsllq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllqMaskEmitter<A, B, C>,
    {
        <Self as VpsllqMaskEmitter<A, B, C>>::vpsllq_mask(self, op0, op1, op2);
    }
    /// `VPSLLQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsllq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllqMaskzEmitter<A, B, C>,
    {
        <Self as VpsllqMaskzEmitter<A, B, C>>::vpsllq_maskz(self, op0, op1, op2);
    }
    /// `VPSLLVD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsllvd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllvdEmitter<A, B, C>,
    {
        <Self as VpsllvdEmitter<A, B, C>>::vpsllvd(self, op0, op1, op2);
    }
    /// `VPSLLVD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsllvd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllvdMaskEmitter<A, B, C>,
    {
        <Self as VpsllvdMaskEmitter<A, B, C>>::vpsllvd_mask(self, op0, op1, op2);
    }
    /// `VPSLLVD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsllvd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllvdMaskzEmitter<A, B, C>,
    {
        <Self as VpsllvdMaskzEmitter<A, B, C>>::vpsllvd_maskz(self, op0, op1, op2);
    }
    /// `VPSLLVQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsllvq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllvqEmitter<A, B, C>,
    {
        <Self as VpsllvqEmitter<A, B, C>>::vpsllvq(self, op0, op1, op2);
    }
    /// `VPSLLVQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsllvq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllvqMaskEmitter<A, B, C>,
    {
        <Self as VpsllvqMaskEmitter<A, B, C>>::vpsllvq_mask(self, op0, op1, op2);
    }
    /// `VPSLLVQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsllvq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsllvqMaskzEmitter<A, B, C>,
    {
        <Self as VpsllvqMaskzEmitter<A, B, C>>::vpsllvq_maskz(self, op0, op1, op2);
    }
    /// `VPSRAD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrad<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsradEmitter<A, B, C>,
    {
        <Self as VpsradEmitter<A, B, C>>::vpsrad(self, op0, op1, op2);
    }
    /// `VPSRAD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrad_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsradMaskEmitter<A, B, C>,
    {
        <Self as VpsradMaskEmitter<A, B, C>>::vpsrad_mask(self, op0, op1, op2);
    }
    /// `VPSRAD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrad_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsradMaskzEmitter<A, B, C>,
    {
        <Self as VpsradMaskzEmitter<A, B, C>>::vpsrad_maskz(self, op0, op1, op2);
    }
    /// `VPSRAQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsraq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsraqEmitter<A, B, C>,
    {
        <Self as VpsraqEmitter<A, B, C>>::vpsraq(self, op0, op1, op2);
    }
    /// `VPSRAQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsraq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsraqMaskEmitter<A, B, C>,
    {
        <Self as VpsraqMaskEmitter<A, B, C>>::vpsraq_mask(self, op0, op1, op2);
    }
    /// `VPSRAQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsraq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsraqMaskzEmitter<A, B, C>,
    {
        <Self as VpsraqMaskzEmitter<A, B, C>>::vpsraq_maskz(self, op0, op1, op2);
    }
    /// `VPSRAVD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsravd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsravdEmitter<A, B, C>,
    {
        <Self as VpsravdEmitter<A, B, C>>::vpsravd(self, op0, op1, op2);
    }
    /// `VPSRAVD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsravd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsravdMaskEmitter<A, B, C>,
    {
        <Self as VpsravdMaskEmitter<A, B, C>>::vpsravd_mask(self, op0, op1, op2);
    }
    /// `VPSRAVD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsravd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsravdMaskzEmitter<A, B, C>,
    {
        <Self as VpsravdMaskzEmitter<A, B, C>>::vpsravd_maskz(self, op0, op1, op2);
    }
    /// `VPSRAVQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsravq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsravqEmitter<A, B, C>,
    {
        <Self as VpsravqEmitter<A, B, C>>::vpsravq(self, op0, op1, op2);
    }
    /// `VPSRAVQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsravq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsravqMaskEmitter<A, B, C>,
    {
        <Self as VpsravqMaskEmitter<A, B, C>>::vpsravq_mask(self, op0, op1, op2);
    }
    /// `VPSRAVQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsravq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsravqMaskzEmitter<A, B, C>,
    {
        <Self as VpsravqMaskzEmitter<A, B, C>>::vpsravq_maskz(self, op0, op1, op2);
    }
    /// `VPSRLD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrld<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrldEmitter<A, B, C>,
    {
        <Self as VpsrldEmitter<A, B, C>>::vpsrld(self, op0, op1, op2);
    }
    /// `VPSRLD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrld_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrldMaskEmitter<A, B, C>,
    {
        <Self as VpsrldMaskEmitter<A, B, C>>::vpsrld_mask(self, op0, op1, op2);
    }
    /// `VPSRLD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrld_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrldMaskzEmitter<A, B, C>,
    {
        <Self as VpsrldMaskzEmitter<A, B, C>>::vpsrld_maskz(self, op0, op1, op2);
    }
    /// `VPSRLQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrlq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlqEmitter<A, B, C>,
    {
        <Self as VpsrlqEmitter<A, B, C>>::vpsrlq(self, op0, op1, op2);
    }
    /// `VPSRLQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrlq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlqMaskEmitter<A, B, C>,
    {
        <Self as VpsrlqMaskEmitter<A, B, C>>::vpsrlq_mask(self, op0, op1, op2);
    }
    /// `VPSRLQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +----+---------------+
    /// | #  | Operands      |
    /// +----+---------------+
    /// | 1  | Xmm, Mem, Imm |
    /// | 2  | Xmm, Xmm, Imm |
    /// | 3  | Xmm, Xmm, Mem |
    /// | 4  | Xmm, Xmm, Xmm |
    /// | 5  | Ymm, Mem, Imm |
    /// | 6  | Ymm, Ymm, Imm |
    /// | 7  | Ymm, Ymm, Mem |
    /// | 8  | Ymm, Ymm, Xmm |
    /// | 9  | Zmm, Mem, Imm |
    /// | 10 | Zmm, Zmm, Imm |
    /// | 11 | Zmm, Zmm, Mem |
    /// | 12 | Zmm, Zmm, Xmm |
    /// +----+---------------+
    /// ```
    #[inline]
    pub fn vpsrlq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlqMaskzEmitter<A, B, C>,
    {
        <Self as VpsrlqMaskzEmitter<A, B, C>>::vpsrlq_maskz(self, op0, op1, op2);
    }
    /// `VPSRLVD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsrlvd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlvdEmitter<A, B, C>,
    {
        <Self as VpsrlvdEmitter<A, B, C>>::vpsrlvd(self, op0, op1, op2);
    }
    /// `VPSRLVD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsrlvd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlvdMaskEmitter<A, B, C>,
    {
        <Self as VpsrlvdMaskEmitter<A, B, C>>::vpsrlvd_mask(self, op0, op1, op2);
    }
    /// `VPSRLVD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsrlvd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlvdMaskzEmitter<A, B, C>,
    {
        <Self as VpsrlvdMaskzEmitter<A, B, C>>::vpsrlvd_maskz(self, op0, op1, op2);
    }
    /// `VPSRLVQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsrlvq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlvqEmitter<A, B, C>,
    {
        <Self as VpsrlvqEmitter<A, B, C>>::vpsrlvq(self, op0, op1, op2);
    }
    /// `VPSRLVQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsrlvq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlvqMaskEmitter<A, B, C>,
    {
        <Self as VpsrlvqMaskEmitter<A, B, C>>::vpsrlvq_mask(self, op0, op1, op2);
    }
    /// `VPSRLVQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsrlvq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsrlvqMaskzEmitter<A, B, C>,
    {
        <Self as VpsrlvqMaskzEmitter<A, B, C>>::vpsrlvq_maskz(self, op0, op1, op2);
    }
    /// `VPSUBD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsubd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsubdEmitter<A, B, C>,
    {
        <Self as VpsubdEmitter<A, B, C>>::vpsubd(self, op0, op1, op2);
    }
    /// `VPSUBD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsubd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsubdMaskEmitter<A, B, C>,
    {
        <Self as VpsubdMaskEmitter<A, B, C>>::vpsubd_mask(self, op0, op1, op2);
    }
    /// `VPSUBD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsubd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsubdMaskzEmitter<A, B, C>,
    {
        <Self as VpsubdMaskzEmitter<A, B, C>>::vpsubd_maskz(self, op0, op1, op2);
    }
    /// `VPSUBQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsubq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsubqEmitter<A, B, C>,
    {
        <Self as VpsubqEmitter<A, B, C>>::vpsubq(self, op0, op1, op2);
    }
    /// `VPSUBQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsubq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsubqMaskEmitter<A, B, C>,
    {
        <Self as VpsubqMaskEmitter<A, B, C>>::vpsubq_mask(self, op0, op1, op2);
    }
    /// `VPSUBQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpsubq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpsubqMaskzEmitter<A, B, C>,
    {
        <Self as VpsubqMaskzEmitter<A, B, C>>::vpsubq_maskz(self, op0, op1, op2);
    }
    /// `VPTERNLOGD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vpternlogd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpternlogdEmitter<A, B, C, D>,
    {
        <Self as VpternlogdEmitter<A, B, C, D>>::vpternlogd(self, op0, op1, op2, op3);
    }
    /// `VPTERNLOGD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vpternlogd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpternlogdMaskEmitter<A, B, C, D>,
    {
        <Self as VpternlogdMaskEmitter<A, B, C, D>>::vpternlogd_mask(self, op0, op1, op2, op3);
    }
    /// `VPTERNLOGD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vpternlogd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpternlogdMaskzEmitter<A, B, C, D>,
    {
        <Self as VpternlogdMaskzEmitter<A, B, C, D>>::vpternlogd_maskz(self, op0, op1, op2, op3);
    }
    /// `VPTERNLOGQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vpternlogq<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpternlogqEmitter<A, B, C, D>,
    {
        <Self as VpternlogqEmitter<A, B, C, D>>::vpternlogq(self, op0, op1, op2, op3);
    }
    /// `VPTERNLOGQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vpternlogq_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpternlogqMaskEmitter<A, B, C, D>,
    {
        <Self as VpternlogqMaskEmitter<A, B, C, D>>::vpternlogq_mask(self, op0, op1, op2, op3);
    }
    /// `VPTERNLOGQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vpternlogq_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VpternlogqMaskzEmitter<A, B, C, D>,
    {
        <Self as VpternlogqMaskzEmitter<A, B, C, D>>::vpternlogq_maskz(self, op0, op1, op2, op3);
    }
    /// `VPTESTMD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vptestmd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VptestmdEmitter<A, B, C>,
    {
        <Self as VptestmdEmitter<A, B, C>>::vptestmd(self, op0, op1, op2);
    }
    /// `VPTESTMD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vptestmd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VptestmdMaskEmitter<A, B, C>,
    {
        <Self as VptestmdMaskEmitter<A, B, C>>::vptestmd_mask(self, op0, op1, op2);
    }
    /// `VPTESTMQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vptestmq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VptestmqEmitter<A, B, C>,
    {
        <Self as VptestmqEmitter<A, B, C>>::vptestmq(self, op0, op1, op2);
    }
    /// `VPTESTMQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vptestmq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VptestmqMaskEmitter<A, B, C>,
    {
        <Self as VptestmqMaskEmitter<A, B, C>>::vptestmq_mask(self, op0, op1, op2);
    }
    /// `VPTESTNMD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vptestnmd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VptestnmdEmitter<A, B, C>,
    {
        <Self as VptestnmdEmitter<A, B, C>>::vptestnmd(self, op0, op1, op2);
    }
    /// `VPTESTNMD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vptestnmd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VptestnmdMaskEmitter<A, B, C>,
    {
        <Self as VptestnmdMaskEmitter<A, B, C>>::vptestnmd_mask(self, op0, op1, op2);
    }
    /// `VPTESTNMQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vptestnmq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VptestnmqEmitter<A, B, C>,
    {
        <Self as VptestnmqEmitter<A, B, C>>::vptestnmq(self, op0, op1, op2);
    }
    /// `VPTESTNMQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------------+
    /// | # | Operands       |
    /// +---+----------------+
    /// | 1 | KReg, Xmm, Mem |
    /// | 2 | KReg, Xmm, Xmm |
    /// | 3 | KReg, Ymm, Mem |
    /// | 4 | KReg, Ymm, Ymm |
    /// | 5 | KReg, Zmm, Mem |
    /// | 6 | KReg, Zmm, Zmm |
    /// +---+----------------+
    /// ```
    #[inline]
    pub fn vptestnmq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VptestnmqMaskEmitter<A, B, C>,
    {
        <Self as VptestnmqMaskEmitter<A, B, C>>::vptestnmq_mask(self, op0, op1, op2);
    }
    /// `VPUNPCKHDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckhdq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckhdqEmitter<A, B, C>,
    {
        <Self as VpunpckhdqEmitter<A, B, C>>::vpunpckhdq(self, op0, op1, op2);
    }
    /// `VPUNPCKHDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckhdq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckhdqMaskEmitter<A, B, C>,
    {
        <Self as VpunpckhdqMaskEmitter<A, B, C>>::vpunpckhdq_mask(self, op0, op1, op2);
    }
    /// `VPUNPCKHDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckhdq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckhdqMaskzEmitter<A, B, C>,
    {
        <Self as VpunpckhdqMaskzEmitter<A, B, C>>::vpunpckhdq_maskz(self, op0, op1, op2);
    }
    /// `VPUNPCKHQDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckhqdq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckhqdqEmitter<A, B, C>,
    {
        <Self as VpunpckhqdqEmitter<A, B, C>>::vpunpckhqdq(self, op0, op1, op2);
    }
    /// `VPUNPCKHQDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckhqdq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckhqdqMaskEmitter<A, B, C>,
    {
        <Self as VpunpckhqdqMaskEmitter<A, B, C>>::vpunpckhqdq_mask(self, op0, op1, op2);
    }
    /// `VPUNPCKHQDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckhqdq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckhqdqMaskzEmitter<A, B, C>,
    {
        <Self as VpunpckhqdqMaskzEmitter<A, B, C>>::vpunpckhqdq_maskz(self, op0, op1, op2);
    }
    /// `VPUNPCKLDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckldq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckldqEmitter<A, B, C>,
    {
        <Self as VpunpckldqEmitter<A, B, C>>::vpunpckldq(self, op0, op1, op2);
    }
    /// `VPUNPCKLDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckldq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckldqMaskEmitter<A, B, C>,
    {
        <Self as VpunpckldqMaskEmitter<A, B, C>>::vpunpckldq_mask(self, op0, op1, op2);
    }
    /// `VPUNPCKLDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpckldq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpckldqMaskzEmitter<A, B, C>,
    {
        <Self as VpunpckldqMaskzEmitter<A, B, C>>::vpunpckldq_maskz(self, op0, op1, op2);
    }
    /// `VPUNPCKLQDQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpcklqdq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpcklqdqEmitter<A, B, C>,
    {
        <Self as VpunpcklqdqEmitter<A, B, C>>::vpunpcklqdq(self, op0, op1, op2);
    }
    /// `VPUNPCKLQDQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpcklqdq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpcklqdqMaskEmitter<A, B, C>,
    {
        <Self as VpunpcklqdqMaskEmitter<A, B, C>>::vpunpcklqdq_mask(self, op0, op1, op2);
    }
    /// `VPUNPCKLQDQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpunpcklqdq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpunpcklqdqMaskzEmitter<A, B, C>,
    {
        <Self as VpunpcklqdqMaskzEmitter<A, B, C>>::vpunpcklqdq_maskz(self, op0, op1, op2);
    }
    /// `VPXORD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpxord<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpxordEmitter<A, B, C>,
    {
        <Self as VpxordEmitter<A, B, C>>::vpxord(self, op0, op1, op2);
    }
    /// `VPXORD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpxord_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpxordMaskEmitter<A, B, C>,
    {
        <Self as VpxordMaskEmitter<A, B, C>>::vpxord_mask(self, op0, op1, op2);
    }
    /// `VPXORD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpxord_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpxordMaskzEmitter<A, B, C>,
    {
        <Self as VpxordMaskzEmitter<A, B, C>>::vpxord_maskz(self, op0, op1, op2);
    }
    /// `VPXORQ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpxorq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpxorqEmitter<A, B, C>,
    {
        <Self as VpxorqEmitter<A, B, C>>::vpxorq(self, op0, op1, op2);
    }
    /// `VPXORQ_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpxorq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpxorqMaskEmitter<A, B, C>,
    {
        <Self as VpxorqMaskEmitter<A, B, C>>::vpxorq_mask(self, op0, op1, op2);
    }
    /// `VPXORQ_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vpxorq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VpxorqMaskzEmitter<A, B, C>,
    {
        <Self as VpxorqMaskzEmitter<A, B, C>>::vpxorq_maskz(self, op0, op1, op2);
    }
    /// `VRCP14PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrcp14pd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrcp14pdEmitter<A, B>,
    {
        <Self as Vrcp14pdEmitter<A, B>>::vrcp14pd(self, op0, op1);
    }
    /// `VRCP14PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrcp14pd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrcp14pdMaskEmitter<A, B>,
    {
        <Self as Vrcp14pdMaskEmitter<A, B>>::vrcp14pd_mask(self, op0, op1);
    }
    /// `VRCP14PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrcp14pd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrcp14pdMaskzEmitter<A, B>,
    {
        <Self as Vrcp14pdMaskzEmitter<A, B>>::vrcp14pd_maskz(self, op0, op1);
    }
    /// `VRCP14PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrcp14ps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrcp14psEmitter<A, B>,
    {
        <Self as Vrcp14psEmitter<A, B>>::vrcp14ps(self, op0, op1);
    }
    /// `VRCP14PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrcp14ps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrcp14psMaskEmitter<A, B>,
    {
        <Self as Vrcp14psMaskEmitter<A, B>>::vrcp14ps_mask(self, op0, op1);
    }
    /// `VRCP14PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrcp14ps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrcp14psMaskzEmitter<A, B>,
    {
        <Self as Vrcp14psMaskzEmitter<A, B>>::vrcp14ps_maskz(self, op0, op1);
    }
    /// `VRCP14SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrcp14sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrcp14sdEmitter<A, B, C>,
    {
        <Self as Vrcp14sdEmitter<A, B, C>>::vrcp14sd(self, op0, op1, op2);
    }
    /// `VRCP14SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrcp14sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrcp14sdMaskEmitter<A, B, C>,
    {
        <Self as Vrcp14sdMaskEmitter<A, B, C>>::vrcp14sd_mask(self, op0, op1, op2);
    }
    /// `VRCP14SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrcp14sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrcp14sdMaskzEmitter<A, B, C>,
    {
        <Self as Vrcp14sdMaskzEmitter<A, B, C>>::vrcp14sd_maskz(self, op0, op1, op2);
    }
    /// `VRCP14SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrcp14ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrcp14ssEmitter<A, B, C>,
    {
        <Self as Vrcp14ssEmitter<A, B, C>>::vrcp14ss(self, op0, op1, op2);
    }
    /// `VRCP14SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrcp14ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrcp14ssMaskEmitter<A, B, C>,
    {
        <Self as Vrcp14ssMaskEmitter<A, B, C>>::vrcp14ss_mask(self, op0, op1, op2);
    }
    /// `VRCP14SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrcp14ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrcp14ssMaskzEmitter<A, B, C>,
    {
        <Self as Vrcp14ssMaskzEmitter<A, B, C>>::vrcp14ss_maskz(self, op0, op1, op2);
    }
    /// `VRNDSCALEPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscalepd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepdEmitter<A, B, C>,
    {
        <Self as VrndscalepdEmitter<A, B, C>>::vrndscalepd(self, op0, op1, op2);
    }
    /// `VRNDSCALEPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscalepd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepdMaskEmitter<A, B, C>,
    {
        <Self as VrndscalepdMaskEmitter<A, B, C>>::vrndscalepd_mask(self, op0, op1, op2);
    }
    /// `VRNDSCALEPD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscalepd_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepdMaskSaeEmitter<A, B, C>,
    {
        <Self as VrndscalepdMaskSaeEmitter<A, B, C>>::vrndscalepd_mask_sae(self, op0, op1, op2);
    }
    /// `VRNDSCALEPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscalepd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepdMaskzEmitter<A, B, C>,
    {
        <Self as VrndscalepdMaskzEmitter<A, B, C>>::vrndscalepd_maskz(self, op0, op1, op2);
    }
    /// `VRNDSCALEPD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscalepd_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepdMaskzSaeEmitter<A, B, C>,
    {
        <Self as VrndscalepdMaskzSaeEmitter<A, B, C>>::vrndscalepd_maskz_sae(self, op0, op1, op2);
    }
    /// `VRNDSCALEPD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscalepd_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepdSaeEmitter<A, B, C>,
    {
        <Self as VrndscalepdSaeEmitter<A, B, C>>::vrndscalepd_sae(self, op0, op1, op2);
    }
    /// `VRNDSCALEPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscaleps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepsEmitter<A, B, C>,
    {
        <Self as VrndscalepsEmitter<A, B, C>>::vrndscaleps(self, op0, op1, op2);
    }
    /// `VRNDSCALEPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscaleps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepsMaskEmitter<A, B, C>,
    {
        <Self as VrndscalepsMaskEmitter<A, B, C>>::vrndscaleps_mask(self, op0, op1, op2);
    }
    /// `VRNDSCALEPS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscaleps_mask_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepsMaskSaeEmitter<A, B, C>,
    {
        <Self as VrndscalepsMaskSaeEmitter<A, B, C>>::vrndscaleps_mask_sae(self, op0, op1, op2);
    }
    /// `VRNDSCALEPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Imm |
    /// | 3 | Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Imm |
    /// | 5 | Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscaleps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepsMaskzEmitter<A, B, C>,
    {
        <Self as VrndscalepsMaskzEmitter<A, B, C>>::vrndscaleps_maskz(self, op0, op1, op2);
    }
    /// `VRNDSCALEPS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscaleps_maskz_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepsMaskzSaeEmitter<A, B, C>,
    {
        <Self as VrndscalepsMaskzSaeEmitter<A, B, C>>::vrndscaleps_maskz_sae(self, op0, op1, op2);
    }
    /// `VRNDSCALEPS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Imm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrndscaleps_sae<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VrndscalepsSaeEmitter<A, B, C>,
    {
        <Self as VrndscalepsSaeEmitter<A, B, C>>::vrndscaleps_sae(self, op0, op1, op2);
    }
    /// `VRNDSCALESD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscalesd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalesdEmitter<A, B, C, D>,
    {
        <Self as VrndscalesdEmitter<A, B, C, D>>::vrndscalesd(self, op0, op1, op2, op3);
    }
    /// `VRNDSCALESD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscalesd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalesdMaskEmitter<A, B, C, D>,
    {
        <Self as VrndscalesdMaskEmitter<A, B, C, D>>::vrndscalesd_mask(self, op0, op1, op2, op3);
    }
    /// `VRNDSCALESD_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscalesd_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalesdMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VrndscalesdMaskSaeEmitter<A, B, C, D>>::vrndscalesd_mask_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VRNDSCALESD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscalesd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalesdMaskzEmitter<A, B, C, D>,
    {
        <Self as VrndscalesdMaskzEmitter<A, B, C, D>>::vrndscalesd_maskz(self, op0, op1, op2, op3);
    }
    /// `VRNDSCALESD_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscalesd_maskz_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalesdMaskzSaeEmitter<A, B, C, D>,
    {
        <Self as VrndscalesdMaskzSaeEmitter<A, B, C, D>>::vrndscalesd_maskz_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VRNDSCALESD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscalesd_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalesdSaeEmitter<A, B, C, D>,
    {
        <Self as VrndscalesdSaeEmitter<A, B, C, D>>::vrndscalesd_sae(self, op0, op1, op2, op3);
    }
    /// `VRNDSCALESS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscaless<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalessEmitter<A, B, C, D>,
    {
        <Self as VrndscalessEmitter<A, B, C, D>>::vrndscaless(self, op0, op1, op2, op3);
    }
    /// `VRNDSCALESS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscaless_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalessMaskEmitter<A, B, C, D>,
    {
        <Self as VrndscalessMaskEmitter<A, B, C, D>>::vrndscaless_mask(self, op0, op1, op2, op3);
    }
    /// `VRNDSCALESS_MASK_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscaless_mask_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalessMaskSaeEmitter<A, B, C, D>,
    {
        <Self as VrndscalessMaskSaeEmitter<A, B, C, D>>::vrndscaless_mask_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VRNDSCALESS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscaless_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalessMaskzEmitter<A, B, C, D>,
    {
        <Self as VrndscalessMaskzEmitter<A, B, C, D>>::vrndscaless_maskz(self, op0, op1, op2, op3);
    }
    /// `VRNDSCALESS_MASKZ_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscaless_maskz_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalessMaskzSaeEmitter<A, B, C, D>,
    {
        <Self as VrndscalessMaskzSaeEmitter<A, B, C, D>>::vrndscaless_maskz_sae(
            self, op0, op1, op2, op3,
        );
    }
    /// `VRNDSCALESS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Xmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vrndscaless_sae<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VrndscalessSaeEmitter<A, B, C, D>,
    {
        <Self as VrndscalessSaeEmitter<A, B, C, D>>::vrndscaless_sae(self, op0, op1, op2, op3);
    }
    /// `VRSQRT14PD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrsqrt14pd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrsqrt14pdEmitter<A, B>,
    {
        <Self as Vrsqrt14pdEmitter<A, B>>::vrsqrt14pd(self, op0, op1);
    }
    /// `VRSQRT14PD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrsqrt14pd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrsqrt14pdMaskEmitter<A, B>,
    {
        <Self as Vrsqrt14pdMaskEmitter<A, B>>::vrsqrt14pd_mask(self, op0, op1);
    }
    /// `VRSQRT14PD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrsqrt14pd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrsqrt14pdMaskzEmitter<A, B>,
    {
        <Self as Vrsqrt14pdMaskzEmitter<A, B>>::vrsqrt14pd_maskz(self, op0, op1);
    }
    /// `VRSQRT14PS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrsqrt14ps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrsqrt14psEmitter<A, B>,
    {
        <Self as Vrsqrt14psEmitter<A, B>>::vrsqrt14ps(self, op0, op1);
    }
    /// `VRSQRT14PS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrsqrt14ps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrsqrt14psMaskEmitter<A, B>,
    {
        <Self as Vrsqrt14psMaskEmitter<A, B>>::vrsqrt14ps_mask(self, op0, op1);
    }
    /// `VRSQRT14PS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vrsqrt14ps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: Vrsqrt14psMaskzEmitter<A, B>,
    {
        <Self as Vrsqrt14psMaskzEmitter<A, B>>::vrsqrt14ps_maskz(self, op0, op1);
    }
    /// `VRSQRT14SD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrsqrt14sd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrsqrt14sdEmitter<A, B, C>,
    {
        <Self as Vrsqrt14sdEmitter<A, B, C>>::vrsqrt14sd(self, op0, op1, op2);
    }
    /// `VRSQRT14SD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrsqrt14sd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrsqrt14sdMaskEmitter<A, B, C>,
    {
        <Self as Vrsqrt14sdMaskEmitter<A, B, C>>::vrsqrt14sd_mask(self, op0, op1, op2);
    }
    /// `VRSQRT14SD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrsqrt14sd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrsqrt14sdMaskzEmitter<A, B, C>,
    {
        <Self as Vrsqrt14sdMaskzEmitter<A, B, C>>::vrsqrt14sd_maskz(self, op0, op1, op2);
    }
    /// `VRSQRT14SS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrsqrt14ss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrsqrt14ssEmitter<A, B, C>,
    {
        <Self as Vrsqrt14ssEmitter<A, B, C>>::vrsqrt14ss(self, op0, op1, op2);
    }
    /// `VRSQRT14SS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrsqrt14ss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrsqrt14ssMaskEmitter<A, B, C>,
    {
        <Self as Vrsqrt14ssMaskEmitter<A, B, C>>::vrsqrt14ss_mask(self, op0, op1, op2);
    }
    /// `VRSQRT14SS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vrsqrt14ss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: Vrsqrt14ssMaskzEmitter<A, B, C>,
    {
        <Self as Vrsqrt14ssMaskzEmitter<A, B, C>>::vrsqrt14ss_maskz(self, op0, op1, op2);
    }
    /// `VSCALEFPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpdEmitter<A, B, C>,
    {
        <Self as VscalefpdEmitter<A, B, C>>::vscalefpd(self, op0, op1, op2);
    }
    /// `VSCALEFPD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefpd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpdErEmitter<A, B, C>,
    {
        <Self as VscalefpdErEmitter<A, B, C>>::vscalefpd_er(self, op0, op1, op2);
    }
    /// `VSCALEFPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpdMaskEmitter<A, B, C>,
    {
        <Self as VscalefpdMaskEmitter<A, B, C>>::vscalefpd_mask(self, op0, op1, op2);
    }
    /// `VSCALEFPD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefpd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpdMaskErEmitter<A, B, C>,
    {
        <Self as VscalefpdMaskErEmitter<A, B, C>>::vscalefpd_mask_er(self, op0, op1, op2);
    }
    /// `VSCALEFPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpdMaskzEmitter<A, B, C>,
    {
        <Self as VscalefpdMaskzEmitter<A, B, C>>::vscalefpd_maskz(self, op0, op1, op2);
    }
    /// `VSCALEFPD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefpd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpdMaskzErEmitter<A, B, C>,
    {
        <Self as VscalefpdMaskzErEmitter<A, B, C>>::vscalefpd_maskz_er(self, op0, op1, op2);
    }
    /// `VSCALEFPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpsEmitter<A, B, C>,
    {
        <Self as VscalefpsEmitter<A, B, C>>::vscalefps(self, op0, op1, op2);
    }
    /// `VSCALEFPS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpsErEmitter<A, B, C>,
    {
        <Self as VscalefpsErEmitter<A, B, C>>::vscalefps_er(self, op0, op1, op2);
    }
    /// `VSCALEFPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpsMaskEmitter<A, B, C>,
    {
        <Self as VscalefpsMaskEmitter<A, B, C>>::vscalefps_mask(self, op0, op1, op2);
    }
    /// `VSCALEFPS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpsMaskErEmitter<A, B, C>,
    {
        <Self as VscalefpsMaskErEmitter<A, B, C>>::vscalefps_mask_er(self, op0, op1, op2);
    }
    /// `VSCALEFPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpsMaskzEmitter<A, B, C>,
    {
        <Self as VscalefpsMaskzEmitter<A, B, C>>::vscalefps_maskz(self, op0, op1, op2);
    }
    /// `VSCALEFPS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefpsMaskzErEmitter<A, B, C>,
    {
        <Self as VscalefpsMaskzErEmitter<A, B, C>>::vscalefps_maskz_er(self, op0, op1, op2);
    }
    /// `VSCALEFSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefsdEmitter<A, B, C>,
    {
        <Self as VscalefsdEmitter<A, B, C>>::vscalefsd(self, op0, op1, op2);
    }
    /// `VSCALEFSD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefsd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefsdErEmitter<A, B, C>,
    {
        <Self as VscalefsdErEmitter<A, B, C>>::vscalefsd_er(self, op0, op1, op2);
    }
    /// `VSCALEFSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefsdMaskEmitter<A, B, C>,
    {
        <Self as VscalefsdMaskEmitter<A, B, C>>::vscalefsd_mask(self, op0, op1, op2);
    }
    /// `VSCALEFSD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefsd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefsdMaskErEmitter<A, B, C>,
    {
        <Self as VscalefsdMaskErEmitter<A, B, C>>::vscalefsd_mask_er(self, op0, op1, op2);
    }
    /// `VSCALEFSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefsdMaskzEmitter<A, B, C>,
    {
        <Self as VscalefsdMaskzEmitter<A, B, C>>::vscalefsd_maskz(self, op0, op1, op2);
    }
    /// `VSCALEFSD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefsd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefsdMaskzErEmitter<A, B, C>,
    {
        <Self as VscalefsdMaskzErEmitter<A, B, C>>::vscalefsd_maskz_er(self, op0, op1, op2);
    }
    /// `VSCALEFSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefssEmitter<A, B, C>,
    {
        <Self as VscalefssEmitter<A, B, C>>::vscalefss(self, op0, op1, op2);
    }
    /// `VSCALEFSS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefssErEmitter<A, B, C>,
    {
        <Self as VscalefssErEmitter<A, B, C>>::vscalefss_er(self, op0, op1, op2);
    }
    /// `VSCALEFSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefssMaskEmitter<A, B, C>,
    {
        <Self as VscalefssMaskEmitter<A, B, C>>::vscalefss_mask(self, op0, op1, op2);
    }
    /// `VSCALEFSS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefssMaskErEmitter<A, B, C>,
    {
        <Self as VscalefssMaskErEmitter<A, B, C>>::vscalefss_mask_er(self, op0, op1, op2);
    }
    /// `VSCALEFSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefssMaskzEmitter<A, B, C>,
    {
        <Self as VscalefssMaskzEmitter<A, B, C>>::vscalefss_maskz(self, op0, op1, op2);
    }
    /// `VSCALEFSS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vscalefss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VscalefssMaskzErEmitter<A, B, C>,
    {
        <Self as VscalefssMaskzErEmitter<A, B, C>>::vscalefss_maskz_er(self, op0, op1, op2);
    }
    /// `VSCATTERDPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vscatterdpd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VscatterdpdEmitter<A, B>,
    {
        <Self as VscatterdpdEmitter<A, B>>::vscatterdpd(self, op0, op1);
    }
    /// `VSCATTERDPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vscatterdps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VscatterdpsEmitter<A, B>,
    {
        <Self as VscatterdpsEmitter<A, B>>::vscatterdps(self, op0, op1);
    }
    /// `VSCATTERQPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// | 3 | Mem, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vscatterqpd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VscatterqpdEmitter<A, B>,
    {
        <Self as VscatterqpdEmitter<A, B>>::vscatterqpd(self, op0, op1);
    }
    /// `VSCATTERQPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Mem, Xmm |
    /// | 2 | Mem, Ymm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vscatterqps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VscatterqpsEmitter<A, B>,
    {
        <Self as VscatterqpsEmitter<A, B>>::vscatterqps(self, op0, op1);
    }
    /// `VSHUFF32X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshuff32x4<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshuff32x4Emitter<A, B, C, D>,
    {
        <Self as Vshuff32x4Emitter<A, B, C, D>>::vshuff32x4(self, op0, op1, op2, op3);
    }
    /// `VSHUFF32X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshuff32x4_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshuff32x4MaskEmitter<A, B, C, D>,
    {
        <Self as Vshuff32x4MaskEmitter<A, B, C, D>>::vshuff32x4_mask(self, op0, op1, op2, op3);
    }
    /// `VSHUFF32X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshuff32x4_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshuff32x4MaskzEmitter<A, B, C, D>,
    {
        <Self as Vshuff32x4MaskzEmitter<A, B, C, D>>::vshuff32x4_maskz(self, op0, op1, op2, op3);
    }
    /// `VSHUFF64X2`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshuff64x2<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshuff64x2Emitter<A, B, C, D>,
    {
        <Self as Vshuff64x2Emitter<A, B, C, D>>::vshuff64x2(self, op0, op1, op2, op3);
    }
    /// `VSHUFF64X2_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshuff64x2_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshuff64x2MaskEmitter<A, B, C, D>,
    {
        <Self as Vshuff64x2MaskEmitter<A, B, C, D>>::vshuff64x2_mask(self, op0, op1, op2, op3);
    }
    /// `VSHUFF64X2_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshuff64x2_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshuff64x2MaskzEmitter<A, B, C, D>,
    {
        <Self as Vshuff64x2MaskzEmitter<A, B, C, D>>::vshuff64x2_maskz(self, op0, op1, op2, op3);
    }
    /// `VSHUFI32X4`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufi32x4<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshufi32x4Emitter<A, B, C, D>,
    {
        <Self as Vshufi32x4Emitter<A, B, C, D>>::vshufi32x4(self, op0, op1, op2, op3);
    }
    /// `VSHUFI32X4_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufi32x4_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshufi32x4MaskEmitter<A, B, C, D>,
    {
        <Self as Vshufi32x4MaskEmitter<A, B, C, D>>::vshufi32x4_mask(self, op0, op1, op2, op3);
    }
    /// `VSHUFI32X4_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufi32x4_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshufi32x4MaskzEmitter<A, B, C, D>,
    {
        <Self as Vshufi32x4MaskzEmitter<A, B, C, D>>::vshufi32x4_maskz(self, op0, op1, op2, op3);
    }
    /// `VSHUFI64X2`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufi64x2<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshufi64x2Emitter<A, B, C, D>,
    {
        <Self as Vshufi64x2Emitter<A, B, C, D>>::vshufi64x2(self, op0, op1, op2, op3);
    }
    /// `VSHUFI64X2_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufi64x2_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshufi64x2MaskEmitter<A, B, C, D>,
    {
        <Self as Vshufi64x2MaskEmitter<A, B, C, D>>::vshufi64x2_mask(self, op0, op1, op2, op3);
    }
    /// `VSHUFI64X2_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Ymm, Ymm, Mem, Imm |
    /// | 2 | Ymm, Ymm, Ymm, Imm |
    /// | 3 | Zmm, Zmm, Mem, Imm |
    /// | 4 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufi64x2_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: Vshufi64x2MaskzEmitter<A, B, C, D>,
    {
        <Self as Vshufi64x2MaskzEmitter<A, B, C, D>>::vshufi64x2_maskz(self, op0, op1, op2, op3);
    }
    /// `VSHUFPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufpd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VshufpdEmitter<A, B, C, D>,
    {
        <Self as VshufpdEmitter<A, B, C, D>>::vshufpd(self, op0, op1, op2, op3);
    }
    /// `VSHUFPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufpd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VshufpdMaskEmitter<A, B, C, D>,
    {
        <Self as VshufpdMaskEmitter<A, B, C, D>>::vshufpd_mask(self, op0, op1, op2, op3);
    }
    /// `VSHUFPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufpd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VshufpdMaskzEmitter<A, B, C, D>,
    {
        <Self as VshufpdMaskzEmitter<A, B, C, D>>::vshufpd_maskz(self, op0, op1, op2, op3);
    }
    /// `VSHUFPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufps<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VshufpsEmitter<A, B, C, D>,
    {
        <Self as VshufpsEmitter<A, B, C, D>>::vshufps(self, op0, op1, op2, op3);
    }
    /// `VSHUFPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufps_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VshufpsMaskEmitter<A, B, C, D>,
    {
        <Self as VshufpsMaskEmitter<A, B, C, D>>::vshufps_mask(self, op0, op1, op2, op3);
    }
    /// `VSHUFPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+--------------------+
    /// | # | Operands           |
    /// +---+--------------------+
    /// | 1 | Xmm, Xmm, Mem, Imm |
    /// | 2 | Xmm, Xmm, Xmm, Imm |
    /// | 3 | Ymm, Ymm, Mem, Imm |
    /// | 4 | Ymm, Ymm, Ymm, Imm |
    /// | 5 | Zmm, Zmm, Mem, Imm |
    /// | 6 | Zmm, Zmm, Zmm, Imm |
    /// +---+--------------------+
    /// ```
    #[inline]
    pub fn vshufps_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
    where
        Assembler<'a>: VshufpsMaskzEmitter<A, B, C, D>,
    {
        <Self as VshufpsMaskzEmitter<A, B, C, D>>::vshufps_maskz(self, op0, op1, op2, op3);
    }
    /// `VSQRTPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtpd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpdEmitter<A, B>,
    {
        <Self as VsqrtpdEmitter<A, B>>::vsqrtpd(self, op0, op1);
    }
    /// `VSQRTPD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtpd_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpdErEmitter<A, B>,
    {
        <Self as VsqrtpdErEmitter<A, B>>::vsqrtpd_er(self, op0, op1);
    }
    /// `VSQRTPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtpd_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpdMaskEmitter<A, B>,
    {
        <Self as VsqrtpdMaskEmitter<A, B>>::vsqrtpd_mask(self, op0, op1);
    }
    /// `VSQRTPD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtpd_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpdMaskErEmitter<A, B>,
    {
        <Self as VsqrtpdMaskErEmitter<A, B>>::vsqrtpd_mask_er(self, op0, op1);
    }
    /// `VSQRTPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtpd_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpdMaskzEmitter<A, B>,
    {
        <Self as VsqrtpdMaskzEmitter<A, B>>::vsqrtpd_maskz(self, op0, op1);
    }
    /// `VSQRTPD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtpd_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpdMaskzErEmitter<A, B>,
    {
        <Self as VsqrtpdMaskzErEmitter<A, B>>::vsqrtpd_maskz_er(self, op0, op1);
    }
    /// `VSQRTPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtps<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpsEmitter<A, B>,
    {
        <Self as VsqrtpsEmitter<A, B>>::vsqrtps(self, op0, op1);
    }
    /// `VSQRTPS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtps_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpsErEmitter<A, B>,
    {
        <Self as VsqrtpsErEmitter<A, B>>::vsqrtps_er(self, op0, op1);
    }
    /// `VSQRTPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtps_mask<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpsMaskEmitter<A, B>,
    {
        <Self as VsqrtpsMaskEmitter<A, B>>::vsqrtps_mask(self, op0, op1);
    }
    /// `VSQRTPS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtps_mask_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpsMaskErEmitter<A, B>,
    {
        <Self as VsqrtpsMaskErEmitter<A, B>>::vsqrtps_mask_er(self, op0, op1);
    }
    /// `VSQRTPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// | 3 | Ymm, Mem |
    /// | 4 | Ymm, Ymm |
    /// | 5 | Zmm, Mem |
    /// | 6 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtps_maskz<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpsMaskzEmitter<A, B>,
    {
        <Self as VsqrtpsMaskzEmitter<A, B>>::vsqrtps_maskz(self, op0, op1);
    }
    /// `VSQRTPS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Zmm, Zmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vsqrtps_maskz_er<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VsqrtpsMaskzErEmitter<A, B>,
    {
        <Self as VsqrtpsMaskzErEmitter<A, B>>::vsqrtps_maskz_er(self, op0, op1);
    }
    /// `VSQRTSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtsdEmitter<A, B, C>,
    {
        <Self as VsqrtsdEmitter<A, B, C>>::vsqrtsd(self, op0, op1, op2);
    }
    /// `VSQRTSD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtsd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtsdErEmitter<A, B, C>,
    {
        <Self as VsqrtsdErEmitter<A, B, C>>::vsqrtsd_er(self, op0, op1, op2);
    }
    /// `VSQRTSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtsdMaskEmitter<A, B, C>,
    {
        <Self as VsqrtsdMaskEmitter<A, B, C>>::vsqrtsd_mask(self, op0, op1, op2);
    }
    /// `VSQRTSD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtsd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtsdMaskErEmitter<A, B, C>,
    {
        <Self as VsqrtsdMaskErEmitter<A, B, C>>::vsqrtsd_mask_er(self, op0, op1, op2);
    }
    /// `VSQRTSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtsdMaskzEmitter<A, B, C>,
    {
        <Self as VsqrtsdMaskzEmitter<A, B, C>>::vsqrtsd_maskz(self, op0, op1, op2);
    }
    /// `VSQRTSD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtsd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtsdMaskzErEmitter<A, B, C>,
    {
        <Self as VsqrtsdMaskzErEmitter<A, B, C>>::vsqrtsd_maskz_er(self, op0, op1, op2);
    }
    /// `VSQRTSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtssEmitter<A, B, C>,
    {
        <Self as VsqrtssEmitter<A, B, C>>::vsqrtss(self, op0, op1, op2);
    }
    /// `VSQRTSS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtssErEmitter<A, B, C>,
    {
        <Self as VsqrtssErEmitter<A, B, C>>::vsqrtss_er(self, op0, op1, op2);
    }
    /// `VSQRTSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtssMaskEmitter<A, B, C>,
    {
        <Self as VsqrtssMaskEmitter<A, B, C>>::vsqrtss_mask(self, op0, op1, op2);
    }
    /// `VSQRTSS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtssMaskErEmitter<A, B, C>,
    {
        <Self as VsqrtssMaskErEmitter<A, B, C>>::vsqrtss_mask_er(self, op0, op1, op2);
    }
    /// `VSQRTSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtssMaskzEmitter<A, B, C>,
    {
        <Self as VsqrtssMaskzEmitter<A, B, C>>::vsqrtss_maskz(self, op0, op1, op2);
    }
    /// `VSQRTSS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsqrtss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsqrtssMaskzErEmitter<A, B, C>,
    {
        <Self as VsqrtssMaskzErEmitter<A, B, C>>::vsqrtss_maskz_er(self, op0, op1, op2);
    }
    /// `VSUBPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpdEmitter<A, B, C>,
    {
        <Self as VsubpdEmitter<A, B, C>>::vsubpd(self, op0, op1, op2);
    }
    /// `VSUBPD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubpd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpdErEmitter<A, B, C>,
    {
        <Self as VsubpdErEmitter<A, B, C>>::vsubpd_er(self, op0, op1, op2);
    }
    /// `VSUBPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpdMaskEmitter<A, B, C>,
    {
        <Self as VsubpdMaskEmitter<A, B, C>>::vsubpd_mask(self, op0, op1, op2);
    }
    /// `VSUBPD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubpd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpdMaskErEmitter<A, B, C>,
    {
        <Self as VsubpdMaskErEmitter<A, B, C>>::vsubpd_mask_er(self, op0, op1, op2);
    }
    /// `VSUBPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpdMaskzEmitter<A, B, C>,
    {
        <Self as VsubpdMaskzEmitter<A, B, C>>::vsubpd_maskz(self, op0, op1, op2);
    }
    /// `VSUBPD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubpd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpdMaskzErEmitter<A, B, C>,
    {
        <Self as VsubpdMaskzErEmitter<A, B, C>>::vsubpd_maskz_er(self, op0, op1, op2);
    }
    /// `VSUBPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpsEmitter<A, B, C>,
    {
        <Self as VsubpsEmitter<A, B, C>>::vsubps(self, op0, op1, op2);
    }
    /// `VSUBPS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubps_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpsErEmitter<A, B, C>,
    {
        <Self as VsubpsErEmitter<A, B, C>>::vsubps_er(self, op0, op1, op2);
    }
    /// `VSUBPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpsMaskEmitter<A, B, C>,
    {
        <Self as VsubpsMaskEmitter<A, B, C>>::vsubps_mask(self, op0, op1, op2);
    }
    /// `VSUBPS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubps_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpsMaskErEmitter<A, B, C>,
    {
        <Self as VsubpsMaskErEmitter<A, B, C>>::vsubps_mask_er(self, op0, op1, op2);
    }
    /// `VSUBPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpsMaskzEmitter<A, B, C>,
    {
        <Self as VsubpsMaskzEmitter<A, B, C>>::vsubps_maskz(self, op0, op1, op2);
    }
    /// `VSUBPS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubps_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubpsMaskzErEmitter<A, B, C>,
    {
        <Self as VsubpsMaskzErEmitter<A, B, C>>::vsubps_maskz_er(self, op0, op1, op2);
    }
    /// `VSUBSD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubsd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubsdEmitter<A, B, C>,
    {
        <Self as VsubsdEmitter<A, B, C>>::vsubsd(self, op0, op1, op2);
    }
    /// `VSUBSD_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubsd_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubsdErEmitter<A, B, C>,
    {
        <Self as VsubsdErEmitter<A, B, C>>::vsubsd_er(self, op0, op1, op2);
    }
    /// `VSUBSD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubsd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubsdMaskEmitter<A, B, C>,
    {
        <Self as VsubsdMaskEmitter<A, B, C>>::vsubsd_mask(self, op0, op1, op2);
    }
    /// `VSUBSD_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubsd_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubsdMaskErEmitter<A, B, C>,
    {
        <Self as VsubsdMaskErEmitter<A, B, C>>::vsubsd_mask_er(self, op0, op1, op2);
    }
    /// `VSUBSD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubsd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubsdMaskzEmitter<A, B, C>,
    {
        <Self as VsubsdMaskzEmitter<A, B, C>>::vsubsd_maskz(self, op0, op1, op2);
    }
    /// `VSUBSD_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubsd_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubsdMaskzErEmitter<A, B, C>,
    {
        <Self as VsubsdMaskzErEmitter<A, B, C>>::vsubsd_maskz_er(self, op0, op1, op2);
    }
    /// `VSUBSS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubss<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubssEmitter<A, B, C>,
    {
        <Self as VsubssEmitter<A, B, C>>::vsubss(self, op0, op1, op2);
    }
    /// `VSUBSS_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubss_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubssErEmitter<A, B, C>,
    {
        <Self as VsubssErEmitter<A, B, C>>::vsubss_er(self, op0, op1, op2);
    }
    /// `VSUBSS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubss_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubssMaskEmitter<A, B, C>,
    {
        <Self as VsubssMaskEmitter<A, B, C>>::vsubss_mask(self, op0, op1, op2);
    }
    /// `VSUBSS_MASK_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubss_mask_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubssMaskErEmitter<A, B, C>,
    {
        <Self as VsubssMaskErEmitter<A, B, C>>::vsubss_mask_er(self, op0, op1, op2);
    }
    /// `VSUBSS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubss_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubssMaskzEmitter<A, B, C>,
    {
        <Self as VsubssMaskzEmitter<A, B, C>>::vsubss_maskz(self, op0, op1, op2);
    }
    /// `VSUBSS_MASKZ_ER`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Xmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vsubss_maskz_er<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VsubssMaskzErEmitter<A, B, C>,
    {
        <Self as VsubssMaskzErEmitter<A, B, C>>::vsubss_maskz_er(self, op0, op1, op2);
    }
    /// `VUCOMISD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vucomisd<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VucomisdEmitter<A, B>,
    {
        <Self as VucomisdEmitter<A, B>>::vucomisd(self, op0, op1);
    }
    /// `VUCOMISD_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vucomisd_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VucomisdSaeEmitter<A, B>,
    {
        <Self as VucomisdSaeEmitter<A, B>>::vucomisd_sae(self, op0, op1);
    }
    /// `VUCOMISS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Mem |
    /// | 2 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vucomiss<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VucomissEmitter<A, B>,
    {
        <Self as VucomissEmitter<A, B>>::vucomiss(self, op0, op1);
    }
    /// `VUCOMISS_SAE`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+----------+
    /// | # | Operands |
    /// +---+----------+
    /// | 1 | Xmm, Xmm |
    /// +---+----------+
    /// ```
    #[inline]
    pub fn vucomiss_sae<A, B>(&mut self, op0: A, op1: B)
    where
        Assembler<'a>: VucomissSaeEmitter<A, B>,
    {
        <Self as VucomissSaeEmitter<A, B>>::vucomiss_sae(self, op0, op1);
    }
    /// `VUNPCKHPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpckhpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpckhpdEmitter<A, B, C>,
    {
        <Self as VunpckhpdEmitter<A, B, C>>::vunpckhpd(self, op0, op1, op2);
    }
    /// `VUNPCKHPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpckhpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpckhpdMaskEmitter<A, B, C>,
    {
        <Self as VunpckhpdMaskEmitter<A, B, C>>::vunpckhpd_mask(self, op0, op1, op2);
    }
    /// `VUNPCKHPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpckhpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpckhpdMaskzEmitter<A, B, C>,
    {
        <Self as VunpckhpdMaskzEmitter<A, B, C>>::vunpckhpd_maskz(self, op0, op1, op2);
    }
    /// `VUNPCKHPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpckhps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpckhpsEmitter<A, B, C>,
    {
        <Self as VunpckhpsEmitter<A, B, C>>::vunpckhps(self, op0, op1, op2);
    }
    /// `VUNPCKHPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpckhps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpckhpsMaskEmitter<A, B, C>,
    {
        <Self as VunpckhpsMaskEmitter<A, B, C>>::vunpckhps_mask(self, op0, op1, op2);
    }
    /// `VUNPCKHPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpckhps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpckhpsMaskzEmitter<A, B, C>,
    {
        <Self as VunpckhpsMaskzEmitter<A, B, C>>::vunpckhps_maskz(self, op0, op1, op2);
    }
    /// `VUNPCKLPD`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpcklpd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpcklpdEmitter<A, B, C>,
    {
        <Self as VunpcklpdEmitter<A, B, C>>::vunpcklpd(self, op0, op1, op2);
    }
    /// `VUNPCKLPD_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpcklpd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpcklpdMaskEmitter<A, B, C>,
    {
        <Self as VunpcklpdMaskEmitter<A, B, C>>::vunpcklpd_mask(self, op0, op1, op2);
    }
    /// `VUNPCKLPD_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpcklpd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpcklpdMaskzEmitter<A, B, C>,
    {
        <Self as VunpcklpdMaskzEmitter<A, B, C>>::vunpcklpd_maskz(self, op0, op1, op2);
    }
    /// `VUNPCKLPS`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpcklps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpcklpsEmitter<A, B, C>,
    {
        <Self as VunpcklpsEmitter<A, B, C>>::vunpcklps(self, op0, op1, op2);
    }
    /// `VUNPCKLPS_MASK`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpcklps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpcklpsMaskEmitter<A, B, C>,
    {
        <Self as VunpcklpsMaskEmitter<A, B, C>>::vunpcklps_mask(self, op0, op1, op2);
    }
    /// `VUNPCKLPS_MASKZ`.
    ///
    /// Supported operand variants:
    ///
    /// ```text
    /// +---+---------------+
    /// | # | Operands      |
    /// +---+---------------+
    /// | 1 | Xmm, Xmm, Mem |
    /// | 2 | Xmm, Xmm, Xmm |
    /// | 3 | Ymm, Ymm, Mem |
    /// | 4 | Ymm, Ymm, Ymm |
    /// | 5 | Zmm, Zmm, Mem |
    /// | 6 | Zmm, Zmm, Zmm |
    /// +---+---------------+
    /// ```
    #[inline]
    pub fn vunpcklps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
    where
        Assembler<'a>: VunpcklpsMaskzEmitter<A, B, C>,
    {
        <Self as VunpcklpsMaskzEmitter<A, B, C>>::vunpcklps_maskz(self, op0, op1, op2);
    }
}
