#[doc = "Register `DPLLCTRLB` reader"]
pub type R = crate::R<DpllctrlbSpec>;
#[doc = "Register `DPLLCTRLB` writer"]
pub type W = crate::W<DpllctrlbSpec>;
#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"]
pub type FilterR = crate::FieldReader;
#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"]
pub type FilterW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `LPEN` reader - Low-Power Enable"]
pub type LpenR = crate::BitReader;
#[doc = "Field `LPEN` writer - Low-Power Enable"]
pub type LpenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WUF` reader - Wake Up Fast"]
pub type WufR = crate::BitReader;
#[doc = "Field `WUF` writer - Wake Up Fast"]
pub type WufW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFCLK` reader - Reference Clock Selection"]
pub type RefclkR = crate::FieldReader;
#[doc = "Field `REFCLK` writer - Reference Clock Selection"]
pub type RefclkW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `LTIME` reader - Lock Time"]
pub type LtimeR = crate::FieldReader;
#[doc = "Field `LTIME` writer - Lock Time"]
pub type LtimeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `LBYPASS` reader - Lock Bypass"]
pub type LbypassR = crate::BitReader;
#[doc = "Field `LBYPASS` writer - Lock Bypass"]
pub type LbypassW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIV` reader - Clock Divider"]
pub type DivR = crate::FieldReader<u16>;
#[doc = "Field `DIV` writer - Clock Divider"]
pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
    #[doc = "Bits 0:1 - Proportional Integral Filter Selection"]
    #[inline(always)]
    pub fn filter(&self) -> FilterR {
        FilterR::new((self.bits & 3) as u8)
    }
    #[doc = "Bit 2 - Low-Power Enable"]
    #[inline(always)]
    pub fn lpen(&self) -> LpenR {
        LpenR::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Wake Up Fast"]
    #[inline(always)]
    pub fn wuf(&self) -> WufR {
        WufR::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bits 4:5 - Reference Clock Selection"]
    #[inline(always)]
    pub fn refclk(&self) -> RefclkR {
        RefclkR::new(((self.bits >> 4) & 3) as u8)
    }
    #[doc = "Bits 8:10 - Lock Time"]
    #[inline(always)]
    pub fn ltime(&self) -> LtimeR {
        LtimeR::new(((self.bits >> 8) & 7) as u8)
    }
    #[doc = "Bit 12 - Lock Bypass"]
    #[inline(always)]
    pub fn lbypass(&self) -> LbypassR {
        LbypassR::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bits 16:26 - Clock Divider"]
    #[inline(always)]
    pub fn div(&self) -> DivR {
        DivR::new(((self.bits >> 16) & 0x07ff) as u16)
    }
}
impl W {
    #[doc = "Bits 0:1 - Proportional Integral Filter Selection"]
    #[inline(always)]
    pub fn filter(&mut self) -> FilterW<DpllctrlbSpec> {
        FilterW::new(self, 0)
    }
    #[doc = "Bit 2 - Low-Power Enable"]
    #[inline(always)]
    pub fn lpen(&mut self) -> LpenW<DpllctrlbSpec> {
        LpenW::new(self, 2)
    }
    #[doc = "Bit 3 - Wake Up Fast"]
    #[inline(always)]
    pub fn wuf(&mut self) -> WufW<DpllctrlbSpec> {
        WufW::new(self, 3)
    }
    #[doc = "Bits 4:5 - Reference Clock Selection"]
    #[inline(always)]
    pub fn refclk(&mut self) -> RefclkW<DpllctrlbSpec> {
        RefclkW::new(self, 4)
    }
    #[doc = "Bits 8:10 - Lock Time"]
    #[inline(always)]
    pub fn ltime(&mut self) -> LtimeW<DpllctrlbSpec> {
        LtimeW::new(self, 8)
    }
    #[doc = "Bit 12 - Lock Bypass"]
    #[inline(always)]
    pub fn lbypass(&mut self) -> LbypassW<DpllctrlbSpec> {
        LbypassW::new(self, 12)
    }
    #[doc = "Bits 16:26 - Clock Divider"]
    #[inline(always)]
    pub fn div(&mut self) -> DivW<DpllctrlbSpec> {
        DivW::new(self, 16)
    }
}
#[doc = "Digital Core Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`dpllctrlb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpllctrlb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DpllctrlbSpec;
impl crate::RegisterSpec for DpllctrlbSpec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`dpllctrlb::R`](R) reader structure"]
impl crate::Readable for DpllctrlbSpec {}
#[doc = "`write(|w| ..)` method takes [`dpllctrlb::W`](W) writer structure"]
impl crate::Writable for DpllctrlbSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DPLLCTRLB to value 0"]
impl crate::Resettable for DpllctrlbSpec {
    const RESET_VALUE: u32 = 0;
}
