#[doc = "Register `INTENCLR` reader"]
pub type R = crate::R<IntenclrSpec>;
#[doc = "Register `INTENCLR` writer"]
pub type W = crate::W<IntenclrSpec>;
#[doc = "Field `FC0O` reader - Frame Counter 0 Overflow Interrupt Disable"]
pub type Fc0oR = crate::BitReader;
#[doc = "Field `FC0O` writer - Frame Counter 0 Overflow Interrupt Disable"]
pub type Fc0oW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FC1O` reader - Frame Counter 1 Overflow Interrupt Disable"]
pub type Fc1oR = crate::BitReader;
#[doc = "Field `FC1O` writer - Frame Counter 1 Overflow Interrupt Disable"]
pub type Fc1oW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FC2O` reader - Frame Counter 2 Overflow Interrupt Disable"]
pub type Fc2oR = crate::BitReader;
#[doc = "Field `FC2O` writer - Frame Counter 2 Overflow Interrupt Disable"]
pub type Fc2oW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VLCDRT` reader - VLCD Ready Toggle Interrupt Disable"]
pub type VlcdrtR = crate::BitReader;
#[doc = "Field `VLCDRT` writer - VLCD Ready Toggle Interrupt Disable"]
pub type VlcdrtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VLCDST` reader - VLCD Status Toggle Interrupt Disable"]
pub type VlcdstR = crate::BitReader;
#[doc = "Field `VLCDST` writer - VLCD Status Toggle Interrupt Disable"]
pub type VlcdstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PRST` reader - Pump Run Status Toggle Interrupt Disable"]
pub type PrstR = crate::BitReader;
#[doc = "Field `PRST` writer - Pump Run Status Toggle Interrupt Disable"]
pub type PrstW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - Frame Counter 0 Overflow Interrupt Disable"]
    #[inline(always)]
    pub fn fc0o(&self) -> Fc0oR {
        Fc0oR::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Frame Counter 1 Overflow Interrupt Disable"]
    #[inline(always)]
    pub fn fc1o(&self) -> Fc1oR {
        Fc1oR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Frame Counter 2 Overflow Interrupt Disable"]
    #[inline(always)]
    pub fn fc2o(&self) -> Fc2oR {
        Fc2oR::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - VLCD Ready Toggle Interrupt Disable"]
    #[inline(always)]
    pub fn vlcdrt(&self) -> VlcdrtR {
        VlcdrtR::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - VLCD Status Toggle Interrupt Disable"]
    #[inline(always)]
    pub fn vlcdst(&self) -> VlcdstR {
        VlcdstR::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Pump Run Status Toggle Interrupt Disable"]
    #[inline(always)]
    pub fn prst(&self) -> PrstR {
        PrstR::new(((self.bits >> 5) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Frame Counter 0 Overflow Interrupt Disable"]
    #[inline(always)]
    pub fn fc0o(&mut self) -> Fc0oW<IntenclrSpec> {
        Fc0oW::new(self, 0)
    }
    #[doc = "Bit 1 - Frame Counter 1 Overflow Interrupt Disable"]
    #[inline(always)]
    pub fn fc1o(&mut self) -> Fc1oW<IntenclrSpec> {
        Fc1oW::new(self, 1)
    }
    #[doc = "Bit 2 - Frame Counter 2 Overflow Interrupt Disable"]
    #[inline(always)]
    pub fn fc2o(&mut self) -> Fc2oW<IntenclrSpec> {
        Fc2oW::new(self, 2)
    }
    #[doc = "Bit 3 - VLCD Ready Toggle Interrupt Disable"]
    #[inline(always)]
    pub fn vlcdrt(&mut self) -> VlcdrtW<IntenclrSpec> {
        VlcdrtW::new(self, 3)
    }
    #[doc = "Bit 4 - VLCD Status Toggle Interrupt Disable"]
    #[inline(always)]
    pub fn vlcdst(&mut self) -> VlcdstW<IntenclrSpec> {
        VlcdstW::new(self, 4)
    }
    #[doc = "Bit 5 - Pump Run Status Toggle Interrupt Disable"]
    #[inline(always)]
    pub fn prst(&mut self) -> PrstW<IntenclrSpec> {
        PrstW::new(self, 5)
    }
}
#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntenclrSpec;
impl crate::RegisterSpec for IntenclrSpec {
    type Ux = u8;
}
#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
impl crate::Readable for IntenclrSpec {}
#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
impl crate::Writable for IntenclrSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
}
#[doc = "`reset()` method sets INTENCLR to value 0"]
impl crate::Resettable for IntenclrSpec {
    const RESET_VALUE: u8 = 0;
}
