#[doc = "Register `OSC16MCTRL` reader"]
pub type R = crate::R<Osc16mctrlSpec>;
#[doc = "Register `OSC16MCTRL` writer"]
pub type W = crate::W<Osc16mctrlSpec>;
#[doc = "Field `ENABLE` reader - Oscillator Enable"]
pub type EnableR = crate::BitReader;
#[doc = "Field `ENABLE` writer - Oscillator Enable"]
pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Oscillator Frequency Select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Fselselect {
    #[doc = "0: 4MHz"]
    _4 = 0,
    #[doc = "1: 8MHz"]
    _8 = 1,
    #[doc = "2: 12MHz"]
    _12 = 2,
    #[doc = "3: 16MHz"]
    _16 = 3,
}
impl From<Fselselect> for u8 {
    #[inline(always)]
    fn from(variant: Fselselect) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for Fselselect {
    type Ux = u8;
}
impl crate::IsEnum for Fselselect {}
#[doc = "Field `FSEL` reader - Oscillator Frequency Select"]
pub type FselR = crate::FieldReader<Fselselect>;
impl FselR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Fselselect {
        match self.bits {
            0 => Fselselect::_4,
            1 => Fselselect::_8,
            2 => Fselselect::_12,
            3 => Fselselect::_16,
            _ => unreachable!(),
        }
    }
    #[doc = "4MHz"]
    #[inline(always)]
    pub fn is_4(&self) -> bool {
        *self == Fselselect::_4
    }
    #[doc = "8MHz"]
    #[inline(always)]
    pub fn is_8(&self) -> bool {
        *self == Fselselect::_8
    }
    #[doc = "12MHz"]
    #[inline(always)]
    pub fn is_12(&self) -> bool {
        *self == Fselselect::_12
    }
    #[doc = "16MHz"]
    #[inline(always)]
    pub fn is_16(&self) -> bool {
        *self == Fselselect::_16
    }
}
#[doc = "Field `FSEL` writer - Oscillator Frequency Select"]
pub type FselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Fselselect, crate::Safe>;
impl<'a, REG> FselW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    #[doc = "4MHz"]
    #[inline(always)]
    pub fn _4(self) -> &'a mut crate::W<REG> {
        self.variant(Fselselect::_4)
    }
    #[doc = "8MHz"]
    #[inline(always)]
    pub fn _8(self) -> &'a mut crate::W<REG> {
        self.variant(Fselselect::_8)
    }
    #[doc = "12MHz"]
    #[inline(always)]
    pub fn _12(self) -> &'a mut crate::W<REG> {
        self.variant(Fselselect::_12)
    }
    #[doc = "16MHz"]
    #[inline(always)]
    pub fn _16(self) -> &'a mut crate::W<REG> {
        self.variant(Fselselect::_16)
    }
}
#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
pub type RunstdbyR = crate::BitReader;
#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ONDEMAND` reader - On Demand Control"]
pub type OndemandR = crate::BitReader;
#[doc = "Field `ONDEMAND` writer - On Demand Control"]
pub type OndemandW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 1 - Oscillator Enable"]
    #[inline(always)]
    pub fn enable(&self) -> EnableR {
        EnableR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bits 2:3 - Oscillator Frequency Select"]
    #[inline(always)]
    pub fn fsel(&self) -> FselR {
        FselR::new((self.bits >> 2) & 3)
    }
    #[doc = "Bit 6 - Run in Standby"]
    #[inline(always)]
    pub fn runstdby(&self) -> RunstdbyR {
        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7 - On Demand Control"]
    #[inline(always)]
    pub fn ondemand(&self) -> OndemandR {
        OndemandR::new(((self.bits >> 7) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 1 - Oscillator Enable"]
    #[inline(always)]
    pub fn enable(&mut self) -> EnableW<Osc16mctrlSpec> {
        EnableW::new(self, 1)
    }
    #[doc = "Bits 2:3 - Oscillator Frequency Select"]
    #[inline(always)]
    pub fn fsel(&mut self) -> FselW<Osc16mctrlSpec> {
        FselW::new(self, 2)
    }
    #[doc = "Bit 6 - Run in Standby"]
    #[inline(always)]
    pub fn runstdby(&mut self) -> RunstdbyW<Osc16mctrlSpec> {
        RunstdbyW::new(self, 6)
    }
    #[doc = "Bit 7 - On Demand Control"]
    #[inline(always)]
    pub fn ondemand(&mut self) -> OndemandW<Osc16mctrlSpec> {
        OndemandW::new(self, 7)
    }
}
#[doc = "16MHz Internal Oscillator (OSC16M) Control\n\nYou can [`read`](crate::Reg::read) this register and get [`osc16mctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osc16mctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Osc16mctrlSpec;
impl crate::RegisterSpec for Osc16mctrlSpec {
    type Ux = u8;
}
#[doc = "`read()` method returns [`osc16mctrl::R`](R) reader structure"]
impl crate::Readable for Osc16mctrlSpec {}
#[doc = "`write(|w| ..)` method takes [`osc16mctrl::W`](W) writer structure"]
impl crate::Writable for Osc16mctrlSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
}
#[doc = "`reset()` method sets OSC16MCTRL to value 0x82"]
impl crate::Resettable for Osc16mctrlSpec {
    const RESET_VALUE: u8 = 0x82;
}
