#[doc = "Register `INTENCLR` reader"]
pub type R = crate::R<IntenclrSpec>;
#[doc = "Register `INTENCLR` writer"]
pub type W = crate::W<IntenclrSpec>;
#[doc = "Field `BOD33RDY` reader - BOD33 Ready"]
pub type Bod33rdyR = crate::BitReader;
#[doc = "Field `BOD33RDY` writer - BOD33 Ready"]
pub type Bod33rdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BOD33DET` reader - BOD33 Detection"]
pub type Bod33detR = crate::BitReader;
#[doc = "Field `BOD33DET` writer - BOD33 Detection"]
pub type Bod33detW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"]
pub type B33srdyR = crate::BitReader;
#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready"]
pub type B33srdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BOD12RDY` reader - BOD12 Ready"]
pub type Bod12rdyR = crate::BitReader;
#[doc = "Field `BOD12RDY` writer - BOD12 Ready"]
pub type Bod12rdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BOD12DET` reader - BOD12 Detection"]
pub type Bod12detR = crate::BitReader;
#[doc = "Field `BOD12DET` writer - BOD12 Detection"]
pub type Bod12detW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `B12SRDY` reader - BOD12 Synchronization Ready"]
pub type B12srdyR = crate::BitReader;
#[doc = "Field `B12SRDY` writer - BOD12 Synchronization Ready"]
pub type B12srdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VREGRDY` reader - Voltage Regulator Ready"]
pub type VregrdyR = crate::BitReader;
#[doc = "Field `VREGRDY` writer - Voltage Regulator Ready"]
pub type VregrdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APWSRDY` reader - Automatic Power Switch Ready"]
pub type ApwsrdyR = crate::BitReader;
#[doc = "Field `APWSRDY` writer - Automatic Power Switch Ready"]
pub type ApwsrdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VCORERDY` reader - VDDCORE Ready"]
pub type VcorerdyR = crate::BitReader;
#[doc = "Field `VCORERDY` writer - VDDCORE Ready"]
pub type VcorerdyW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - BOD33 Ready"]
    #[inline(always)]
    pub fn bod33rdy(&self) -> Bod33rdyR {
        Bod33rdyR::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - BOD33 Detection"]
    #[inline(always)]
    pub fn bod33det(&self) -> Bod33detR {
        Bod33detR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - BOD33 Synchronization Ready"]
    #[inline(always)]
    pub fn b33srdy(&self) -> B33srdyR {
        B33srdyR::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - BOD12 Ready"]
    #[inline(always)]
    pub fn bod12rdy(&self) -> Bod12rdyR {
        Bod12rdyR::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - BOD12 Detection"]
    #[inline(always)]
    pub fn bod12det(&self) -> Bod12detR {
        Bod12detR::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - BOD12 Synchronization Ready"]
    #[inline(always)]
    pub fn b12srdy(&self) -> B12srdyR {
        B12srdyR::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 8 - Voltage Regulator Ready"]
    #[inline(always)]
    pub fn vregrdy(&self) -> VregrdyR {
        VregrdyR::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 9 - Automatic Power Switch Ready"]
    #[inline(always)]
    pub fn apwsrdy(&self) -> ApwsrdyR {
        ApwsrdyR::new(((self.bits >> 9) & 1) != 0)
    }
    #[doc = "Bit 10 - VDDCORE Ready"]
    #[inline(always)]
    pub fn vcorerdy(&self) -> VcorerdyR {
        VcorerdyR::new(((self.bits >> 10) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - BOD33 Ready"]
    #[inline(always)]
    pub fn bod33rdy(&mut self) -> Bod33rdyW<IntenclrSpec> {
        Bod33rdyW::new(self, 0)
    }
    #[doc = "Bit 1 - BOD33 Detection"]
    #[inline(always)]
    pub fn bod33det(&mut self) -> Bod33detW<IntenclrSpec> {
        Bod33detW::new(self, 1)
    }
    #[doc = "Bit 2 - BOD33 Synchronization Ready"]
    #[inline(always)]
    pub fn b33srdy(&mut self) -> B33srdyW<IntenclrSpec> {
        B33srdyW::new(self, 2)
    }
    #[doc = "Bit 3 - BOD12 Ready"]
    #[inline(always)]
    pub fn bod12rdy(&mut self) -> Bod12rdyW<IntenclrSpec> {
        Bod12rdyW::new(self, 3)
    }
    #[doc = "Bit 4 - BOD12 Detection"]
    #[inline(always)]
    pub fn bod12det(&mut self) -> Bod12detW<IntenclrSpec> {
        Bod12detW::new(self, 4)
    }
    #[doc = "Bit 5 - BOD12 Synchronization Ready"]
    #[inline(always)]
    pub fn b12srdy(&mut self) -> B12srdyW<IntenclrSpec> {
        B12srdyW::new(self, 5)
    }
    #[doc = "Bit 8 - Voltage Regulator Ready"]
    #[inline(always)]
    pub fn vregrdy(&mut self) -> VregrdyW<IntenclrSpec> {
        VregrdyW::new(self, 8)
    }
    #[doc = "Bit 9 - Automatic Power Switch Ready"]
    #[inline(always)]
    pub fn apwsrdy(&mut self) -> ApwsrdyW<IntenclrSpec> {
        ApwsrdyW::new(self, 9)
    }
    #[doc = "Bit 10 - VDDCORE Ready"]
    #[inline(always)]
    pub fn vcorerdy(&mut self) -> VcorerdyW<IntenclrSpec> {
        VcorerdyW::new(self, 10)
    }
}
#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntenclrSpec;
impl crate::RegisterSpec for IntenclrSpec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
impl crate::Readable for IntenclrSpec {}
#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
impl crate::Writable for IntenclrSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTENCLR to value 0"]
impl crate::Resettable for IntenclrSpec {
    const RESET_VALUE: u32 = 0;
}
