#[doc = "Register `VREG` reader"]
pub type R = crate::R<VregSpec>;
#[doc = "Register `VREG` writer"]
pub type W = crate::W<VregSpec>;
#[doc = "Field `ENABLE` reader - Enable"]
pub type EnableR = crate::BitReader;
#[doc = "Field `ENABLE` writer - Enable"]
pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Voltage Regulator Selection in active mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Selselect {
    #[doc = "0: LDO selection"]
    Ldo = 0,
    #[doc = "1: Buck selection"]
    Buck = 1,
    #[doc = "2: Switched Cap selection"]
    Scvreg = 2,
}
impl From<Selselect> for u8 {
    #[inline(always)]
    fn from(variant: Selselect) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for Selselect {
    type Ux = u8;
}
impl crate::IsEnum for Selselect {}
#[doc = "Field `SEL` reader - Voltage Regulator Selection in active mode"]
pub type SelR = crate::FieldReader<Selselect>;
impl SelR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Option<Selselect> {
        match self.bits {
            0 => Some(Selselect::Ldo),
            1 => Some(Selselect::Buck),
            2 => Some(Selselect::Scvreg),
            _ => None,
        }
    }
    #[doc = "LDO selection"]
    #[inline(always)]
    pub fn is_ldo(&self) -> bool {
        *self == Selselect::Ldo
    }
    #[doc = "Buck selection"]
    #[inline(always)]
    pub fn is_buck(&self) -> bool {
        *self == Selselect::Buck
    }
    #[doc = "Switched Cap selection"]
    #[inline(always)]
    pub fn is_scvreg(&self) -> bool {
        *self == Selselect::Scvreg
    }
}
#[doc = "Field `SEL` writer - Voltage Regulator Selection in active mode"]
pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 2, Selselect>;
impl<'a, REG> SelW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    #[doc = "LDO selection"]
    #[inline(always)]
    pub fn ldo(self) -> &'a mut crate::W<REG> {
        self.variant(Selselect::Ldo)
    }
    #[doc = "Buck selection"]
    #[inline(always)]
    pub fn buck(self) -> &'a mut crate::W<REG> {
        self.variant(Selselect::Buck)
    }
    #[doc = "Switched Cap selection"]
    #[inline(always)]
    pub fn scvreg(self) -> &'a mut crate::W<REG> {
        self.variant(Selselect::Scvreg)
    }
}
#[doc = "Field `STDBYPL0` reader - Standby in PL0"]
pub type Stdbypl0R = crate::BitReader;
#[doc = "Field `STDBYPL0` writer - Standby in PL0"]
pub type Stdbypl0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RUNSTDBY` reader - Run during Standby"]
pub type RunstdbyR = crate::BitReader;
#[doc = "Field `RUNSTDBY` writer - Run during Standby"]
pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LPEFF` reader - Low Power efficiency"]
pub type LpeffR = crate::BitReader;
#[doc = "Field `LPEFF` writer - Low Power efficiency"]
pub type LpeffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VSVSTEP` reader - Voltage Scaling Voltage Step"]
pub type VsvstepR = crate::FieldReader;
#[doc = "Field `VSVSTEP` writer - Voltage Scaling Voltage Step"]
pub type VsvstepW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `VSPER` reader - Voltage Scaling Period"]
pub type VsperR = crate::FieldReader;
#[doc = "Field `VSPER` writer - Voltage Scaling Period"]
pub type VsperW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
    #[doc = "Bit 1 - Enable"]
    #[inline(always)]
    pub fn enable(&self) -> EnableR {
        EnableR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bits 2:3 - Voltage Regulator Selection in active mode"]
    #[inline(always)]
    pub fn sel(&self) -> SelR {
        SelR::new(((self.bits >> 2) & 3) as u8)
    }
    #[doc = "Bit 5 - Standby in PL0"]
    #[inline(always)]
    pub fn stdbypl0(&self) -> Stdbypl0R {
        Stdbypl0R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Run during Standby"]
    #[inline(always)]
    pub fn runstdby(&self) -> RunstdbyR {
        RunstdbyR::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 8 - Low Power efficiency"]
    #[inline(always)]
    pub fn lpeff(&self) -> LpeffR {
        LpeffR::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bits 16:19 - Voltage Scaling Voltage Step"]
    #[inline(always)]
    pub fn vsvstep(&self) -> VsvstepR {
        VsvstepR::new(((self.bits >> 16) & 0x0f) as u8)
    }
    #[doc = "Bits 24:31 - Voltage Scaling Period"]
    #[inline(always)]
    pub fn vsper(&self) -> VsperR {
        VsperR::new(((self.bits >> 24) & 0xff) as u8)
    }
}
impl W {
    #[doc = "Bit 1 - Enable"]
    #[inline(always)]
    pub fn enable(&mut self) -> EnableW<VregSpec> {
        EnableW::new(self, 1)
    }
    #[doc = "Bits 2:3 - Voltage Regulator Selection in active mode"]
    #[inline(always)]
    pub fn sel(&mut self) -> SelW<VregSpec> {
        SelW::new(self, 2)
    }
    #[doc = "Bit 5 - Standby in PL0"]
    #[inline(always)]
    pub fn stdbypl0(&mut self) -> Stdbypl0W<VregSpec> {
        Stdbypl0W::new(self, 5)
    }
    #[doc = "Bit 6 - Run during Standby"]
    #[inline(always)]
    pub fn runstdby(&mut self) -> RunstdbyW<VregSpec> {
        RunstdbyW::new(self, 6)
    }
    #[doc = "Bit 8 - Low Power efficiency"]
    #[inline(always)]
    pub fn lpeff(&mut self) -> LpeffW<VregSpec> {
        LpeffW::new(self, 8)
    }
    #[doc = "Bits 16:19 - Voltage Scaling Voltage Step"]
    #[inline(always)]
    pub fn vsvstep(&mut self) -> VsvstepW<VregSpec> {
        VsvstepW::new(self, 16)
    }
    #[doc = "Bits 24:31 - Voltage Scaling Period"]
    #[inline(always)]
    pub fn vsper(&mut self) -> VsperW<VregSpec> {
        VsperW::new(self, 24)
    }
}
#[doc = "VREG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`vreg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct VregSpec;
impl crate::RegisterSpec for VregSpec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`vreg::R`](R) reader structure"]
impl crate::Readable for VregSpec {}
#[doc = "`write(|w| ..)` method takes [`vreg::W`](W) writer structure"]
impl crate::Writable for VregSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets VREG to value 0"]
impl crate::Resettable for VregSpec {
    const RESET_VALUE: u32 = 0;
}
