<?xml version="1.0" encoding="UTF-8"?>
<avr-tools-device-file xmlns:xalan="http://xml.apache.org/xalan" xmlns:NumHelper="NumHelper" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
  <variants>
    <variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="2.1" vccmax="4.2"/>
  </variants>
  <devices>
    <device name="ATA5700M322" architecture="AVR8" family="megaAVR">
      <address-spaces>
        <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0x10000">
          <memory-segment start="0x0000" size="0x8000" type="flash" rw="R" exec="1" name="ROM" pagesize="0x40"/>
          <memory-segment start="0x8000" size="0x8000" type="flash" rw="RW" exec="1" name="FLASH" pagesize="0x40"/>
        </address-space>
        <address-space endianness="little" name="signatures" id="signatures" start="0" size="3">
          <memory-segment start="0" size="3" type="signatures" rw="R" exec="0" name="SIGNATURES"/>
        </address-space>
        <address-space endianness="little" name="fuses" id="fuses" start="0" size="0x0001">
          <memory-segment start="0" size="0x0001" type="fuses" rw="RW" exec="0" name="FUSES"/>
        </address-space>
        <address-space endianness="little" name="lockbits" id="lockbits" start="0" size="0x0001">
          <memory-segment start="0" size="0x0001" type="lockbits" rw="RW" exec="0" name="LOCKBITS"/>
        </address-space>
        <address-space endianness="little" name="data" id="data" start="0x0000" size="0x0600">
          <memory-segment external="false" type="regs" size="0x0020" start="0x0000" name="REGISTERS"/>
          <memory-segment name="MAPPED_IO" start="0x0020" size="0x01e0" type="io" external="false"/>
          <memory-segment name="IRAM" start="0x0200" size="0x0400" type="ram" external="false"/>
        </address-space>
        <address-space endianness="little" name="eeprom" id="eeprom" start="0x0000" size="0x0880">
          <memory-segment start="0x0000" size="0x0880" type="eeprom" rw="RW" exec="0" name="EEPROM" pagesize="0x10"/>
        </address-space>
        <address-space size="0x40" start="0x00" endianness="little" name="io" id="io"/>
      </address-spaces>
      <peripherals>
        <module name="AES">
          <instance name="AES">
            <register-group name="AES" name-in-module="AES" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CLK">
          <instance name="CLK">
            <register-group name="CLK" name-in-module="CLK" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CPU">
          <instance name="CPU">
            <register-group name="CPU" name-in-module="CPU" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CRC">
          <instance name="CRC">
            <register-group name="CRC" name-in-module="CRC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DEBOUNCE">
          <instance name="DEBOUNCE">
            <register-group name="DEBOUNCE" name-in-module="DEBOUNCE" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DEBUG">
          <instance name="DEBUG">
            <register-group name="DEBUG" name-in-module="DEBUG" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DFIFO">
          <instance name="DFIFO">
            <register-group name="DFIFO" name-in-module="DFIFO" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="EEPROM">
          <instance name="EEPROM">
            <register-group name="EEPROM" name-in-module="EEPROM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="GPIOREGS_DVCC">
          <instance name="GPIOREGS_DVCC">
            <register-group name="GPIOREGS_DVCC" name-in-module="GPIOREGS_DVCC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="GPIOREGS_LFVCC">
          <instance name="GPIOREGS_LFVCC">
            <register-group name="GPIOREGS_LFVCC" name-in-module="GPIOREGS_LFVCC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="INT">
          <instance name="INT">
            <register-group name="INT" name-in-module="INT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="LED">
          <instance name="LED">
            <register-group name="LED" name-in-module="LED" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="LF_FIFO">
          <instance name="LF_FIFO">
            <register-group name="LF_FIFO" name-in-module="LF_FIFO" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="LF_PROTOCOL_HANDLER">
          <instance name="LF_PROTOCOL_HANDLER">
            <register-group name="LF_PROTOCOL_HANDLER" name-in-module="LF_PROTOCOL_HANDLER" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="LF_RECEIVER">
          <instance name="LF_RECEIVER">
            <register-group name="LF_RECEIVER" name-in-module="LF_RECEIVER" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="LF_RSSI">
          <instance name="LF_RSSI">
            <register-group name="LF_RSSI" name-in-module="LF_RSSI" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="LF_TIMER">
          <instance name="LF_TIMER">
            <register-group name="LF_TIMER" name-in-module="LF_TIMER" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="LF_TRANSPONDER">
          <instance name="LF_TRANSPONDER">
            <register-group name="LF_TRANSPONDER" name-in-module="LF_TRANSPONDER" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="MEM">
          <instance name="MEM">
            <register-group name="MEM" name-in-module="MEM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="PORTB">
          <instance name="PORTB">
            <register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="PORTC">
          <instance name="PORTC">
            <register-group name="PORTC" name-in-module="PORTC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="PORTD">
          <instance name="PORTD">
            <register-group name="PORTD" name-in-module="PORTD" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SFIFO">
          <instance name="SFIFO">
            <register-group name="SFIFO" name-in-module="SFIFO" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SPI">
          <instance name="SPI">
            <register-group name="SPI" name-in-module="SPI" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SPI2">
          <instance name="SPI2">
            <register-group name="SPI2" name-in-module="SPI2" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SSM">
          <instance name="SSM">
            <register-group name="SSM" name-in-module="SSM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SUP">
          <instance name="SUP">
            <register-group name="SUP" name-in-module="SUP" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER0_WDT">
          <instance name="TIMER0_WDT">
            <register-group name="TIMER0_WDT" name-in-module="TIMER0_WDT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER1">
          <instance name="TIMER1">
            <register-group name="TIMER1" name-in-module="TIMER1" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER2">
          <instance name="TIMER2">
            <register-group name="TIMER2" name-in-module="TIMER2" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER3">
          <instance name="TIMER3">
            <register-group name="TIMER3" name-in-module="TIMER3" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER4">
          <instance name="TIMER4">
            <register-group name="TIMER4" name-in-module="TIMER4" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER5">
          <instance name="TIMER5">
            <register-group name="TIMER5" name-in-module="TIMER5" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TMO">
          <instance name="TMO">
            <register-group name="TMO" name-in-module="TMO" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TPLF_CAL">
          <instance name="TPLF_CAL">
            <register-group name="TPLF_CAL" name-in-module="TPLF_CAL" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TWI1">
          <instance name="TWI1">
            <register-group name="TWI1" name-in-module="TWI1" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TWI2">
          <instance name="TWI2">
            <register-group name="TWI2" name-in-module="TWI2" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="VX_MODE">
          <instance name="VX_MODE">
            <register-group name="VX_MODE" name-in-module="VX_MODE" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FUSE">
          <instance name="FUSE">
            <register-group name="FUSE" name-in-module="FUSE" offset="0" address-space="fuses"/>
          </instance>
        </module>
        <module name="LOCKBIT">
          <instance name="LOCKBIT">
            <register-group name="LOCKBIT" name-in-module="LOCKBIT" offset="0" address-space="lockbits"/>
          </instance>
        </module>
      </peripherals>
      <interrupts>
        <interrupt index="0" name="RESET" caption="External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset"/>
        <interrupt index="1" name="INT0" caption="External Interrupt Request 0"/>
        <interrupt index="2" name="INT1" caption="External Interrupt Request 1"/>
        <interrupt index="3" name="PCI0" caption="Pin Change Interrupt Request 0"/>
        <interrupt index="4" name="PCI1" caption="Pin Change Interrupt Request 1"/>
        <interrupt index="5" name="VMON" caption="Voltage Monitoring Interrupt"/>
        <interrupt index="6" name="AVCCR" caption="AVCC Reset Interrupt"/>
        <interrupt index="7" name="AVCCL" caption="AVCC Low Interrupt"/>
        <interrupt index="8" name="T0INT" caption="Timer0 Interval Interrupt"/>
        <interrupt index="9" name="T1COMP" caption="Timer/Counter1 Compare Match Interrupt"/>
        <interrupt index="10" name="T1OVF" caption="Timer/Counter1 Overflow Interrupt"/>
        <interrupt index="11" name="T2COMP" caption="Timer/Counter2 Compare Match Interrupt"/>
        <interrupt index="12" name="T2OVF" caption="Timer/Counter2 Overflow Interrupt"/>
        <interrupt index="13" name="T3CAP" caption="Timer/Counter3 Capture Event Interrupt"/>
        <interrupt index="14" name="T3COMP" caption="Timer/Counter3 Compare Match Interrupt"/>
        <interrupt index="15" name="T3OVF" caption="Timer/Counter3 Overflow Interrupt"/>
        <interrupt index="16" name="T4CAP" caption="Timer/Counter4 Capture Event Interrupt"/>
        <interrupt index="17" name="T4COMP" caption="Timer/Counter4 Compare Match Interrupt"/>
        <interrupt index="18" name="T4OVF" caption="Timer/Counter4 Overflow Interrupt"/>
        <interrupt index="19" name="T5COMP" caption="Timer/Counter5 Compare Match Interrupt"/>
        <interrupt index="20" name="T5OVF" caption="Timer/Counter5 Overflow Interrupt"/>
        <interrupt index="21" name="SPI" caption="SPI Serial Transfer Complete Interrupt"/>
        <interrupt index="22" name="SRX_FIFO" caption="SPI Rx Buffer Interrupt"/>
        <interrupt index="23" name="STX_FIFO" caption="SPI Tx Buffer Interrupt"/>
        <interrupt index="24" name="SSM" caption="Sequencer State Machine Interrupt"/>
        <interrupt index="25" name="DFFLR" caption="Data FIFO fill level reached Interrupt"/>
        <interrupt index="26" name="DFOUE" caption="Data FIFO overflow or underflow error Interrupt"/>
        <interrupt index="27" name="SFFLR" caption="RSSI/Preamble FIFO fill level reached Interrupt"/>
        <interrupt index="28" name="SFOUE" caption="RSSI/Preamble FIFO overflow or underflow error Interrupt"/>
        <interrupt index="29" name="TMTCF" caption="Tx Modulator Telegram Finish Interrupt"/>
        <interrupt index="30" name="AES" caption="AES Krypto Unit Interrupt"/>
        <interrupt index="31" name="TPINT" caption="Transponder Mode Interrupt"/>
        <interrupt index="32" name="TPTOERR" caption="Transponder Timeout Error Interrupt"/>
        <interrupt index="33" name="LFID0INT" caption="LF receiver Identifier 0 Interrupt"/>
        <interrupt index="34" name="LFID1INT" caption="LF receiver Identifier 1 Interrupt"/>
        <interrupt index="35" name="LFFEINT" caption="LF receiver Frame End Interrupt"/>
        <interrupt index="36" name="LFBCR" caption="LF receiver Bit Count Reached Interrupt"/>
        <interrupt index="37" name="LFPBD" caption="LF receiver PreBurst Detected Interrupt"/>
        <interrupt index="38" name="LFDE" caption="LF receiver Decoder Error Interrupt"/>
        <interrupt index="39" name="LFEOT" caption="LF receiver End of Telegram Interrupt"/>
        <interrupt index="40" name="LFTCOR" caption="LF receiver Timer Compare Match Interrupt"/>
        <interrupt index="41" name="LFRSCO" caption="LF receiver RSSI measurement Interrupt"/>
        <interrupt index="42" name="LDFFLR" caption="LF Data FIFO Fill Level Reached Interrupt"/>
        <interrupt index="43" name="LDFOUE" caption="LF Data FIFO Overflow or Underflow Error Interrupt"/>
        <interrupt index="44" name="EXCM" caption="External input Clock monitoring Interrupt"/>
        <interrupt index="45" name="E2CINT" caption="EEPROM Error Correction Interrupt"/>
        <interrupt index="46" name="ERDY" caption="EEPROM Ready Interrupt"/>
        <interrupt index="47" name="SPMR" caption="Store Program Memory Ready"/>
        <interrupt index="48" name="TWI1" caption="TWI1 Interrupt"/>
        <interrupt index="49" name="SPI2" caption="SPI2 Interrupt"/>
        <interrupt index="50" name="TWI2" caption="TWI2 Interrupt"/>
      </interrupts>
      <interfaces>
        <interface name="ISP" type="isp"/>
        <interface name="HVSP" type="hvsp"/>
        <interface name="debugWIRE" type="dw"/>
      </interfaces>
      <property-groups>
        <property-group name="SIGNATURES">
          <property name="JTAGID" value="0x9569"/>
          <property name="SIGNATURE0" value="0x1e"/>
          <property name="SIGNATURE1" value="0x95"/>
          <property name="SIGNATURE2" value="0x67"/>
        </property-group>
        <property-group name="OCD">
          <property name="OCD_REVISION" value="1"/>
          <property name="OCD_DATAREG" value="0x31"/>
          <property name="PROGBASE" value="0x0000"/>
        </property-group>
        <property-group name="JTAG_INTERFACE">
          <property name="ALLOWFULLPAGESTREAM" value="0x00"/>
        </property-group>
        <property-group name="ISP_INTERFACE">
          <property name="IspEnterProgMode_timeout" value="255"/>
          <property name="IspEnterProgMode_stabDelay" value="255"/>
          <property name="IspEnterProgMode_cmdexeDelay" value="30"/>
          <property name="IspEnterProgMode_synchLoops" value="64"/>
          <property name="IspEnterProgMode_bitDelay" value="5"/>
          <property name="IspEnterProgMode_byteDelay" value="1"/>
          <property name="IspEnterProgMode_pollIndex" value="3"/>
          <property name="IspEnterProgMode_pollValue" value="0x53"/>
          <property name="IspLeaveProgMode_preDelay" value="1"/>
          <property name="IspLeaveProgMode_postDelay" value="1"/>
          <property name="IspChipErase_eraseDelay" value="45"/>
          <property name="IspChipErase_pollMethod" value="1"/>
          <property name="IspProgramFlash_mode" value="0x41"/>
          <property name="IspProgramFlash_blockSize" value="64"/>
          <property name="IspProgramFlash_delay" value="10"/>
          <property name="IspProgramFlash_cmd1" value="0x40"/>
          <property name="IspProgramFlash_cmd2" value="0x4C"/>
          <property name="IspProgramFlash_cmd3" value="0x00"/>
          <property name="IspProgramFlash_pollVal1" value="0x00"/>
          <property name="IspProgramFlash_pollVal2" value="0x00"/>
          <property name="IspProgramEeprom_mode" value="0x41"/>
          <property name="IspProgramEeprom_blockSize" value="16"/>
          <property name="IspProgramEeprom_delay" value="20"/>
          <property name="IspProgramEeprom_cmd1" value="0xC1"/>
          <property name="IspProgramEeprom_cmd2" value="0xC2"/>
          <property name="IspProgramEeprom_cmd3" value="0x00"/>
          <property name="IspProgramEeprom_pollVal1" value="0x00"/>
          <property name="IspProgramEeprom_pollVal2" value="0x00"/>
          <property name="IspReadFlash_blockSize" value="256"/>
          <property name="IspReadEeprom_blockSize" value="256"/>
          <property name="IspReadFuse_pollIndex" value="4"/>
          <property name="IspReadLock_pollIndex" value="4"/>
          <property name="IspReadSign_pollIndex" value="4"/>
          <property name="IspReadOsccal_pollIndex" value="4"/>
        </property-group>
        <property-group name="HVSP_INTERFACE">
          <property name="HvspControlStack" value="0x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x00"/>
          <property name="HvspEnterProgMode_stabDelay" value="100"/>
          <property name="HvspEnterProgMode_cmdexeDelay" value="0"/>
          <property name="HvspEnterProgMode_synchCycles" value="6"/>
          <property name="HvspEnterProgMode_latchCycles" value="1"/>
          <property name="HvspEnterProgMode_toggleVtg" value="1"/>
          <property name="HvspEnterProgMode_powoffDelay" value="25"/>
          <property name="HvspEnterProgMode_resetDelay1" value="2"/>
          <property name="HvspEnterProgMode_resetDelay2" value="0"/>
          <property name="HvspLeaveProgMode_stabDelay" value="100"/>
          <property name="HvspLeaveProgMode_resetDelay" value="25"/>
          <property name="HvspChipErase_pollTimeout" value="40"/>
          <property name="HvspChipErase_eraseTime" value="0"/>
          <property name="HvspProgramFlash_mode" value="0x0B"/>
          <property name="HvspProgramFlash_blockSize" value="32"/>
          <property name="HvspProgramFlash_pollTimeout" value="5"/>
          <property name="HvspReadFlash_blockSize" value="256"/>
          <property name="HvspProgramEeprom_mode" value="0x05"/>
          <property name="HvspProgramEeprom_blockSize" value="8"/>
          <property name="HvspProgramEeprom_pollTimeout" value="5"/>
          <property name="HvspReadEeprom_blockSize" value="256"/>
          <property name="HvspProgramFuse_pollTimeout" value="25"/>
          <property name="HvspProgramLock_pollTimeout" value="25"/>
        </property-group>
        <property-group name="ISP_INTERFACE_STK600">
          <property name="IspEnterProgMode_timeout" value="255"/>
          <property name="IspEnterProgMode_stabDelay" value="255"/>
          <property name="IspEnterProgMode_cmdexeDelay" value="45"/>
          <property name="IspEnterProgMode_synchLoops" value="64"/>
          <property name="IspEnterProgMode_byteDelay" value="4"/>
          <property name="IspEnterProgMode_pollIndex" value="3"/>
          <property name="IspEnterProgMode_pollValue" value="0x53"/>
          <property name="IspLeaveProgMode_preDelay" value="1"/>
          <property name="IspLeaveProgMode_postDelay" value="1"/>
          <property name="IspChipErase_eraseDelay" value="45"/>
          <property name="IspChipErase_pollMethod" value="1"/>
          <property name="IspProgramFlash_mode" value="0x41"/>
          <property name="IspProgramFlash_blockSize" value="32"/>
          <property name="IspProgramFlash_delay" value="10"/>
          <property name="IspProgramFlash_cmd1" value="0x40"/>
          <property name="IspProgramFlash_cmd2" value="0x4C"/>
          <property name="IspProgramFlash_cmd3" value="0x00"/>
          <property name="IspProgramFlash_pollVal1" value="0x00"/>
          <property name="IspProgramFlash_pollVal2" value="0x00"/>
          <property name="IspProgramEeprom_mode" value="0x41"/>
          <property name="IspProgramEeprom_blockSize" value="8"/>
          <property name="IspProgramEeprom_delay" value="20"/>
          <property name="IspProgramEeprom_cmd1" value="0xC1"/>
          <property name="IspProgramEeprom_cmd2" value="0xC2"/>
          <property name="IspProgramEeprom_cmd3" value="0x00"/>
          <property name="IspProgramEeprom_pollVal1" value="0x00"/>
          <property name="IspProgramEeprom_pollVal2" value="0x00"/>
          <property name="IspReadFlash_blockSize" value="256"/>
          <property name="IspReadEeprom_blockSize" value="256"/>
          <property name="IspReadFuse_pollIndex" value="4"/>
          <property name="IspReadLock_pollIndex" value="4"/>
          <property name="IspReadSign_pollIndex" value="4"/>
          <property name="IspReadOsccal_pollIndex" value="4"/>
        </property-group>
        <property-group name="HVSP_INTERFACE_STK600">
          <property name="HvspControlStack" value="0x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x00"/>
          <property name="HvspEnterProgMode_stabDelay" value="100"/>
          <property name="HvspEnterProgMode_cmdexeDelay" value="0"/>
          <property name="HvspEnterProgMode_synchCycles" value="6"/>
          <property name="HvspEnterProgMode_latchCycles" value="1"/>
          <property name="HvspEnterProgMode_toggleVtg" value="1"/>
          <property name="HvspEnterProgMode_powoffDelay" value="20"/>
          <property name="HvspEnterProgMode_resetDelay1" value="0"/>
          <property name="HvspEnterProgMode_resetDelay2" value="50"/>
          <property name="HvspLeaveProgMode_stabDelay" value="100"/>
          <property name="HvspLeaveProgMode_resetDelay" value="25"/>
          <property name="HvspChipErase_pollTimeout" value="40"/>
          <property name="HvspChipErase_eraseTime" value="0"/>
          <property name="HvspProgramFlash_mode" value="0x0B"/>
          <property name="HvspProgramFlash_blockSize" value="32"/>
          <property name="HvspProgramFlash_pollTimeout" value="5"/>
          <property name="HvspReadFlash_blockSize" value="256"/>
          <property name="HvspProgramEeprom_mode" value="0x05"/>
          <property name="HvspProgramEeprom_blockSize" value="8"/>
          <property name="HvspProgramEeprom_pollTimeout" value="5"/>
          <property name="HvspReadEeprom_blockSize" value="256"/>
          <property name="HvspProgramFuse_pollTimeout" value="25"/>
          <property name="HvspProgramLock_pollTimeout" value="25"/>
        </property-group>
      </property-groups>
    </device>
  </devices>
  <modules>
    <module caption="" name="AES">
      <register-group caption="" name="AES">
        <register caption="AES Control Register" name="AESCR" offset="0x003D" size="1">
          <bitfield caption="AES Enable" mask="0x80" name="AESE"/>
          <bitfield caption="AES Load Key Memory" mask="0x40" name="AESLKM"/>
          <bitfield caption="AES Reset" mask="0x20" name="AESRES"/>
          <bitfield caption="AES State XOR load" mask="0x10" name="AESXOR"/>
          <bitfield caption="AES Direction" mask="0x08" name="AESD"/>
          <bitfield caption="AES Interrupt Mask" mask="0x04" name="AESIM"/>
          <bitfield caption="AES Write Data" mask="0x02" name="AESWD"/>
          <bitfield caption="AES Write Key" mask="0x01" name="AESWK"/>
        </register>
        <register caption="AES Data Pointer Register" name="AESDPR" offset="0x017F" size="1" mask="0x0F"/>
        <register caption="AES Data Register" name="AESDR" offset="0x0181" size="1" mask="0xFF"/>
        <register caption="AES Key Register" name="AESKR" offset="0x0180" size="1" mask="0xFF"/>
        <register caption="AES Status Register" name="AESSR" offset="0x003E" size="1">
          <bitfield caption="AES Error Flag" mask="0x80" name="AESERF"/>
          <bitfield caption="AES Ready Flag" mask="0x01" name="AESRF"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="CLK">
      <register-group caption="" name="CLK">
        <register caption="Clock output control Register" name="CLKOCR" offset="0x0116" size="1">
          <bitfield caption="Clock output driver enable" mask="0x04" name="CLKOEN"/>
          <bitfield caption="Clock output source" mask="0x03" name="CLKOS" values="CLKOUT_CLOCK_SELECT"/>
        </register>
        <register caption="Clock output divider settings Register" name="CLKOD" offset="0x0115" size="1" mask="0xFF"/>
        <register caption="Clock management override control register" name="CMOCR" offset="0x00CA" size="1">
          <bitfield caption="FRC Active" mask="0x04" name="FRCACT"/>
          <bitfield caption="MRC Always On" mask="0x02" name="MRCAO"/>
          <bitfield caption="FRC Always On" mask="0x01" name="FRCAO"/>
        </register>
        <register caption="Clock management status Register" name="CMSR" offset="0x00C9" size="1">
          <bitfield caption="External clock fail" mask="0x01" name="ECF"/>
        </register>
        <register caption="Fast RC oscillator calibration Register" name="FRCCAL" offset="0x00C7" size="1" mask="0x1F"/>
        <register caption="Middle RC oscillator calibration Register" name="MRCCAL" offset="0x00C6" size="1" mask="0xFE"/>
        <register caption="Power reduction Register 0" name="PRR0" offset="0x003A" size="1">
          <bitfield caption="Power Reduction Two Wire Interface 1" mask="0x80" name="PRTWI1"/>
          <bitfield caption="Power Reduction Crypto Unit" mask="0x40" name="PRCU"/>
          <bitfield caption="Power Reduction Clock Output" mask="0x20" name="PRCO"/>
          <bitfield caption="Power Reduction Voltage Monitor" mask="0x10" name="PRVM"/>
          <bitfield caption="Power Reduction CRC" mask="0x08" name="PRCRC"/>
          <bitfield caption="Power Reduction Transmit DSP Control" mask="0x04" name="PRTXDC"/>
          <bitfield caption="Power Reduction LF RSSI" mask="0x02" name="PRLFRS"/>
          <bitfield caption="Power Reduction Serial Peripheral Interface" mask="0x01" name="PRSPI"/>
        </register>
        <register caption="Power reduction Register 1" name="PRR1" offset="0x0021" size="1">
          <bitfield caption="Power Reduction LF Protocol Handler" mask="0x80" name="PRLFPH"/>
          <bitfield caption="Power Reduction LF Transponder" mask="0x40" name="PRLFTP"/>
          <bitfield caption="Power Reduction LF Receiver" mask="0x20" name="PRLFR"/>
          <bitfield caption="Power Reduction Timer 5" mask="0x10" name="PRT5"/>
          <bitfield caption="Power Reduction Timer 4" mask="0x08" name="PRT4"/>
          <bitfield caption="Power Reduction Timer 3" mask="0x04" name="PRT3"/>
          <bitfield caption="Power Reduction Timer 2" mask="0x02" name="PRT2"/>
          <bitfield caption="Power Reduction Timer 1" mask="0x01" name="PRT1"/>
        </register>
        <register caption="Power reduction register 2" name="PRR2" offset="0x0022" size="1">
          <bitfield caption="Power Reduction Sequencer State Machine" mask="0x80" name="PRSSM"/>
          <bitfield caption="Power Reduction Tx Modulator" mask="0x40" name="PRTM"/>
          <bitfield caption="VX Tri-State Disable" mask="0x10" name="VXTSDI"/>
          <bitfield caption="Power Reduction Data FIFO" mask="0x08" name="PRDF"/>
          <bitfield caption="Power Reduction Support FIFO" mask="0x04" name="PRSF"/>
          <bitfield caption="Power Reduction TWI2" mask="0x02" name="PRTWI2"/>
          <bitfield caption="Power Reduction SPI2" mask="0x01" name="PRSPI2"/>
        </register>
        <register caption="" name="XFUSE" offset="0x00C5" size="1"/>
      </register-group>
      <value-group caption="" name="CLKOUT_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_frc" name="VAL_0x01" value="0x01"/>
        <value caption="clk_mrc" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="CPU">
      <register-group caption="" name="CPU">
        <register caption="Clock Prescaler Register" name="CLPR" offset="0x01E5" size="1">
          <bitfield caption="Clock Prescaler Change Enable" mask="0x80" name="CLPCE"/>
          <bitfield caption="Timer Clock Prescaler Select" mask="0x38" name="CLTPS" values="CPU_CLT_PRESCALE_3BITS"/>
          <bitfield caption="System Clock Prescaler Select" mask="0x07" name="CLKPS" values="CPU_CLK_PRESCALE_3BITS"/>
        </register>
        <register caption="Clock Management Control Register" name="CMCR" offset="0x01E3" size="1">
          <bitfield caption="Clock management control change enable" mask="0x80" name="CMCCE"/>
          <bitfield caption="Clock monitor enable" mask="0x40" name="CMONEN"/>
          <bitfield caption="Core Clock Select" mask="0x08" name="CCS"/>
          <bitfield caption="Clock Management Mode" mask="0x07" name="CMM"/>
        </register>
        <register caption="Clock interrupt mask Register" name="CMIMR" offset="0x01E4" size="1">
          <bitfield caption="External clock interrupt enable" mask="0x01" name="ECIE"/>
        </register>
        <register caption="Debug Wire Data Register" name="DWDR" offset="0x0051" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="MCU control Register" name="MCUCR" offset="0x002E" size="1">
          <bitfield caption="Interrupt Vector Select" mask="0x80" name="IVSEL"/>
          <bitfield caption="Trace Enable" mask="0x40" name="TRCEN"/>
          <bitfield caption="Trace Change Enable" mask="0x20" name="TRCCE"/>
          <bitfield caption="Pull-up Resistors Disable" mask="0x10" name="PUD"/>
          <bitfield caption="Enable Port Settings" mask="0x08" name="ENPS"/>
          <bitfield caption="SPI Interrupt Only" mask="0x04" name="SPIIO"/>
          <bitfield caption="Interrupt Vector Location" mask="0x03" name="IVL" values="CPU_IVL_2BITS"/>
        </register>
        <register caption="MCU Status Register" name="MCUSR" offset="0x004B" size="1">
          <bitfield caption="Transponder Reset Flag" mask="0x20" name="TPRF"/>
          <bitfield caption="DebugWire Reset Flag" mask="0x10" name="DWRF"/>
          <bitfield caption="Watchdog Reset Flag" mask="0x08" name="WDRF"/>
          <bitfield caption="External Reset Flag" mask="0x02" name="EXTRF"/>
          <bitfield caption="Power-On Reset Flag" mask="0x01" name="PORF"/>
        </register>
        <register caption="Sleep mode control Register" name="SMCR" offset="0x0058" size="1">
          <bitfield caption="Sleep Mode Select" mask="0x0E" name="SM" values="CPU_SLEEP_MODE_3BITS"/>
          <bitfield caption="Sleep Enable" mask="0x01" name="SE"/>
        </register>
        <register caption="Stack Pointer" name="SP" offset="0x005D" size="2" mask="0x07FF"/>
        <register caption="Store Program Memory Control and Status Register" name="SPMCSR" offset="0x0057" size="1">
          <bitfield caption="SPM Interrupt Enable" mask="0x80" name="SPMIE"/>
          <bitfield caption="Read-While-Write Section Busy" mask="0x40" name="RWWSB"/>
          <bitfield caption="Fuse Lockbit select" mask="0x38" name="FLSEL" values="CPU_FUSE_LOCK_SEL_3BITS"/>
          <bitfield caption="Page Write" mask="0x04" name="PGWRT"/>
          <bitfield caption="Page Erase" mask="0x02" name="PGERS"/>
          <bitfield caption="Self Programming Enable" mask="0x01" name="SELFPRGEN"/>
        </register>
        <register caption="Status Register" name="SREG" offset="0x005F" size="1">
          <bitfield caption="Global Interrupt Enable" mask="0x80" name="I"/>
          <bitfield caption="Bit Copy Storage" mask="0x40" name="T"/>
          <bitfield caption="Half Carry Flag" mask="0x20" name="H"/>
          <bitfield caption="Sign Bit" mask="0x10" name="S"/>
          <bitfield caption="Two's Complement Overflow Flag" mask="0x08" name="V"/>
          <bitfield caption="Negative Flag" mask="0x04" name="N"/>
          <bitfield caption="Zero Flag" mask="0x02" name="Z"/>
          <bitfield caption="Carry Flag" mask="0x01" name="C"/>
        </register>
      </register-group>
      <value-group caption="" name="CPU_CLT_PRESCALE_3BITS">
        <value caption="disabled" name="VAL_0x00" value="0x00"/>
        <value caption="1" name="VAL_0x01" value="0x01"/>
        <value caption="2" name="VAL_0x02" value="0x02"/>
        <value caption="4" name="VAL_0x03" value="0x03"/>
        <value caption="8" name="VAL_0x04" value="0x04"/>
        <value caption="16" name="VAL_0x05" value="0x05"/>
        <value caption="32" name="VAL_0x06" value="0x06"/>
        <value caption="64" name="VAL_0x07" value="0x07"/>
      </value-group>
      <value-group caption="" name="CPU_CLK_PRESCALE_3BITS">
        <value caption="1" name="VAL_0x00" value="0x00"/>
        <value caption="2" name="VAL_0x01" value="0x01"/>
        <value caption="4" name="VAL_0x02" value="0x02"/>
        <value caption="8" name="VAL_0x03" value="0x03"/>
        <value caption="16" name="VAL_0x04" value="0x04"/>
        <value caption="32" name="VAL_0x05" value="0x05"/>
        <value caption="64" name="VAL_0x06" value="0x06"/>
        <value caption="128" name="VAL_0x07" value="0x07"/>
      </value-group>
      <value-group caption="" name="CPU_SLEEP_MODE_3BITS">
        <value caption="Idle" name="IDLE" value="0x00"/>
        <value caption="Power save" name="PSAVE" value="0x01"/>
        <value caption="Power down" name="PDOWN" value="0x02"/>
        <value caption="Extended power save" name="EPSAVE" value="0x03"/>
        <value caption="Extended power down" name="EPDOWN" value="0x04"/>
        <value caption="Power off" name="POFF" value="0x05"/>
      </value-group>
      <value-group caption="" name="CPU_IVL_2BITS">
        <value caption="0x3600" name="VAL_0x00" value="0x00"/>
        <value caption="0x4000" name="VAL_0x01" value="0x01"/>
        <value caption="0x7000" name="VAL_0x02" value="0x02"/>
        <value caption="0x8000" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="CPU_FUSE_LOCK_SEL_3BITS">
        <value caption="ROM/FLASH" name="VAL_0x00" value="0x00"/>
        <value caption="Lockbits" name="VAL_0x01" value="0x08"/>
        <value caption="Security Fuses" name="VAL_0x03" value="0x18"/>
        <value caption="EEPROM Protection Fuse Low" name="VAL_0x05" value="0x28"/>
        <value caption="EEPROM Protection Fuse High" name="VALR_0x07" value="0x38"/>
      </value-group>
    </module>
    <module caption="" name="CRC">
      <register-group caption="" name="CRC">
        <register caption="CRC Control Register" name="CRCCR" offset="0x0145" size="1">
          <bitfield caption="Reflect Data Output Byte" mask="0x04" name="REFLO"/>
          <bitfield caption="Reflect Data Input Byte" mask="0x02" name="REFLI"/>
          <bitfield caption="CRC Data Register Reset" mask="0x01" name="CRCRS"/>
        </register>
        <register caption="CRC Data Input Register" name="CRCDIR" offset="0x01E0" size="1" mask="0xFF" ocd-rw="W"/>
        <register caption="CRC Data Output Register" name="CRCDOR" offset="0x0146" size="1" mask="0xFF" ocd-rw="R"/>
      </register-group>
    </module>
    <module caption="" name="DEBOUNCE">
      <register-group caption="" name="DEBOUNCE">
        <register caption="DeBounce Control Register" name="DBCR" offset="0x0152" size="1">
          <bitfield caption="Debounce Handshake Active" mask="0x08" name="DBHA"/>
          <bitfield caption="Debounce Timer Mask Select" mask="0x04" name="DBTMS"/>
          <bitfield caption="Debounce Clock Select" mask="0x02" name="DBCS"/>
          <bitfield caption="Debounce Mode" mask="0x01" name="DBMD"/>
        </register>
        <register caption="DeBounce Enable Port B" name="DBENB" offset="0x0154" size="1" mask="0xFF"/>
        <register caption="DeBounce Enable Port C" name="DBENC" offset="0x0155" size="1" mask="0x07"/>
        <register caption="DeBounce Enable Port D" name="DBEND" offset="0x0164" size="1" mask="0xFF"/>
        <register caption="Debounce Timer Compare Register" name="DBTC" offset="0x0153" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="DEBUG">
      <register-group caption="" name="DEBUG">
        <register caption="Debugging Support Switch" name="DBGSW" offset="0x0156" size="1">
          <bitfield caption="Analog Test Pins Enable" mask="0x80" name="ATEST"/>
          <bitfield caption="CPU Busy Flag" mask="0x40" name="CPBF"/>
          <bitfield caption="CPU Busy Flag Output Select" mask="0x30" name="CPBFOS" values="CPU_BUSY_OUT"/>
          <bitfield caption="Debugging Support Group Select" mask="0x0F" name="DBGGS"/>
        </register>
        <register caption="Downbond Test Register" name="DBONDR" offset="0x01E7" size="1">
          <bitfield caption="Bond Test 6" mask="0x40" name="BTEST6"/>
          <bitfield caption="Bond Test 5" mask="0x20" name="BTEST5"/>
          <bitfield caption="Bond Test 4" mask="0x10" name="BTEST4"/>
          <bitfield caption="Bond AGND LF" mask="0x08" name="AGND_LF"/>
          <bitfield caption="Bond ISO SUBS3 GND" mask="0x04" name="ISO_GND"/>
          <bitfield caption="Bond AGND BB" mask="0x02" name="AGND_BB"/>
          <bitfield caption="Bond BBESD" mask="0x01" name="BBESD"/>
        </register>
        <register caption="Trace Data Register" name="TRCDR" offset="0x00FF" size="1" mask="0xFF"/>
        <register caption="Trace ID Register" name="TRCID" offset="0x00FC" size="2" mask="0xFFFF"/>
      </register-group>
      <value-group caption="" name="CPU_BUSY_OUT">
        <value caption="disabled" name="VAL_0x00" value="0x00"/>
        <value caption="PB0" name="VAL_0x01" value="0x01"/>
        <value caption="PB3" name="VAL_0x02" value="0x02"/>
        <value caption="PC1" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="DFIFO">
      <register-group caption="" name="DFIFO">
        <register caption="Data FIFO Configuration Register" name="DFC" offset="0x00DA" size="1">
          <bitfield caption="Data FIFO Direct Read Access Operational Mode" mask="0x80" name="DFDRA"/>
          <bitfield caption="Data FIFO Fill-Level Configuration" mask="0x3F" name="DFFLC"/>
        </register>
        <register caption="Data FIFO Data Register" name="DFD" offset="0x00D8" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="Data FIFO Interrupt Mask Register" name="DFI" offset="0x00D9" size="1">
          <bitfield caption="Data FIFO Error Interrupt Mask" mask="0x02" name="DFERIM"/>
          <bitfield caption="Data FIFO Fill-level Interrupt Mask" mask="0x01" name="DFFLIM"/>
        </register>
        <register caption="Data FIFO Fill Level Register" name="DFL" offset="0x00D5" size="1">
          <bitfield caption="Data FIFO Clear" mask="0x80" name="DFCLR"/>
          <bitfield caption="Data FIFO Fill Level Status" mask="0x3F" name="DFFLS"/>
        </register>
        <register caption="Data FIFO Read Pointer" name="DFRP" offset="0x00D7" size="1" mask="0x3F"/>
        <register caption="Data FIFO Status Register" name="DFS" offset="0x00D2" size="1">
          <bitfield caption="Data FIFO Overflow Flag" mask="0x04" name="DFOFL"/>
          <bitfield caption="Data FIFO Underflow Flag" mask="0x02" name="DFUFL"/>
          <bitfield caption="Data FIFO Fill-Level Reached Status Flag" mask="0x01" name="DFFLRF"/>
        </register>
        <register caption="Data FIFO Write Pointer" name="DFWP" offset="0x00D6" size="1" mask="0x3F"/>
      </register-group>
    </module>
    <module caption="" name="EEPROM">
      <register-group caption="" name="EEPROM">
        <register caption="EEPROM Address Register" name="EEAR" offset="0x0041" size="2" mask="0x0FFF"/>
        <register caption="EEPROM Control Register" name="EECR" offset="0x003F" size="1">
          <bitfield caption="Non-volatile memory busy" mask="0x80" name="NVMBSY"/>
          <bitfield caption="EEPROM page access (multiple bytes access mode)" mask="0x40" name="EEPAGE"/>
          <bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM" values="EEP_MODE"/>
          <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
          <bitfield caption="EEPROM Master Write Enable" mask="0x04" name="EEMWE"/>
          <bitfield caption="EEPROM Write Enable" mask="0x02" name="EEWE"/>
          <bitfield caption="EEPROM Read Enable" mask="0x01" name="EERE"/>
        </register>
        <register caption="EEPROM Control Register 2" name="EECR2" offset="0x0036" size="1">
          <bitfield caption="EEPROM Error Correction Code Flag" mask="0x80" name="E2CF"/>
          <bitfield caption="EEPROM error Fault Flag bit" mask="0x40" name="E2FF"/>
          <bitfield caption="EEPROM Access Violation Flag" mask="0x20" name="E2AVF"/>
          <bitfield caption="EEPROM Error Code Correction Interrupt Mask" mask="0x02" name="E2CIM"/>
          <bitfield caption="EEPROM Burst Read Enable" mask="0x01" name="EEBRE"/>
        </register>
        <register caption="EEPROM Data Register" name="EEDR" offset="0x0040" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="EEPROM Protection Register" name="EEPR" offset="0x0043" size="1">
          <bitfield caption="EEPROM Access Protection" mask="0x0F" name="EEAP"/>
        </register>
        <register caption="EEPROM Protection Register 1" name="EEPR1" offset="0x013B" size="1">
          <bitfield caption="EEPROM Protection Section 7 Read Disable" mask="0x80" name="EEPS7RD"/>
          <bitfield caption="EEPROM Protection Section 7 Write Disable" mask="0x40" name="EEPS7WD"/>
          <bitfield caption="EEPROM Protection Section 6 Read Disable" mask="0x20" name="EEPS6RD"/>
          <bitfield caption="EEPROM Protection Section 6 Write Disable" mask="0x10" name="EEPS6WD"/>
          <bitfield caption="EEPROM Protection Section 5 Read Disable" mask="0x08" name="EEPS5RD"/>
          <bitfield caption="EEPROM Protection Section 5 Write Disable" mask="0x04" name="EEPS5WD"/>
          <bitfield caption="EEPROM Protection Section 4 Read Disable" mask="0x02" name="EEPS4RD"/>
          <bitfield caption="EEPROM Protection Section 4 Write Disable" mask="0x01" name="EEPS4WD"/>
        </register>
        <register caption="EEPROM Protection Register 2" name="EEPR2" offset="0x013C" size="1">
          <bitfield caption="EEPROM Protection Section 11 Read Disable" mask="0x80" name="EEPS11RD"/>
          <bitfield caption="EEPROM Protection Section 11 Write Disable" mask="0x40" name="EEPS11WD"/>
          <bitfield caption="EEPROM Protection Section 10 Read Disable" mask="0x20" name="EEPS10RD"/>
          <bitfield caption="EEPROM Protection Section 10 Write Disableble" mask="0x10" name="EEPS10WD"/>
          <bitfield caption="EEPROM Protection Section 9 Read Disable" mask="0x08" name="EEPS9RD"/>
          <bitfield caption="EEPROM Protection Section 9 Write Disable" mask="0x04" name="EEPS9WD"/>
          <bitfield caption="EEPROM Protection Section 8 Read Disable" mask="0x02" name="EEPS8RD"/>
          <bitfield caption="EEPROM Protection Section 8 Write Disable" mask="0x01" name="EEPS8WD"/>
        </register>
        <register caption="EEPROM Protection Register 3" name="EEPR3" offset="0x013D" size="1">
          <bitfield caption="EEPROM Protection Section 12 Read Disable" mask="0x02" name="EEPS12RD"/>
          <bitfield caption="EEPROM Protection Section 12 Write Disable" mask="0x01" name="EEPS12WD"/>
        </register>
      </register-group>
      <value-group caption="" name="EEP_MODE">
        <value caption="Erase and Write in one operation" name="VAL_0x00" value="0x00"/>
        <value caption="Erase Only" name="VAL_0x01" value="0x01"/>
        <value caption="Write Only" name="VAL_0x02" value="0x02"/>
      </value-group>
    </module>
    <module caption="" name="GPIOREGS_DVCC">
      <register-group caption="" name="GPIOREGS_DVCC">
        <register caption="General Purpose I/O Register 0" name="GPIOR0" offset="0x0020" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 1" name="GPIOR1" offset="0x0044" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 2" name="GPIOR2" offset="0x0045" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="GPIOREGS_LFVCC">
      <register-group caption="" name="GPIOREGS_LFVCC">
        <register caption="General Purpose I/O Register 3" name="GPIOR3" offset="0x0182" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 4" name="GPIOR4" offset="0x0183" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 5" name="GPIOR5" offset="0x0184" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 6" name="GPIOR6" offset="0x0185" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 7" name="GPIOR7" offset="0x0186" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 8" name="GPIOR8" offset="0x0187" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="INT">
      <register-group caption="" name="INT">
        <register caption="External Interrupt control Register" name="EICRA" offset="0x006B" size="1">
          <bitfield caption="Interrupt Sense Control 1" mask="0x0C" name="ISC1" values="INTERRUPT_SENSE_CONTROL"/>
          <bitfield caption="Interrupt Sense Control 0" mask="0x03" name="ISC0" values="INTERRUPT_SENSE_CONTROL"/>
        </register>
        <register caption="External Interrupt Flag Register" name="EIFR" offset="0x0048" size="1">
          <bitfield caption="External Interrupt Flag 1" mask="0x02" name="INTF1"/>
          <bitfield caption="External Interrupt Flag 0" mask="0x01" name="INTF0"/>
        </register>
        <register caption="External Interrupt Mask Register" name="EIMSK" offset="0x0047" size="1">
          <bitfield caption="External Interrupt Request 1 Enable" mask="0x02" name="INT1"/>
          <bitfield caption="External Interrupt Request 0 Enable" mask="0x01" name="INT0"/>
        </register>
        <register caption="Pin change Interrupt control Register" name="PCICR" offset="0x0046" size="1">
          <bitfield caption="Pin Change Interrupt Enable 1" mask="0x02" name="PCIE1"/>
          <bitfield caption="Pin Change Interrupt Enable 0" mask="0x01" name="PCIE0"/>
        </register>
        <register caption="Pin change Interrupt flag Register" name="PCIFR" offset="0x0161" size="1">
          <bitfield caption="Pin Change Interrupt Flag 1" mask="0x02" name="PCIF1"/>
          <bitfield caption="Pin Change Interrupt Flag 0" mask="0x01" name="PCIF0"/>
        </register>
        <register caption="Pin change Mask Register 0" name="PCMSK0" offset="0x006C" size="1">
          <bitfield caption="Pin Change Enable Mask bit 7" mask="0x80" name="PCINT7"/>
          <bitfield caption="Pin Change Enable Mask bit 6" mask="0x40" name="PCINT6"/>
          <bitfield caption="Pin Change Enable Mask bit 5" mask="0x20" name="PCINT5"/>
          <bitfield caption="Pin Change Enable Mask bit 4" mask="0x10" name="PCINT4"/>
          <bitfield caption="Pin Change Enable Mask bit 3" mask="0x08" name="PCINT3"/>
          <bitfield caption="Pin Change Enable Mask bit 2" mask="0x04" name="PCINT2"/>
          <bitfield caption="Pin Change Enable Mask bit 1" mask="0x02" name="PCINT1"/>
          <bitfield caption="Pin Change Enable Mask bit 0" mask="0x01" name="PCINT0"/>
        </register>
        <register caption="Pin change Mask Register 1" name="PCMSK1" offset="0x006D" size="1">
          <bitfield caption="Pin Change Enable Mask bit 15" mask="0x80" name="PCINT15"/>
          <bitfield caption="Pin Change Enable Mask bit 14" mask="0x40" name="PCINT14"/>
          <bitfield caption="Pin Change Enable Mask bit 13" mask="0x20" name="PCINT13"/>
          <bitfield caption="Pin Change Enable Mask bit 12" mask="0x10" name="PCINT12"/>
          <bitfield caption="Pin Change Enable Mask bit 11" mask="0x08" name="PCINT11"/>
          <bitfield caption="Pin Change Enable Mask bit 10" mask="0x04" name="PCINT10"/>
          <bitfield caption="Pin Change Enable Mask bit 9" mask="0x02" name="PCINT9"/>
          <bitfield caption="Pin Change Enable Mask bit 8" mask="0x01" name="PCINT8"/>
        </register>
      </register-group>
      <value-group caption="Interrupt Sense Control" name="INTERRUPT_SENSE_CONTROL">
        <value caption="Low Level of INTX" name="VAL_0x00" value="0x00"/>
        <value caption="Logical Change of INTX" name="VAL_0x01" value="0x01"/>
        <value caption="Falling Edge of INTX" name="VAL_0x02" value="0x02"/>
        <value caption="Rising Edge of INTX" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="LED">
      <register-group caption="" name="LED">
        <register caption="Pad Driver Strength Control Register" name="PDSCR" offset="0x01EF" size="1">
          <bitfield caption="Analog Testbus Select" mask="0x80" name="ATBSEL"/>
          <bitfield caption="Testmode Enable for RSSI Measurement" mask="0x40" name="RSSISEL"/>
          <bitfield caption="Standby Test Enable" mask="0x20" name="STBTEST"/>
          <bitfield caption="Pad Driver Strength Control" mask="0x1F" name="PDSC"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="LF_FIFO">
      <register-group caption="" name="LF_FIFO">
        <register caption="LF Data FIFO Configuration Register" name="LDFC" offset="0x01D7" size="1">
          <bitfield caption="LF Data FIFO MSB alignment bit" mask="0x40" name="LDFMSB"/>
          <bitfield caption="LF Data FIFO Fill-Level Configuration" mask="0x3F" name="LDFFLC"/>
        </register>
        <register caption="LF Data FIFO Clock Switch Register" name="LDFCKSW" offset="0x0049" size="1">
          <bitfield caption="LF Data FIFO Synchronous Clock Status" mask="0x02" name="LDFSCKS"/>
          <bitfield caption="LF Data FIFO Synchronous Clock Switch" mask="0x01" name="LDFSCSW"/>
        </register>
        <register caption="LF Data FIFO Data Register" name="LDFD" offset="0x0039" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="LF Data FIFO Fill Level Register" name="LDFFL" offset="0x0038" size="1">
          <bitfield caption="LF Data FIFO Clear" mask="0x80" name="LDFCLR"/>
          <bitfield caption="LF Data Fifo Fill Level" mask="0x3F" name="LDFFL"/>
        </register>
        <register caption="LF Data FIFO Interrupt Mask Register" name="LDFIM" offset="0x01D6" size="1">
          <bitfield caption="LF Data FIFO Error Interrupt Mask" mask="0x02" name="LDFEIM"/>
          <bitfield caption="LF Data FIFO Fill-level Interrupt Mask" mask="0x01" name="LDFFLIM"/>
        </register>
        <register caption="LF Data FIFO Read Pointer" name="LDFRP" offset="0x01D4" size="1">
          <bitfield caption="LF Data FIFO Read Pointer" mask="0x3F" name="LDFRP"/>
        </register>
        <register caption="LF Data FIFO Status Register" name="LDFS" offset="0x01D1" size="1">
          <bitfield caption="LF Data FIFO OverFlow flag" mask="0x04" name="LDFOF"/>
          <bitfield caption="LF Data FIFO UnderFlow flag" mask="0x02" name="LDFUF"/>
          <bitfield caption="LF Data FIFO Fill-Level Reached flag" mask="0x01" name="LDFFLR"/>
        </register>
        <register caption="LF Data FIFO Write Pointer" name="LDFWP" offset="0x01D3" size="1">
          <bitfield caption="LF Data FIFO Write Pointer bit 5" mask="0x3F" name="LDFWP"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="LF_PROTOCOL_HANDLER">
      <register-group caption="" name="LF_PROTOCOL_HANDLER">
        <register caption="Protocol Handler Bit Counter Read Register" name="PHBCRR" offset="0x0188" size="1" mask="0xFF"/>
        <register caption="Protocol Handler CRC Control Register" name="PHCRCR" offset="0x01D9" size="1">
          <bitfield caption="CRC Enable" mask="0x80" name="CRCEN"/>
          <bitfield caption="CRC size bit 1" mask="0x20" name="CRCSE1"/>
          <bitfield caption="CRC size bit 0" mask="0x10" name="CRCSE0"/>
          <bitfield caption="CRC ID Frame" mask="0x04" name="CRCFR"/>
        </register>
        <register caption="PH CRC Polynomial Register" name="PHCRP" offset="0x01DC" size="2" mask="0xFFFF"/>
        <register caption="PH CRC Checksum Register" name="PHCSR" offset="0x01DE" size="2" mask="0xFFFF"/>
        <register caption="PH CRC Start Value Register" name="PHCST" offset="0x01DA" size="2" mask="0xFFFF"/>
        <register caption="Protocol Handler Data Frame end Register" name="PHDFR" offset="0x01A5" size="1" mask="0xFF"/>
        <register caption="Protocol Handler Flag Register" name="PHFR" offset="0x003B" size="1">
          <bitfield caption="Protocol Handler IDentifier 1 Flag" mask="0x20" name="PHID1F"/>
          <bitfield caption="Protocol Handler IDentifier 0 Flag" mask="0x10" name="PHID0F"/>
          <bitfield caption="Protocol Handler ID Frame Flag" mask="0x08" name="PHIDFF"/>
          <bitfield caption="Protocol Handler Date Frame Flag" mask="0x04" name="PHDFF"/>
          <bitfield caption="Protocol Handler Telegram Bit Length Flag" mask="0x02" name="PHTBLF"/>
          <bitfield caption="PH CRC Error Status Flag" mask="0x01" name="CRCEF"/>
        </register>
        <register caption="PH ID0 Register" name="PHID0" offset="0x0190" size="4" mask="0xFFFFFFFF"/>
        <register caption="PH Identifier 0 Length Register" name="PHID0L" offset="0x0194" size="1" mask="0x3F"/>
        <register caption="PH ID1 Register" name="PHID1" offset="0x0195" size="4" mask="0xFFFFFFFF"/>
        <register caption="PH Identifier 1 Length Register" name="PHID1L" offset="0x0199" size="1" mask="0x3F"/>
        <register caption="Protocol Handler ID Frame Register" name="PHIDFR" offset="0x019A" size="1" mask="0xFF"/>
        <register caption="Protocol Handler Interrupt Mask Register" name="PHIMR" offset="0x01D8" size="1">
          <bitfield caption="Protocol Handler IDentifier 1 Interrupt Mask" mask="0x20" name="PHID1IM"/>
          <bitfield caption="Protocol Handler IDentifier 0 Interrupt Mask" mask="0x10" name="PHID0IM"/>
          <bitfield caption="Protocol Handler ID Frame Interrupt Mask" mask="0x08" name="PHIDFIM"/>
          <bitfield caption="Protocol Handler Date Frame Interrupt Mask" mask="0x04" name="PHDFIM"/>
          <bitfield caption="Protocol Handler Telegram Bit Length Interrupt Mask" mask="0x02" name="PHTBLIM"/>
        </register>
        <register caption="Protocol Handler Telegram Bit Length Register" name="PHTBLR" offset="0x01A4" size="1" mask="0xFF"/>
        <register caption="PH Telegram Configuration Register" name="PHTCR" offset="0x0037" size="1">
          <bitfield caption="Continue or Single receive Mode" mask="0x80" name="CSM"/>
          <bitfield caption="Continuous Pattern Mode" mask="0x40" name="CPM"/>
          <bitfield caption="ID Frame stored in FIFO" mask="0x20" name="FRFIFO"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="LF_RECEIVER">
      <register-group caption="" name="LF_RECEIVER">
        <register caption="LF Receiver Control Register 0" name="LFCR0" offset="0x004F" size="1">
          <bitfield caption="LF Receiver Reset Time" mask="0xC0" name="LFRRT" values="LFREC_RESET_TIME"/>
          <bitfield caption="LF Receiver Maximum Gain Select" mask="0x20" name="LFMG"/>
          <bitfield caption="LF Receiver Bit Rate" mask="0x18" name="LFBR" values="LFREC_BIT_RATE"/>
          <bitfield caption="LF Receiver Channel 3 Enable" mask="0x04" name="LFCE3"/>
          <bitfield caption="LF Receiver Channel 2 Enable" mask="0x02" name="LFCE2"/>
          <bitfield caption="LF Receiver Channel 1 Enable" mask="0x01" name="LFCE1"/>
        </register>
        <register caption="LF Receiver Control Register 1" name="LFCR1" offset="0x0050" size="1">
          <bitfield caption="LF Receiver Enable" mask="0x80" name="LFRE"/>
          <bitfield caption="LF Port Event Enable" mask="0x40" name="LFPEEN"/>
          <bitfield caption="Adapt Threshold Enable" mask="0x20" name="ADTHEN"/>
          <bitfield caption="FLL Enable" mask="0x10" name="FLLEN"/>
          <bitfield caption="Analog Reset Manchester Detector Enable" mask="0x08" name="ARMDE"/>
          <bitfield caption="LF Function Mode bit 1" mask="0x04" name="LFFM1"/>
          <bitfield caption="RSSI Startup Time" mask="0x03" name="RSST" values="LFREC_RSSI_RESET_TIME"/>
        </register>
        <register caption="LF Receiver Control Register 2" name="LFCR2" offset="0x005A" size="1">
          <bitfield caption="LF Velocity Control" mask="0xE0" name="LFVC"/>
          <bitfield caption="LF coil Damping level select" mask="0x04" name="LFDAMP"/>
          <bitfield caption="LF Sensitivity Mode" mask="0x03" name="LFSEN" values="LFREC_SENSITIVITY_MODE"/>
        </register>
        <register caption="LF Receiver Control Register 3" name="LFCR3" offset="0x005B" size="1">
          <bitfield caption="LF Standby mode Enable" mask="0x80" name="LFSBEN"/>
          <bitfield caption="LF Standby Time" mask="0x70" name="LFTS" values="LFREC_STANDBY_TIME"/>
          <bitfield caption="LF On Time with Activated Standby Mode" mask="0x08" name="LFTON"/>
          <bitfield caption="LF RC Pump mode Enable" mask="0x04" name="LFRCPM"/>
          <bitfield caption="LF RC Pump Continuous Enable" mask="0x02" name="LFRCPCEN"/>
          <bitfield caption="LF RC Trim Enable" mask="0x01" name="LFRCTEN"/>
        </register>
        <register caption="LF Receiver Decoder Setting Register 1" name="LFDSR1" offset="0x0130" size="1">
          <bitfield caption="Count Threshold A" mask="0x30" name="CTTHA"/>
          <bitfield caption="High Threshold A" mask="0x0C" name="HITHA"/>
          <bitfield caption="Low Threshold A" mask="0x03" name="LOTHA"/>
        </register>
        <register caption="LF Decoder Setting 10 Register" name="LFDSR10" offset="0x0139" size="1">
          <bitfield caption="Stop Bit Correlator Threshold" mask="0xC0" name="STBTH"/>
          <bitfield caption="Frequency Control Limit" mask="0x3F" name="FCL"/>
        </register>
        <register caption="Low Frequency Decoder Setting Register 11" name="LFDSR11" offset="0x013A" size="1">
          <bitfield caption="Time Init B" mask="0xF0" name="TINITB"/>
          <bitfield caption="Time Init A" mask="0x0F" name="TINITA"/>
        </register>
        <register caption="LF Receiver Decoder Setting Register 2" name="LFDSR2" offset="0x0131" size="1">
          <bitfield caption="Count Threshold B" mask="0x30" name="CTTHB"/>
          <bitfield caption="High Threshold B" mask="0x0C" name="HITHB"/>
          <bitfield caption="Low Threshold B" mask="0x03" name="LOTHB"/>
        </register>
        <register caption="LF Receiver Decoder Setting Register 3" name="LFDSR3" offset="0x0132" size="1">
          <bitfield caption="Quality Check Threshold" mask="0x38" name="QCTH"/>
          <bitfield caption="Preburst Detection Threshold" mask="0x03" name="PBDTH"/>
        </register>
        <register caption="LF Receiver Decoder Setting Register 4" name="LFDSR4" offset="0x0133" size="1">
          <bitfield caption="Sync Restart Control" mask="0xC0" name="SRSTC"/>
          <bitfield caption="Sync Count Threshold A" mask="0x38" name="SCTHA"/>
          <bitfield caption="Sync Detection Threshold A" mask="0x07" name="SDTHA"/>
        </register>
        <register caption="LF Decoder Setting 5 Register" name="LFDSR5" offset="0x0134" size="1">
          <bitfield caption="Snyc Start-Up Time B" mask="0x80" name="SSUTB"/>
          <bitfield caption="Snyc Start-Up Time A" mask="0x40" name="SSUTA"/>
          <bitfield caption="Sync Count Threshold B" mask="0x38" name="SCTHB"/>
          <bitfield caption="Sync Detection Threshold B" mask="0x07" name="SDTHB"/>
        </register>
        <register caption="LF Decoder Setting 6 Register" name="LFDSR6" offset="0x0135" size="1">
          <bitfield caption="Time Out Timer Delta Sync detect" mask="0x38" name="TODS"/>
          <bitfield caption="Time Out Decode Unit" mask="0x07" name="TODU"/>
        </register>
        <register caption="LF Decoder Setting 7 Register" name="LFDSR7" offset="0x0136" size="1">
          <bitfield caption="FLL Manchester Detector Gain" mask="0xC0" name="MDG"/>
          <bitfield caption="FLL Manchester Detector Speed" mask="0x30" name="MDSP"/>
          <bitfield caption="FLL Preburst Gain" mask="0x0C" name="PBG"/>
          <bitfield caption="FLL Preburst Speed" mask="0x03" name="PBSP"/>
        </register>
        <register caption="LF Decoder Setting 8 Register" name="LFDSR8" offset="0x0137" size="1">
          <bitfield caption="Adaptive Switch Threshold" mask="0x70" name="ASWTH"/>
          <bitfield caption="Loop Gain Fading Enable" mask="0x08" name="LGFE"/>
          <bitfield caption="Counter Limit Delta" mask="0x07" name="CLD"/>
        </register>
        <register caption="LF Decoder Setting 9 Register" name="LFDSR9" offset="0x0138" size="1">
          <bitfield caption="Step Width" mask="0x1F" name="STW"/>
        </register>
        <register caption="LF Receiver Flag Register" name="LFFR" offset="0x003C" size="1">
          <bitfield caption="LF Envelope Signal" mask="0x80" name="LFES"/>
          <bitfield caption="LF Signal Detect" mask="0x40" name="LFSD"/>
          <bitfield caption="LF telegram Time Out Flag" mask="0x08" name="LFTOF"/>
          <bitfield caption="LF End of Telegram Flag" mask="0x04" name="LFEOF"/>
          <bitfield caption="LF Decoder Error Flag" mask="0x02" name="LFDEF"/>
          <bitfield caption="LF Synchronization Detect Flag" mask="0x01" name="LFSYDF"/>
        </register>
        <register caption="LF Receiver Interrupt Mask Register" name="LFIMR" offset="0x018F" size="1">
          <bitfield caption="LF End Of telegram Interrupt Mask" mask="0x04" name="LFEOIM"/>
          <bitfield caption="LF Decoder Error Interrupt Mask" mask="0x02" name="LFDEIM"/>
          <bitfield caption="LF Synchronization Detected Interrupt Mask" mask="0x01" name="LFSYDIM"/>
        </register>
        <register caption="LF Receiver Channel 1 Quality Faktor Register" name="LFQC1" offset="0x01A9" size="1">
          <bitfield caption="LF capacitor select channel 1" mask="0xF0" name="LFCS1"/>
          <bitfield caption="LF resistor select channel 1" mask="0x0F" name="LFQS1"/>
        </register>
        <register caption="LF Receiver Channel 2 Quality Faktor Register" name="LFQC2" offset="0x01A8" size="1">
          <bitfield caption="LF capacitor select channel 2" mask="0xF0" name="LFCS2"/>
          <bitfield caption="LF resistor select channel 2" mask="0x0F" name="LFQS2"/>
        </register>
        <register caption="LF Receiver Channel 3 Quality Faktor Register" name="LFQC3" offset="0x01A7" size="1">
          <bitfield caption="LF capacitor select channel 3" mask="0xF0" name="LFCS3"/>
          <bitfield caption="LF resistor select channel 3" mask="0x0F" name="LFQS3"/>
        </register>
        <register caption="LF Receiver SRC Tuning LSB" name="LFSRCTL" offset="0x015C" size="1">
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x01" name="LFSRCT0"/>
        </register>
        <register caption="LF Receiver SRC Tuning MSB" name="LFSRCTM" offset="0x0151" size="1">
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x80" name="LFSRCT8"/>
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x40" name="LFSRCT7"/>
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x20" name="LFSRCT6"/>
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x10" name="LFSRCT5"/>
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x08" name="LFSRCT4"/>
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x04" name="LFSRCT3"/>
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x02" name="LFSRCT2"/>
          <bitfield caption="LF Receiver SRC Tuning Tuning value" mask="0x01" name="LFSRCT1"/>
        </register>
        <register caption="LF Receiver Stop Bit Register" name="LFSTOP" offset="0x01A0" size="1">
          <bitfield caption="LF Stop Bits Length" mask="0x70" name="LFSTL"/>
          <bitfield caption="LF Stop Bits Symbols" mask="0x0F" name="LFSTSY"/>
        </register>
        <register caption="LF Receiver Synchronization Length Register" name="LFSYLE" offset="0x019F" size="1">
          <bitfield caption="" mask="0x3F" name="LFSYLE"/>
        </register>
        <register caption="LF Receiver Synchronization Symbols Register" name="LFSYSY" offset="0x019B" size="4" mask="0xFFFFFFFF"/>
      </register-group>
      <value-group caption="" name="LFREC_RESET_TIME">
        <value caption="128 us" name="VAL_0x00" value="0x00"/>
        <value caption="160 us" name="VAL_0x01" value="0x01"/>
        <value caption="192 us" name="VAL_0x02" value="0x02"/>
        <value caption="224 us" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="LFREC_BIT_RATE">
        <value caption="1.95 kBit/s" name="VAL_0x00" value="0x00"/>
        <value caption="3.90 kBit/s" name="VAL_0x01" value="0x01"/>
        <value caption="7.81 kBit/s" name="VAL_0x02" value="0x02"/>
      </value-group>
      <value-group caption="" name="LFREC_RSSI_RESET_TIME">
        <value caption="256 us" name="VAL_0x00" value="0x00"/>
        <value caption="384 us" name="VAL_0x01" value="0x01"/>
        <value caption="512 us" name="VAL_0x02" value="0x02"/>
        <value caption="640 us" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="LFREC_SENSITIVITY_MODE">
        <value caption="High Sensitivity" name="VAL_0x00" value="0x00"/>
        <value caption="Medium Sensitivity" name="VAL_0x01" value="0x01"/>
        <value caption="Low Sensitivity" name="VAL_0x02" value="0x02"/>
      </value-group>
      <value-group caption="" name="LFREC_STANDBY_TIME">
        <value caption=" 384 us" name="VAL_0x00" value="0x00"/>
        <value caption=" 768 us" name="VAL_0x01" value="0x01"/>
        <value caption="1152 us" name="VAL_0x02" value="0x02"/>
        <value caption="1536 us" name="VAL_0x03" value="0x03"/>
        <value caption="2304 us" name="VAL_0x04" value="0x04"/>
        <value caption="3072 us" name="VAL_0x05" value="0x05"/>
        <value caption="4608 us" name="VAL_0x06" value="0x06"/>
        <value caption="6144 us" name="VAL_0x07" value="0x07"/>
      </value-group>
    </module>
    <module caption="" name="LF_RSSI">
      <register-group caption="" name="LF_RSSI">
        <register caption="RSSI Calibration Register" name="RSCALIB" offset="0x01B6" size="1">
          <bitfield caption="RSSI Calibration Bit 7" mask="0x80" name="RSCALIB7"/>
          <bitfield caption="RSSI Calibration Bit 6" mask="0x40" name="RSCALIB6"/>
          <bitfield caption="RSSI Calibration Bit 5" mask="0x20" name="RSCALIB5"/>
          <bitfield caption="RSSI Calibration Bit 4" mask="0x10" name="RSCALIB4"/>
          <bitfield caption="RSSI Calibration Bit 3" mask="0x08" name="RSCALIB3"/>
          <bitfield caption="RSSI Calibration Bit 2" mask="0x04" name="RSCALIB2"/>
          <bitfield caption="RSSI Calibration Bit 1" mask="0x02" name="RSCALIB1"/>
          <bitfield caption="RSSI Calibration Bit 0" mask="0x01" name="RSCALIB0"/>
        </register>
        <register caption="RSSI Control Register" name="RSCR" offset="0x01B0" size="1">
          <bitfield caption="RSSI Reset Bit" mask="0x80" name="RSRES"/>
          <bitfield caption="RSSI Mode Bit 1" mask="0x20" name="RSMODE1"/>
          <bitfield caption="RSSI Mode Bit 0" mask="0x10" name="RSMODE0"/>
          <bitfield caption="RSSI Operation Flag Mask Bit" mask="0x08" name="RSOFM"/>
          <bitfield caption="RSSI End Operation Request Bit" mask="0x04" name="RSEOR"/>
          <bitfield caption="RSSI Operation Start Bit" mask="0x02" name="RSOS"/>
          <bitfield caption="RSSI Sign Detection Enable Bit" mask="0x01" name="RSSDEN"/>
        </register>
        <register caption="RSSI Debug Register" name="RSDBGR" offset="0x01C5" size="1">
          <bitfield caption="RSSI Debug Enable Bit" mask="0x80" name="RSDBGEN"/>
          <bitfield caption="RSSI Debug Select Bit 1" mask="0x40" name="RSDBGS1"/>
          <bitfield caption="RSSI Debug Select Bit 0" mask="0x20" name="RSDBGS0"/>
          <bitfield caption="RSSI Hold Measurement Bit" mask="0x10" name="RSHOME"/>
          <bitfield caption="RSSI Fix Pre-Divider Bit" mask="0x08" name="RSFPD"/>
          <bitfield caption="RSSI Infinity Measurement Bit" mask="0x04" name="RSINFM"/>
          <bitfield caption="RSSI Set Analog Bit" mask="0x01" name="RSSANA"/>
        </register>
        <register caption="RSSI Delay Register" name="RSDLYR" offset="0x01B7" size="1">
          <bitfield caption="RSSI Range Delay Bit 1" mask="0x80" name="RSRD1"/>
          <bitfield caption="RSSI Range Delay Bit 0" mask="0x40" name="RSRD0"/>
          <bitfield caption="RSSI Tracking Delay Bit 5" mask="0x20" name="RSTRD5"/>
          <bitfield caption="RSSI Tracking Delay Bit 4" mask="0x10" name="RSTRD4"/>
          <bitfield caption="RSSI Tracking Delay Bit 3" mask="0x08" name="RSTRD3"/>
          <bitfield caption="RSSI Tracking Delay Bit 2" mask="0x04" name="RSTRD2"/>
          <bitfield caption="RSSI Tracking Delay Bit 1" mask="0x02" name="RSTRD1"/>
          <bitfield caption="RSSI Tracking Delay Bit 0" mask="0x01" name="RSTRD0"/>
        </register>
        <register caption="RSSI Flag Register" name="RSFR" offset="0x01B4" size="1">
          <bitfield caption="RSSI Averaging Out of Range Channel 3 Bit" mask="0x80" name="RSAOOR3"/>
          <bitfield caption="RSSI Averaging Out of Range Channel 2 Bit" mask="0x40" name="RSAOOR2"/>
          <bitfield caption="RSSI Averaging Out of Range Channel 1 Bit" mask="0x20" name="RSAOOR1"/>
          <bitfield caption="RSSI Operation Finish Flag Bit" mask="0x08" name="RSOFF"/>
          <bitfield caption="RSSI Out of Range Channel 3 Bit" mask="0x04" name="RSOOR3"/>
          <bitfield caption="RSSI Out of Range Channel 2 Bit" mask="0x02" name="RSOOR2"/>
          <bitfield caption="RSSI Out of Range Channel 1 Bit" mask="0x01" name="RSOOR1"/>
        </register>
        <register caption="RSSI Measurement Setting 1 Register" name="RSMS1R" offset="0x01B2" size="1">
          <bitfield caption="RSSI Set Calibration Bit" mask="0x80" name="RSSCAL"/>
          <bitfield caption="RSSI Show Sample Value Bit" mask="0x40" name="RSSSV"/>
          <bitfield caption="RSSI Current Mode Select Bit" mask="0x20" name="RSCMS"/>
          <bitfield caption="RSSI Stimulus Bit" mask="0x10" name="RSSTIM"/>
          <bitfield caption="RSSI internal Measurement Bit" mask="0x08" name="RSINTM"/>
          <bitfield caption="RSSI Channel 3 Enable Bit" mask="0x04" name="RSCH3E"/>
          <bitfield caption="RSSI Channel 2 Enable Bit" mask="0x02" name="RSCH2E"/>
          <bitfield caption="RSSI Channel 1 Enable Bit" mask="0x01" name="RSCH1E"/>
        </register>
        <register caption="RSSI Measurement Setting 2 Register" name="RSMS2R" offset="0x01B3" size="1">
          <bitfield caption="RSSI Average Select Bit 3" mask="0x80" name="RSAVGS3"/>
          <bitfield caption="RSSI Average Select Bit 2" mask="0x40" name="RSAVGS2"/>
          <bitfield caption="RSSI Average Select Bit 1" mask="0x20" name="RSAVGS1"/>
          <bitfield caption="RSSI Average Select Bit 0" mask="0x10" name="RSAVGS0"/>
          <bitfield caption="RSSI Sample Address Bit 3" mask="0x08" name="RSSADR3"/>
          <bitfield caption="RSSI Sample Address Bit 2" mask="0x04" name="RSSADR2"/>
          <bitfield caption="RSSI Sample Address Bit 1" mask="0x02" name="RSSADR1"/>
          <bitfield caption="RSSI Sample Address Bit 0" mask="0x01" name="RSSADR0"/>
        </register>
        <register caption="RSSI Result 1 High Byte Register" name="RSRES1H" offset="0x01B9" size="1">
          <bitfield caption="RSSI Result 1 High Byte Bit 7" mask="0x80" name="RSRES1H7"/>
          <bitfield caption="RSSI Result 1 High Byte Bit 6" mask="0x40" name="RSRES1H6"/>
          <bitfield caption="RSSI Result 1 High Byte Bit 5" mask="0x20" name="RSRES1H5"/>
          <bitfield caption="RSSI Result 1 High Byte Bit 4" mask="0x10" name="RSRES1H4"/>
          <bitfield caption="RSSI Result 1 High Byte Bit 3" mask="0x08" name="RSRES1H3"/>
          <bitfield caption="RSSI Result 1 High Byte Bit 2" mask="0x04" name="RSRES1H2"/>
          <bitfield caption="RSSI Result 1 High Byte Bit 1" mask="0x02" name="RSRES1H1"/>
          <bitfield caption="RSSI Result 1 High Byte Bit 0" mask="0x01" name="RSRES1H0"/>
        </register>
        <register caption="RSSI Result 1 Low Byte Register" name="RSRES1L" offset="0x01B8" size="1">
          <bitfield caption="RSSI Result 1 Low Byte Bit 7" mask="0x80" name="RSRES1L7"/>
          <bitfield caption="RSSI Result 1 Low Byte Bit 6" mask="0x40" name="RSRES1L6"/>
          <bitfield caption="RSSI Result 1 Low Byte Bit 5" mask="0x20" name="RSRES1L5"/>
          <bitfield caption="RSSI Result 1 Low Byte Bit 4" mask="0x10" name="RSRES1L4"/>
          <bitfield caption="RSSI Result 1 Low Byte Bit 3" mask="0x08" name="RSRES1L3"/>
          <bitfield caption="RSSI Result 1 Low Byte Bit 2" mask="0x04" name="RSRES1L2"/>
          <bitfield caption="RSSI Result 1 Low Byte Bit 1" mask="0x02" name="RSRES1L1"/>
          <bitfield caption="RSSI Result 1 Low Byte Bit 0" mask="0x01" name="RSRES1L0"/>
        </register>
        <register caption="RSSI Result 2 High Byte Register" name="RSRES2H" offset="0x01BB" size="1">
          <bitfield caption="RSSI Result 2 High Byte Bit 7" mask="0x80" name="RSRES2H7"/>
          <bitfield caption="RSSI Result 2 High Byte Bit 6" mask="0x40" name="RSRES2H6"/>
          <bitfield caption="RSSI Result 2 High Byte Bit 5" mask="0x20" name="RSRES2H5"/>
          <bitfield caption="RSSI Result 2 High Byte Bit 4" mask="0x10" name="RSRES2H4"/>
          <bitfield caption="RSSI Result 2 High Byte Bit 3" mask="0x08" name="RSRES2H3"/>
          <bitfield caption="RSSI Result 2 High Byte Bit 2" mask="0x04" name="RSRES2H2"/>
          <bitfield caption="RSSI Result 2 High Byte Bit 1" mask="0x02" name="RSRES2H1"/>
          <bitfield caption="RSSI Result 2 High Byte Bit 0" mask="0x01" name="RSRES2H0"/>
        </register>
        <register caption="RSSI Result 2 Low Byte Register" name="RSRES2L" offset="0x01BA" size="1">
          <bitfield caption="RSSI Result 2 Low Byte Bit 7" mask="0x80" name="RSRES2L7"/>
          <bitfield caption="RSSI Result 2 Low Byte Bit 6" mask="0x40" name="RSRES2L6"/>
          <bitfield caption="RSSI Result 2 Low Byte Bit 5" mask="0x20" name="RSRES2L5"/>
          <bitfield caption="RSSI Result 2 Low Byte Bit 4" mask="0x10" name="RSRES2L4"/>
          <bitfield caption="RSSI Result 2 Low Byte Bit 3" mask="0x08" name="RSRES2L3"/>
          <bitfield caption="RSSI Result 2 Low Byte Bit 2" mask="0x04" name="RSRES2L2"/>
          <bitfield caption="RSSI Result 2 Low Byte Bit 1" mask="0x02" name="RSRES2L1"/>
          <bitfield caption="RSSI Result 2 Low Byte Bit 0" mask="0x01" name="RSRES2L0"/>
        </register>
        <register caption="RSSI Result 3 High Byte Register" name="RSRES3H" offset="0x01BD" size="1">
          <bitfield caption="RSSI Result 3 High Byte Bit 7" mask="0x80" name="RSRES3H7"/>
          <bitfield caption="RSSI Result 3 High Byte Bit 6" mask="0x40" name="RSRES3H6"/>
          <bitfield caption="RSSI Result 3 High Byte Bit 5" mask="0x20" name="RSRES3H5"/>
          <bitfield caption="RSSI Result 3 High Byte Bit 4" mask="0x10" name="RSRES3H4"/>
          <bitfield caption="RSSI Result 3 High Byte Bit 3" mask="0x08" name="RSRES3H3"/>
          <bitfield caption="RSSI Result 3 High Byte Bit 2" mask="0x04" name="RSRES3H2"/>
          <bitfield caption="RSSI Result 3 High Byte Bit 1" mask="0x02" name="RSRES3H1"/>
          <bitfield caption="RSSI Result 3 High Byte Bit 0" mask="0x01" name="RSRES3H0"/>
        </register>
        <register caption="RSSI Result 3 Low Byte Register" name="RSRES3L" offset="0x01BC" size="1">
          <bitfield caption="RSSI Result 3 Low Byte Bit 7" mask="0x80" name="RSRES3L7"/>
          <bitfield caption="RSSI Result 3 Low Byte Bit 6" mask="0x40" name="RSRES3L6"/>
          <bitfield caption="RSSI Result 3 Low Byte Bit 5" mask="0x20" name="RSRES3L5"/>
          <bitfield caption="RSSI Result 3 Low Byte Bit 4" mask="0x10" name="RSRES3L4"/>
          <bitfield caption="RSSI Result 3 Low Byte Bit 3" mask="0x08" name="RSRES3L3"/>
          <bitfield caption="RSSI Result 3 Low Byte Bit 2" mask="0x04" name="RSRES3L2"/>
          <bitfield caption="RSSI Result 3 Low Byte Bit 1" mask="0x02" name="RSRES3L1"/>
          <bitfield caption="RSSI Result 3 Low Byte Bit 0" mask="0x01" name="RSRES3L0"/>
        </register>
        <register caption="RSSI Result 4 High Byte Register" name="RSRES4H" offset="0x01BF" size="1">
          <bitfield caption="RSSI Result 4 High Byte Bit 7" mask="0x80" name="RSRES4H7"/>
          <bitfield caption="RSSI Result 4 High Byte Bit 6" mask="0x40" name="RSRES4H6"/>
          <bitfield caption="RSSI Result 4 High Byte Bit 5" mask="0x20" name="RSRES4H5"/>
          <bitfield caption="RSSI Result 4 High Byte Bit 4" mask="0x10" name="RSRES4H4"/>
          <bitfield caption="RSSI Result 4 High Byte Bit 3" mask="0x08" name="RSRES4H3"/>
          <bitfield caption="RSSI Result 4 High Byte Bit 2" mask="0x04" name="RSRES4H2"/>
          <bitfield caption="RSSI Result 4 High Byte Bit 1" mask="0x02" name="RSRES4H1"/>
          <bitfield caption="RSSI Result 4 High Byte Bit 0" mask="0x01" name="RSRES4H0"/>
        </register>
        <register caption="RSSI Result 4 Low Byte Register" name="RSRES4L" offset="0x01BE" size="1">
          <bitfield caption="RSSI Result 4 Low Byte Bit 7" mask="0x80" name="RSRES4L7"/>
          <bitfield caption="RSSI Result 4 Low Byte Bit 6" mask="0x40" name="RSRES4L6"/>
          <bitfield caption="RSSI Result 4 Low Byte Bit 5" mask="0x20" name="RSRES4L5"/>
          <bitfield caption="RSSI Result 4 Low Byte Bit 4" mask="0x10" name="RSRES4L4"/>
          <bitfield caption="RSSI Result 4 Low Byte Bit 3" mask="0x08" name="RSRES4L3"/>
          <bitfield caption="RSSI Result 4 Low Byte Bit 2" mask="0x04" name="RSRES4L2"/>
          <bitfield caption="RSSI Result 4 Low Byte Bit 1" mask="0x02" name="RSRES4L1"/>
          <bitfield caption="RSSI Result 4 Low Byte Bit 0" mask="0x01" name="RSRES4L0"/>
        </register>
        <register caption="RSSI Status Register" name="RSSR" offset="0x01B1" size="1">
          <bitfield caption="RSSI Sample Valid Bit" mask="0x02" name="RSSVLD"/>
          <bitfield caption="RSSI Ready Bit" mask="0x01" name="RSRDY"/>
        </register>
        <register caption="RSSI SRC Calibration Register" name="RSSRCR" offset="0x01C0" size="1">
          <bitfield caption="RSSI SRC Step Bit 1" mask="0x80" name="SRCSTEP1"/>
          <bitfield caption="RSSI SRC Step Bit 0" mask="0x40" name="SRCSTEP0"/>
          <bitfield caption="RSSI SRC Clear Bit" mask="0x10" name="SRCCLR"/>
          <bitfield caption="RSSI SRC Minimum Value Bit 1" mask="0x08" name="SRCMIN1"/>
          <bitfield caption="RSSI SRC Minimum Value Bit 0" mask="0x04" name="SRCMIN0"/>
          <bitfield caption="RSSI SRC Calibration Mode Bit 1" mask="0x02" name="SRCMODE1"/>
          <bitfield caption="RSSI SRC Calibration Mode Bit 0" mask="0x01" name="SRCMODE0"/>
        </register>
        <register caption="Sign Detection Channel 1 vs 2 Result Register" name="SD12RR" offset="0x01C1" size="1">
          <bitfield caption="Sign Detection Channel 1 vs 2 Result Bit 7" mask="0x80" name="SD12RR7"/>
          <bitfield caption="Sign Detection Channel 1 vs 2 Result Bit 6" mask="0x40" name="SD12RR6"/>
          <bitfield caption="Sign Detection Channel 1 vs 2 Result Bit 5" mask="0x20" name="SD12RR5"/>
          <bitfield caption="Sign Detection Channel 1 vs 2 Result Bit 4" mask="0x10" name="SD12RR4"/>
          <bitfield caption="Sign Detection Channel 1 vs 2 Result Bit 3" mask="0x08" name="SD12RR3"/>
          <bitfield caption="Sign Detection Channel 1 vs 2 Result Bit 2" mask="0x04" name="SD12RR2"/>
          <bitfield caption="Sign Detection Channel 1 vs 2 Result Bit 1" mask="0x02" name="SD12RR1"/>
          <bitfield caption="Sign Detection Channel 1 vs 2 Result Bit 0" mask="0x01" name="SD12RR0"/>
        </register>
        <register caption="Sign Detection Channel 1 vs 3 Result Register" name="SD13RR" offset="0x01C2" size="1">
          <bitfield caption="Sign Detection Channel 1 vs 3 Result Bit 7" mask="0x80" name="SD13RR7"/>
          <bitfield caption="Sign Detection Channel 1 vs 3 Result Bit 6" mask="0x40" name="SD13RR6"/>
          <bitfield caption="Sign Detection Channel 1 vs 3 Result Bit 5" mask="0x20" name="SD13RR5"/>
          <bitfield caption="Sign Detection Channel 1 vs 3 Result Bit 4" mask="0x10" name="SD13RR4"/>
          <bitfield caption="Sign Detection Channel 1 vs 3 Result Bit 3" mask="0x08" name="SD13RR3"/>
          <bitfield caption="Sign Detection Channel 1 vs 3 Result Bit 2" mask="0x04" name="SD13RR2"/>
          <bitfield caption="Sign Detection Channel 1 vs 3 Result Bit 1" mask="0x02" name="SD13RR1"/>
          <bitfield caption="Sign Detection Channel 1 vs 3 Result Bit 0" mask="0x01" name="SD13RR0"/>
        </register>
        <register caption="Sign Detection Channel 2 vs 3 Result Register" name="SD23RR" offset="0x01C3" size="1">
          <bitfield caption="Sign Detection Channel 2 vs 3 Result Bit 7" mask="0x80" name="SD23RR7"/>
          <bitfield caption="Sign Detection Channel 2 vs 3 Result Bit 6" mask="0x40" name="SD23RR6"/>
          <bitfield caption="Sign Detection Channel 2 vs 3 Result Bit 5" mask="0x20" name="SD23RR5"/>
          <bitfield caption="Sign Detection Channel 2 vs 3 Result Bit 4" mask="0x10" name="SD23RR4"/>
          <bitfield caption="Sign Detection Channel 2 vs 3 Result Bit 3" mask="0x08" name="SD23RR3"/>
          <bitfield caption="Sign Detection Channel 2 vs 3 Result Bit 2" mask="0x04" name="SD23RR2"/>
          <bitfield caption="Sign Detection Channel 2 vs 3 Result Bit 1" mask="0x02" name="SD23RR1"/>
          <bitfield caption="Sign Detection Channel 2 vs 3 Result Bit 0" mask="0x01" name="SD23RR0"/>
        </register>
        <register caption="Sign Detection 360 Degree Result Register" name="SD360R" offset="0x01C4" size="1">
          <bitfield caption="Sign Detection 360 Degree Result Bit 7" mask="0x80" name="SD360R7"/>
          <bitfield caption="Sign Detection 360 Degree Result Bit 6" mask="0x40" name="SD360R6"/>
          <bitfield caption="Sign Detection 360 Degree Result Bit 5" mask="0x20" name="SD360R5"/>
          <bitfield caption="Sign Detection 360 Degree Result Bit 4" mask="0x10" name="SD360R4"/>
          <bitfield caption="Sign Detection 360 Degree Result Bit 3" mask="0x08" name="SD360R3"/>
          <bitfield caption="Sign Detection 360 Degree Result Bit 2" mask="0x04" name="SD360R2"/>
          <bitfield caption="Sign Detection 360 Degree Result Bit 1" mask="0x02" name="SD360R1"/>
          <bitfield caption="Sign Detection 360 Degree Result Bit 0" mask="0x01" name="SD360R0"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="LF_TIMER">
      <register-group caption="" name="LF_TIMER">
        <register caption="LF Timer Control Mode Register" name="LTCMR" offset="0x0035" size="1">
          <bitfield caption="LF Timer Enable" mask="0x80" name="LTENA"/>
          <bitfield caption="LF Timer Start Mode" mask="0x40" name="LTSM"/>
          <bitfield caption="LF Timer Continuous Mode" mask="0x20" name="LTCM"/>
          <bitfield caption="LF Timer Compare Interrupt Mask" mask="0x10" name="LTCIM"/>
          <bitfield caption="LF Timer Compare Reset Mask" mask="0x08" name="LTCRM"/>
          <bitfield caption="LF Timer Prescaler Select bit 2" mask="0x04" name="LTPS2"/>
          <bitfield caption="LF Timer Prescaler Select bit 1" mask="0x02" name="LTPS1"/>
          <bitfield caption="LF Timer Prescaler Select bit 0" mask="0x01" name="LTPS0"/>
        </register>
        <register caption="LF Timer Compare Register" name="LTCOR" offset="0x01A1" size="1" mask="0xFF"/>
        <register caption="LF Timer Event Mask Register" name="LTEMR" offset="0x01A6" size="1">
          <bitfield caption="LF Timer Compare Flag" mask="0x80" name="LTCOF"/>
          <bitfield caption="End OF telegram Event Mask" mask="0x40" name="EOFEM"/>
          <bitfield caption="Fill Level reached Event Mask" mask="0x20" name="FLEM"/>
          <bitfield caption="Telegram Bit Length reached Event Mask" mask="0x10" name="TBLEM"/>
          <bitfield caption="Data Frame end reached Event Mask" mask="0x08" name="DFEM"/>
          <bitfield caption="Identifier Frame Event Mask" mask="0x04" name="IDFEM"/>
          <bitfield caption="ID1 Event Mask" mask="0x02" name="ID1EM"/>
          <bitfield caption="ID0 Event Mask" mask="0x01" name="ID0EM"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="LF_TRANSPONDER">
      <register-group caption="" name="LF_TRANSPONDER">
        <register caption="Transponder Control Register 1" name="TPCR1" offset="0x0165" size="1">
          <bitfield caption="Transponder Mode" mask="0x80" name="TPMODE"/>
          <bitfield caption="Transponder Decoder Field Clock Prescaler value" mask="0x60" name="TPDFCP" values="LFTP_FIELDCLK_PRESCALER"/>
          <bitfield caption="Transponder Bit Rate" mask="0x10" name="TPBR"/>
          <bitfield caption="Transponder Quadrature Pulse Length Operation Modulation" mask="0x04" name="TPQPLM"/>
        </register>
        <register caption="Transponder Control 2 Register" name="TPCR2" offset="0x002C" size="1">
          <bitfield caption="Transponder watch dog value for No Field timeout (with SRC clk)" mask="0x60" name="TPWDLV" values="LFTP_TPWDLV"/>
          <bitfield caption="Transponder No Field Timeout enable" mask="0x10" name="TPNFTO"/>
          <bitfield caption="Transponder Disable" mask="0x08" name="TPD"/>
          <bitfield caption="Transponder Power Switch Disable" mask="0x04" name="TPPSD"/>
          <bitfield caption="Transponder Modulation" mask="0x02" name="TPMOD"/>
          <bitfield caption="Transponder Mode Acknowledge" mask="0x01" name="TPMA"/>
        </register>
        <register caption="Transponder Control Register 3" name="TPCR3" offset="0x0171" size="1">
          <bitfield caption="Transponder Reception Continuous Damping" mask="0x20" name="TPRCD"/>
          <bitfield caption="Transponder Transmit Listen Window" mask="0x04" name="TPTLIW"/>
          <bitfield caption="Transponder Receive Data" mask="0x02" name="TPRD"/>
          <bitfield caption="Transponder Transmit Data" mask="0x01" name="TPTD"/>
        </register>
        <register caption="Transponder Control Register 4" name="TPCR4" offset="0x0172" size="1">
          <bitfield caption="Transponder Battery Charge Mode" mask="0x10" name="TPBCM"/>
          <bitfield caption="Transponder Battery Charge Current Select" mask="0x0F" name="TPBCCS"/>
        </register>
        <register caption="Transponder Control Register 5" name="TPCR5" offset="0x0173" size="1">
          <bitfield caption="Transponder Modulation Damping Select" mask="0x70" name="TPMD"/>
          <bitfield caption="Transponder Modulation Undamped Level Select" mask="0x07" name="TPMUD" values="LFTP_TPMUD"/>
        </register>
        <register caption="Transponder Decoder Comparator Register 1" name="TPDCR1" offset="0x0167" size="1">
          <bitfield caption="Transponder Decode Comparator Length value 1" mask="0x3F" name="TPDCL1"/>
        </register>
        <register caption="Transponder Decoder Comparator Register 2" name="TPDCR2" offset="0x0168" size="1">
          <bitfield caption="Transponder Decode Comparator Length value 2" mask="0x3F" name="TPDCL2"/>
        </register>
        <register caption="Transponder Decoder Comparator Register 3" name="TPDCR3" offset="0x0169" size="1">
          <bitfield caption="Transponder Decode Comparator Length value 3" mask="0x3F" name="TPDCL3"/>
        </register>
        <register caption="Transponder Decoder Comparator Register 4" name="TPDCR4" offset="0x016A" size="1">
          <bitfield caption="Transponder Decode Comparator Length value 4" mask="0x3F" name="TPDCL4"/>
        </register>
        <register caption="Transponder Decoder Comparator Register 5" name="TPDCR5" offset="0x016B" size="1">
          <bitfield caption="Transponder Decode Comparator Length value 5" mask="0x3F" name="TPDCL5"/>
        </register>
        <register caption="Transponder Encoder Mode Register" name="TPECMR" offset="0x0170" size="1">
          <bitfield caption="Transponder Encoder Mode 4" mask="0xC0" name="TPECM4" values="LFTP_TPECM"/>
          <bitfield caption="Transponder Encoder Mode 3" mask="0x30" name="TPECM3" values="LFTP_TPECM"/>
          <bitfield caption="Transponder Encoder Mode 2" mask="0x0C" name="TPECM2" values="LFTP_TPECM"/>
          <bitfield caption="Transponder Encoder Mode 1" mask="0x03" name="TPECM1" values="LFTP_TPECM"/>
        </register>
        <register caption="Transponder Encoder Comparator Register 1" name="TPECR1" offset="0x016C" size="1">
          <bitfield caption="Transponder Encode Comparator Length value 1" mask="0xFF" name="TPECL1"/>
        </register>
        <register caption="Transponder Encoder Comparator Register 2" name="TPECR2" offset="0x016D" size="1">
          <bitfield caption="Transponder Encode Comparator Length value 2" mask="0xFF" name="TPECL2"/>
        </register>
        <register caption="Transponder Encoder Comparator Register 3" name="TPECR3" offset="0x016E" size="1">
          <bitfield caption="Transponder Encode Comparator Length value 3" mask="0xFF" name="TPECL3"/>
        </register>
        <register caption="Transponder Encoder Comparator Register 4" name="TPECR4" offset="0x016F" size="1">
          <bitfield caption="Transponder Encode Comparator Length value 4" mask="0xFF" name="TPECL4"/>
        </register>
        <register caption="Transponder Flag Register" name="TPFR" offset="0x002D" size="1">
          <bitfield caption="Transponder Bit Error Flag" mask="0x08" name="TPBERF"/>
          <bitfield caption="Transponder No Field Timeout Flag" mask="0x04" name="TPNFTF"/>
          <bitfield caption="Transponder Field Timeout Flag" mask="0x02" name="TPFTF"/>
          <bitfield caption="Transponder Flag" mask="0x01" name="TPF"/>
        </register>
        <register caption="Transponder Interrupt Mask Register" name="TPIMR" offset="0x0166" size="1">
          <bitfield caption="Transponder Bit Error Interrupt Mask" mask="0x08" name="TPBERIM"/>
          <bitfield caption="Transponder No Field Timeout Interrupt Mask" mask="0x04" name="TPNFTIM"/>
          <bitfield caption="Transponder Field Timeout Interrupt Mask" mask="0x02" name="TPFTIM"/>
          <bitfield caption="Transponder Interrupt Mask" mask="0x01" name="TPIM"/>
        </register>
        <register caption="Transponder Status Register" name="TPSR" offset="0x0059" size="1">
          <bitfield caption="Transponder Battery Charge OK" mask="0x08" name="TPBCOK"/>
          <bitfield caption="Transponder Power Switch" mask="0x04" name="TPPSW"/>
          <bitfield caption="Transponder GAP Signal" mask="0x02" name="TPGAP"/>
          <bitfield caption="Transponder Active" mask="0x01" name="TPA"/>
        </register>
      </register-group>
      <value-group caption="" name="LFTP_FIELDCLK_PRESCALER">
        <value caption="Field Clock / 1" name="VAL_0x00" value="0x00"/>
        <value caption="Field Clock / 1" name="VAL_0x01" value="0x01"/>
        <value caption="Field Clock / 2" name="VAL_0x02" value="0x02"/>
        <value caption="Field Clock / 4" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="LFTP_TPWDLV">
        <value caption="1.024 ms" name="VAL_0x00" value="0x00"/>
        <value caption="2.048 ms" name="VAL_0x01" value="0x01"/>
        <value caption="3.072 ms" name="VAL_0x02" value="0x02"/>
        <value caption="4.096 ms" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="LFTP_TPMUD">
        <value caption="5.0 V" name="VAL_0x00" value="0x00"/>
        <value caption="5.4 V" name="VAL_0x01" value="0x01"/>
        <value caption="5.8 V" name="VAL_0x02" value="0x02"/>
        <value caption="6.2 V" name="VAL_0x03" value="0x03"/>
        <value caption="6.6 V" name="VAL_0x04" value="0x04"/>
        <value caption="7.0 V" name="VAL_0x05" value="0x05"/>
        <value caption="Up to OVP" name="VAL_0x07" value="0x07"/>
      </value-group>
      <value-group caption="" name="LFTP_TPECM">
        <value caption="Manchester" name="VAL_0x00" value="0x00"/>
        <value caption="Biphase" name="VAL_0x01" value="0x01"/>
        <value caption="NRZ" name="VAL_0x02" value="0x02"/>
        <value caption="Manchester" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="MEM">
      <register-group caption="" name="MEM">
        <register caption="EEPROM Status Register" name="EEST" offset="0x015B" size="1">
          <bitfield caption="EEPROM Syndrome" mask="0x0F" name="EESYN"/>
        </register>
        <register caption="Program Memory Status Register" name="PGMST" offset="0x015A" size="1">
          <bitfield caption="Program Memory Syndrome" mask="0x1F" name="PGMSYN"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="PORTB">
      <register-group caption="" name="PORTB">
        <register caption="Port B Data Direction Register" name="DDRB" offset="0x0024" size="1" mask="0xFF"/>
        <register caption="Port B Input Pins" name="PINB" offset="0x0023" size="1" mask="0xFF"/>
        <register caption="Port B Data Register" name="PORTB" offset="0x0025" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="PORTC">
      <register-group caption="" name="PORTC">
        <register caption="Port C Data Direction Register" name="DDRC" offset="0x0027" size="1" mask="0x07"/>
        <register caption="Port C Input Pins" name="PINC" offset="0x0026" size="1" mask="0x07"/>
        <register caption="Port C Data Register" name="PORTC" offset="0x0028" size="1" mask="0x07"/>
      </register-group>
    </module>
    <module caption="" name="PORTD">
      <register-group caption="" name="PORTD">
        <register caption="Port D Data Direction Register" name="DDRD" offset="0x002A" size="1" mask="0xFF"/>
        <register caption="Port D Input Pins" name="PIND" offset="0x0029" size="1" mask="0xFF"/>
        <register caption="Port D Data Register" name="PORTD" offset="0x002B" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="SFIFO">
      <register-group caption="" name="SFIFO">
        <register caption="Support FIFO Configuration Register" name="SFC" offset="0x00E1" size="1">
          <bitfield caption="Support FIFO Direct Read Access Operational Mode" mask="0x80" name="SFDRA"/>
          <bitfield caption="Support FIFO Fill-Level Configuration" mask="0x1F" name="SFFLC"/>
        </register>
        <register caption="Support FIFO Data Register" name="SFD" offset="0x00DF" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="Support FIFO Interrupt Mask Register" name="SFI" offset="0x00E0" size="1">
          <bitfield caption="Support FIFO Error Interrupt Mask" mask="0x02" name="SFERIM"/>
          <bitfield caption="Support FIFO Fill-level Interrupt Mask" mask="0x01" name="SFFLIM"/>
        </register>
        <register caption="Support FIFO Fill Level Register" name="SFL" offset="0x00DC" size="1">
          <bitfield caption="Support FIFO Clear" mask="0x80" name="SFCLR"/>
          <bitfield caption="Support FIFO Fill Level Status" mask="0x1F" name="SFFLS"/>
        </register>
        <register caption="Support FIFO Read Pointer" name="SFRP" offset="0x00DE" size="1" mask="0x1F"/>
        <register caption="Support FIFO Status Register" name="SFS" offset="0x00DB" size="1">
          <bitfield caption="Support FIFO Overflow Flag" mask="0x04" name="SFOFL"/>
          <bitfield caption="Support FIFO Underflow Flag" mask="0x02" name="SFUFL"/>
          <bitfield caption="Support FIFO Fill-Level Reached Status Flag" mask="0x01" name="SFFLRF"/>
        </register>
        <register caption="Support FIFO Write Pointer" name="SFWP" offset="0x00DD" size="1" mask="0x1F"/>
      </register-group>
    </module>
    <module caption="" name="SPI">
      <register-group caption="" name="SPI">
        <register caption="SPI FIFO Fill Status Register" name="SFFR" offset="0x0157" size="1">
          <bitfield caption="SPI Tx Buffer Clear" mask="0x80" name="TFC"/>
          <bitfield caption="Transmit Buffer Fill Level" mask="0x70" name="TFL"/>
          <bitfield caption="Rx Buffer Clear" mask="0x08" name="RFC"/>
          <bitfield caption="Receive Buffer Fill Level" mask="0x07" name="RFL"/>
        </register>
        <register caption="SPI FIFO Interrupt Register" name="SFIR" offset="0x0158" size="1">
          <bitfield caption="SPI Rx Buffer Interrupt Enable" mask="0x80" name="STIE"/>
          <bitfield caption="Transmit Buffer Interrupt Level" mask="0x70" name="TIL"/>
          <bitfield caption="Rx Buffer Interrupt Enable" mask="0x08" name="SRIE"/>
          <bitfield caption="Receive Buffer Interrupt Level" mask="0x07" name="RIL"/>
        </register>
        <register caption="SPI control Register" name="SPCR" offset="0x004C" size="1">
          <bitfield caption="Spe Interrupt Enable" mask="0x80" name="SPIE"/>
          <bitfield caption="SPI Enable" mask="0x40" name="SPE"/>
          <bitfield caption="Data Order" mask="0x20" name="DORD"/>
          <bitfield caption="Master/Slave Select" mask="0x10" name="MSTR"/>
          <bitfield caption="Clock Polarity" mask="0x08" name="CPOL"/>
          <bitfield caption="Clock Phase" mask="0x04" name="CPHA"/>
          <bitfield caption="SPI Clock Rate Select" mask="0x03" name="SPR" values="SPI_SPR"/>
        </register>
        <register caption="SPI Data Register" name="SPDR" offset="0x004E" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="SPI Status Register" name="SPSR" offset="0x004D" size="1">
          <bitfield caption="SPI Interrupt Flag" mask="0x80" name="SPIF"/>
          <bitfield caption="Tx Buffer Interrupt Flag" mask="0x20" name="TXIF"/>
          <bitfield caption="Rx Buffer Interrupt Flag" mask="0x10" name="RXIF"/>
          <bitfield caption="Double SPI Speed Bit" mask="0x01" name="SPI2X"/>
        </register>
      </register-group>
      <value-group caption="" name="SPI_SPR">
        <value caption="clkio/4" name="VAL_0x00" value="0x00"/>
        <value caption="clkio/16" name="VAL_0x01" value="0x01"/>
        <value caption="clkio/64" name="VAL_0x02" value="0x02"/>
        <value caption="clkio/128" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="SPI2">
      <register-group caption="" name="SPI2">
        <register caption="SPI2 control Register" name="SP2CR" offset="0x00F7" size="1">
          <bitfield caption="Spi2 Interrupt Enable" mask="0x80" name="SP2IE"/>
          <bitfield caption="SPI2 Enable" mask="0x40" name="SP2E"/>
          <bitfield caption="Data Order" mask="0x20" name="DORD2"/>
          <bitfield caption="Master/Slave Select" mask="0x10" name="MSTR2"/>
          <bitfield caption="Clock Polarity" mask="0x08" name="CPOL2"/>
          <bitfield caption="Clock Phase" mask="0x04" name="CPHA2"/>
          <bitfield caption="SPI2 Clock Rate Select" mask="0x03" name="SP2R" values="SPI2_SP2R"/>
        </register>
        <register caption="SPI2 Data Register" name="SP2DR" offset="0x00F8" size="1" mask="0xFF"/>
        <register caption="SPI2 Status Register" name="SP2SR" offset="0x00F9" size="1">
          <bitfield caption="SPI2 Interrupt Flag" mask="0x80" name="SP2IF"/>
          <bitfield caption="Write Colliion Flag" mask="0x40" name="WCOL2"/>
          <bitfield caption="Double SPI2 Speed Bit" mask="0x01" name="SPI22X"/>
        </register>
      </register-group>
      <value-group caption="" name="SPI2_SP2R">
        <value caption="clkio/4" name="VAL_0x00" value="0x00"/>
        <value caption="clkio/16" name="VAL_0x01" value="0x01"/>
        <value caption="clkio/64" name="VAL_0x02" value="0x02"/>
        <value caption="clkio/128" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="SSM">
      <register-group caption="" name="SSM">
        <register caption="Master State Machine Control Register 1" name="MSMCR1" offset="0x00EC" size="1">
          <bitfield caption="Master State Machine SubState Machine Select 0" mask="0x0F" name="MSMSM0" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine SubState Machine Select 1" mask="0xF0" name="MSMSM1" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 2" name="MSMCR2" offset="0x00ED" size="1">
          <bitfield caption="Master State Machine SubState Machine Select 2" mask="0x0F" name="MSMSM2" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine SubState Machine Select 3" mask="0xF0" name="MSMSM3" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 3" name="MSMCR3" offset="0x00EE" size="1">
          <bitfield caption="Master State Machine SubState Machine Select 4" mask="0x0F" name="MSMSM4" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine SubState Machine Select 5" mask="0xF0" name="MSMSM5" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 4" name="MSMCR4" offset="0x00EF" size="1">
          <bitfield caption="Master State Machine SubState Machine Select 6" mask="0x0F" name="MSMSM6" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine SubState Machine Select 7" mask="0xF0" name="MSMSM7" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine state register" name="MSMSTR" offset="0x00E9" size="1" ocd-rw="R">
          <bitfield caption="Sequencer State Machine Master State" mask="0x1F" name="SSMMST"/>
        </register>
        <register caption="SSM Control Register" name="SSMCR" offset="0x00E2" size="1">
          <bitfield caption="Sequencer State Machine Tx Ask-Shaping Enable" mask="0x20" name="SSMTAE"/>
          <bitfield caption="Sequencer State Machine PV Enable" mask="0x10" name="SSMPVE"/>
          <bitfield caption="Sequencer State Machine Tx Preemphasis Enable" mask="0x08" name="SSMTPE"/>
          <bitfield caption="Sequencer State Machine Tx Gauss Enable" mask="0x04" name="SSMTGE"/>
        </register>
        <register caption="SSM Filter Bandwidth Register" name="SSMFBR" offset="0x00E4" size="1">
          <bitfield caption="Sequencer State Machine PLL Lock Delay Time" mask="0x20" name="SSMPLDT"/>
        </register>
        <register caption="SSM Interrupt Flag Register" name="SSMIFR" offset="0x00E7" size="1">
          <bitfield caption="Sequencer State Machine Interrupt Flag" mask="0x01" name="SSMIF"/>
        </register>
        <register caption="SSM interrupt mask register" name="SSMIMR" offset="0x00E8" size="1">
          <bitfield caption="Sequencer State Machine Interrupt Mask" mask="0x01" name="SSMIM"/>
        </register>
        <register caption="SSM Run Register" name="SSMRR" offset="0x00E5" size="1">
          <bitfield caption="Sequencer State Machine Stop" mask="0x02" name="SSMST"/>
          <bitfield caption="Sequencer State Machine Run" mask="0x01" name="SSMR"/>
        </register>
        <register caption="SSM Status Register" name="SSMSR" offset="0x00E6" size="1">
          <bitfield caption="Sequencer State Machine Error" mask="0x80" name="SSMERR"/>
          <bitfield caption="Sequencer State Machine Error State Machine" mask="0x0F" name="SSMESM"/>
        </register>
        <register caption="SSM State Register" name="SSMSTR" offset="0x00EA" size="1" ocd-rw="R">
          <bitfield caption="Sequencer State Machine State A" mask="0x3F" name="SSMSTA"/>
        </register>
      </register-group>
      <value-group caption="" name="SSM_SUB_STATE_MACHINE">
        <value caption="None/Stop" name="VAL_0x00" value="0x00"/>
        <value caption="PLL en" name="VAL_0x01" value="0x01"/>
        <value caption="PLL lock" name="VAL_0x02" value="0x02"/>
        <value caption="TX DSP enable" name="VAL_0x03" value="0x03"/>
        <value caption="TX DSP disable" name="VAL_0x04" value="0x04"/>
        <value caption="Send telegram" name="VAL_0x05" value="0x05"/>
        <value caption="Shut down" name="VAL_0x06" value="0x06"/>
        <value caption="VCO Tuning" name="VAL_0x07" value="0x07"/>
        <value caption="Antenna Tuning" name="VAL_0x08" value="0x08"/>
      </value-group>
    </module>
    <module caption="" name="SUP">
      <register-group caption="" name="SUP">
        <register caption="Calibration ready signature" name="CALRDY" offset="0x00D1" size="1" mask="0xFF"/>
        <register caption="Calibration ready signature LFVCC" name="CALRDYLF" offset="0x01E8" size="1" mask="0xFF"/>
        <register caption="Power Management Test Enable Register" name="PMTER" offset="0x01FE" size="1" mask="0xFF"/>
        <register caption="RC oscillator Temperature Compensation register" name="RCTCAL" offset="0x00C8" size="1">
          <bitfield caption="Disable MRC Oscillator Bandgap" mask="0x10" name="DI_MRCBG"/>
          <bitfield caption="Medium frequency RC Oscillator Temperature Compensation" mask="0x0E" name="MRCTC"/>
          <bitfield caption="FRC Oscillator Temperature Compensation bit" mask="0x01" name="FRCTC"/>
        </register>
        <register caption="Supply calibration register 1" name="SUPCA1" offset="0x00CD" size="1">
          <bitfield caption="Power Amplifier Regulator Calibration" mask="0xF0" name="PVCAL"/>
          <bitfield caption="Power Amplifier Regulator Double Internal Current" mask="0x08" name="PVDIC"/>
          <bitfield caption="Power Amplifier Voltage 2.2V" mask="0x04" name="PV22"/>
        </register>
        <register caption="Supply calibration register 10" name="SUPCA10" offset="0x01F8" size="1" mask="0x1F"/>
        <register caption="Supply calibration register 2" name="SUPCA2" offset="0x00CE" size="1">
          <bitfield caption="Band Gap Calibration" mask="0x0F" name="BGCAL"/>
        </register>
        <register caption="Supply calibration register 3" name="SUPCA3" offset="0x00CF" size="1">
          <bitfield caption="AVCC Regulator Output Voltage Calibration" mask="0xFF" name="ACAL"/>
        </register>
        <register caption="Supply calibration register 4" name="SUPCA4" offset="0x00D0" size="1">
          <bitfield caption="ICONST Constant current of bandgap" mask="0x3F" name="ICONST"/>
        </register>
        <register caption="Supply calibration register 5" name="SUPCA5" offset="0x01F3" size="1">
          <bitfield caption="IPTAT current of bandgap" mask="0x3F" name="IPTAT"/>
        </register>
        <register caption="Supply calibration register 6" name="SUPCA6" offset="0x01F4" size="1">
          <bitfield caption="Threshold voltage of bandgap" mask="0xFF" name="VBGTR"/>
        </register>
        <register caption="Supply calibration register 7" name="SUPCA7" offset="0x01F5" size="1">
          <bitfield caption="VREF voltage for LFVCC Brown-out-Detector" mask="0x38" name="LFVCCBD"/>
          <bitfield caption="LFVCC and DVCC Output Voltage Calibration" mask="0x07" name="VCCCAL"/>
        </register>
        <register caption="Supply calibration register 8" name="SUPCA8" offset="0x01F6" size="1">
          <bitfield caption="VREF voltage for DVCC Brown-out-Detector" mask="0x38" name="DVCCBD"/>
          <bitfield caption="VSIG voltage for LFVCC Brown-out-Detector" mask="0x07" name="VSWBD"/>
        </register>
        <register caption="Supply calibration register 9" name="SUPCA9" offset="0x01F7" size="1">
          <bitfield caption="VMEM ldo voltage" mask="0xFF" name="VMEM"/>
        </register>
        <register caption="Supply Control Register" name="SUPCR" offset="0x00CC" size="1">
          <bitfield caption="Memory Voltage Regulator Enable" mask="0x80" name="VMEMEN"/>
          <bitfield caption="VMEM Reset Mask" mask="0x40" name="VMRESM"/>
          <bitfield caption="DVCC High Current Mode Enable" mask="0x20" name="DVHEN"/>
          <bitfield caption="AVCC Enable" mask="0x10" name="AVEN"/>
          <bitfield caption="AVCC Double Internal Current" mask="0x08" name="AVDIC"/>
          <bitfield caption="Power amplifier Voltage supply Enable" mask="0x04" name="PVEN"/>
          <bitfield caption="AVCC Low Interrupt Mask" mask="0x02" name="AVCCLM"/>
          <bitfield caption="AVCC Reset Interrupt Mask" mask="0x01" name="AVCCRM"/>
        </register>
        <register caption="Supply Interrupt Flag Register" name="SUPFR" offset="0x00CB" size="1">
          <bitfield caption="AVCC low interrupt flag" mask="0x02" name="AVCCLF"/>
          <bitfield caption="AVCC reset interrupt flag" mask="0x01" name="AVCCRF"/>
        </register>
        <register caption="Voltage Monitor Control Register" name="VMCR" offset="0x01E6" size="1">
          <bitfield caption="Voltage Monitor Range Select" mask="0x80" name="VMRS"/>
          <bitfield caption="Voltage Monitor Power Supply Select" mask="0x60" name="VMPS"/>
          <bitfield caption="Voltage Monitor Interrupt Mask" mask="0x10" name="VMIM"/>
          <bitfield caption="Voltage Monitor Level Select" mask="0x0F" name="VMLS"/>
        </register>
        <register caption="Voltage Monitor Status and Control Register" name="VMSCR" offset="0x004A" size="1">
          <bitfield caption="Voltage Monitor Disable Hysteresis" mask="0x02" name="VMDIH"/>
          <bitfield caption="Voltage Monitor Flag" mask="0x01" name="VMF"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="TIMER0_WDT">
      <register-group caption="" name="TIMER0_WDT">
        <register caption="Timer0 Control Register" name="T0CR" offset="0x0162" size="1">
          <bitfield caption="Timer0 Prescaler Reset" mask="0x10" name="T0PR"/>
          <bitfield caption="Timer0 Interrupt Enable" mask="0x08" name="T0IE"/>
          <bitfield caption="Timer0 Prescaler Select" mask="0x07" name="T0PS" values="TIM0_PS_SELECT"/>
        </register>
        <register caption="Timer0 Interrupt Flag Register" name="T0IFR" offset="0x0052" size="1">
          <bitfield caption="Timer0 Flag" mask="0x01" name="T0F"/>
        </register>
        <register caption="Watchdog Timer0 control Register" name="WDTCR" offset="0x006E" size="1">
          <bitfield caption="Watchdog Change Enable" mask="0x10" name="WDCE"/>
          <bitfield caption="Watchdog System Reset Enable" mask="0x08" name="WDE"/>
          <bitfield caption="Watchdog Prescaler Select" mask="0x07" name="WDPS" values="TIM0_WDPS_SELECT"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM0_PS_SELECT">
        <value caption="0.256ms typ" name="VAL_0x00" value="0x00"/>
        <value caption="1ms typ" name="VAL_0x01" value="0x01"/>
        <value caption="8ms typ" name="VAL_0x02" value="0x02"/>
        <value caption="0.5s typ" name="VAL_0x03" value="0x03"/>
        <value caption="1s typ" name="VAL_0x04" value="0x04"/>
        <value caption="8s typ" name="VAL_0x05" value="0x05"/>
        <value caption="67s typ" name="VAL_0x06" value="0x06"/>
        <value caption="134s typ" name="VAL_0x07" value="0x07"/>
      </value-group>
      <value-group caption="" name="TIM0_WDPS_SELECT">
        <value caption="1ms typ (0.85ms min)" name="VAL_0x00" value="0x00"/>
        <value caption="4ms typ (3.4ms min)" name="VAL_0x01" value="0x01"/>
        <value caption="32ms typ (27ms min)" name="VAL_0x02" value="0x02"/>
        <value caption="2.1s typ (1.75s min)" name="VAL_0x03" value="0x03"/>
        <value caption="4.2s typ (3.5s min)" name="VAL_0x04" value="0x04"/>
        <value caption="16.8s typ (14s min)" name="VAL_0x05" value="0x05"/>
        <value caption="134s typ (110s min)" name="VAL_0x06" value="0x06"/>
        <value caption="268s typ (220s min)" name="VAL_0x07" value="0x07"/>
      </value-group>
    </module>
    <module caption="" name="TIMER1">
      <register-group caption="" name="TIMER1">
        <register caption="Timer1 Counter Register" name="T1CNT" offset="0x006F" size="1" mask="0xFF" ocd-rw="R"/>
        <register caption="Timer1 Compare Register" name="T1COR" offset="0x0070" size="1" mask="0xFF"/>
        <register caption="Timer1 control Register" name="T1CR" offset="0x0031" size="1">
          <bitfield caption="Timer1 Enable" mask="0x80" name="T1ENA"/>
          <bitfield caption="Timer1 Toggle with Start" mask="0x40" name="T1TOS"/>
          <bitfield caption="Timer1 Reset" mask="0x20" name="T1RES"/>
          <bitfield caption="Timer1 Toggle Output Preset" mask="0x10" name="T1TOP"/>
          <bitfield caption="Timer1 Compare Reset Mask" mask="0x04" name="T1CRM"/>
          <bitfield caption="Timer1 Compare Toggle Mask" mask="0x02" name="T1CTM"/>
          <bitfield caption="Timer1 Overflow Toggle Mask" mask="0x01" name="T1OTM"/>
        </register>
        <register caption="Timer1 Interrupt Flag Register" name="T1IFR" offset="0x01A2" size="1">
          <bitfield caption="Timer1 Compare Flag" mask="0x02" name="T1COF"/>
          <bitfield caption="Timer1 Overflow Flag" mask="0x01" name="T1OFF"/>
        </register>
        <register caption="Timer1 Interrupt Mask Register" name="T1IMR" offset="0x0072" size="1">
          <bitfield caption="Timer1 Compare Interrupt Mask" mask="0x02" name="T1CIM"/>
          <bitfield caption="Timer1 Overflow Interrupt Mask" mask="0x01" name="T1OIM"/>
        </register>
        <register caption="Timer1 Mode Register" name="T1MR" offset="0x0071" size="1">
          <bitfield caption="Timer1 Duty Cycle" mask="0xC0" name="T1DC" values="TIM1_DC_SELECT"/>
          <bitfield caption="Timer1 Prescaler Select" mask="0x3C" name="T1PS"/>
          <bitfield caption="Timer1 Clock Select" mask="0x03" name="T1CS" values="TIM1_CLOCK_SELECT"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM1_DC_SELECT">
        <value caption="Bypass" name="VAL_0x00" value="0x00"/>
        <value caption="Duty cycle 1/1 (div 2)" name="VAL_0x01" value="0x01"/>
        <value caption="Duty cycle 1/2 (div 3)" name="VAL_0x02" value="0x02"/>
        <value caption="Duty cycle 1/3 (div 4)" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TIM1_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_frc" name="VAL_0x01" value="0x01"/>
        <value caption="clk_T" name="VAL_0x02" value="0x02"/>
        <value caption="clk_mrc" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER2">
      <register-group caption="" name="TIMER2">
        <register caption="Timer2 Counter Register" name="T2CNT" offset="0x0073" size="1" mask="0xFF" ocd-rw="R"/>
        <register caption="Timer2 Compare Register" name="T2COR" offset="0x0074" size="1" mask="0xFF"/>
        <register caption="Timer2 Control Register" name="T2CR" offset="0x0032" size="1">
          <bitfield caption="Timer2 Enable" mask="0x80" name="T2ENA"/>
          <bitfield caption="Timer2 Toggle with Start" mask="0x40" name="T2TOS"/>
          <bitfield caption="Timer2 Reset" mask="0x20" name="T2RES"/>
          <bitfield caption="Timer2 Toggle Output Preset" mask="0x10" name="T2TOP"/>
          <bitfield caption="Timer2 Compare Reset Mask" mask="0x04" name="T2CRM"/>
          <bitfield caption="Timer2 Compare Toggle Mask" mask="0x02" name="T2CTM"/>
          <bitfield caption="Timer2 Overflow Toggle Mask" mask="0x01" name="T2OTM"/>
        </register>
        <register caption="Timer2 Interrupt Flag Register" name="T2IFR" offset="0x0159" size="1">
          <bitfield caption="Timer2 Compare Flag" mask="0x02" name="T2COF"/>
          <bitfield caption="Timer2 Overflow Flag" mask="0x01" name="T2OFF"/>
        </register>
        <register caption="Timer2 Interrupt Mask Register" name="T2IMR" offset="0x0076" size="1">
          <bitfield caption="Timer2 Compare Interrupt Mask" mask="0x02" name="T2CIM"/>
          <bitfield caption="Timer2 Overflow Interrupt Mask" mask="0x01" name="T2OIM"/>
        </register>
        <register caption="Timer2 Mode Register" name="T2MR" offset="0x0075" size="1">
          <bitfield caption="Timer2 Duty Cycle" mask="0xC0" name="T2DC" values="TIM2_DC_SELECT"/>
          <bitfield caption="Timer2 Prescaler Select" mask="0x3C" name="T2PS"/>
          <bitfield caption="Timer2 Clock Select" mask="0x03" name="T2CS" values="TIM2_CLOCK_SELECT"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM2_DC_SELECT">
        <value caption="Bypass" name="VAL_0x00" value="0x00"/>
        <value caption="Duty cycle 1/1 (div 2)" name="VAL_0x01" value="0x01"/>
        <value caption="Duty cycle 1/2 (div 3)" name="VAL_0x02" value="0x02"/>
        <value caption="Duty cycle 1/3 (div 4)" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TIM2_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_mrc" name="VAL_0x01" value="0x01"/>
        <value caption="clk_T" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto4" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER3">
      <register-group caption="" name="TIMER3">
        <register caption="Timer3 counter Register" name="T3CNT" offset="0x0077" size="2" mask="0xFFFF" ocd-rw="R"/>
        <register caption="Timer3 compare Register" name="T3COR" offset="0x0079" size="2" mask="0xFFFF"/>
        <register caption="Timer3 control Register" name="T3CR" offset="0x0033" size="1">
          <bitfield caption="Timer3 Enable" mask="0x80" name="T3ENA"/>
          <bitfield caption="Timer3 Toggle with Start" mask="0x40" name="T3TOS"/>
          <bitfield caption="Timer3 Reset" mask="0x20" name="T3RES"/>
          <bitfield caption="Timer3 Toggle Output Preset" mask="0x10" name="T3TOP"/>
          <bitfield caption="Timer3 CaPture Reset Mask" mask="0x08" name="T3CPRM"/>
          <bitfield caption="Timer3 Compare Reset Mask" mask="0x04" name="T3CRM"/>
          <bitfield caption="Timer3 Compare Toggle Mask" mask="0x02" name="T3CTM"/>
          <bitfield caption="Timer3 Overflow Toggle Mask" mask="0x01" name="T3OTM"/>
        </register>
        <register caption="Timer3 input capture Register" name="T3ICR" offset="0x007B" size="2" mask="0xFFFF" ocd-rw="R"/>
        <register caption="Timer3 interrupt flag Register" name="T3IFR" offset="0x01E1" size="1">
          <bitfield caption="Timer3 Input Capture Flag" mask="0x04" name="T3ICF"/>
          <bitfield caption="Timer3 Compare Flag" mask="0x02" name="T3COF"/>
          <bitfield caption="Timer3 OverFlow Flag" mask="0x01" name="T3OFF"/>
        </register>
        <register caption="Timer3 interrupt mask Register" name="T3IMR" offset="0x007F" size="1">
          <bitfield caption="Timer3 Capture Interrupt Mask" mask="0x04" name="T3CPIM"/>
          <bitfield caption="Timer3 Compare Interrupt Mask" mask="0x02" name="T3CIM"/>
          <bitfield caption="Timer3 Overflow Interrupt Mask" mask="0x01" name="T3OIM"/>
        </register>
        <register caption="Timer3 mode Register" name="T3MRA" offset="0x007D" size="1">
          <bitfield caption="Timer3 Prescaler Select" mask="0x1C" name="T3PS"/>
          <bitfield caption="Timer3 Clock Select" mask="0x03" name="T3CS" values="TIM3_CLOCK_SELECT"/>
        </register>
        <register caption="Timer3 mode Register" name="T3MRB" offset="0x007E" size="1">
          <bitfield caption="Timer3 Input Capture Select" mask="0xE0" name="T3ICS" values="TIM3_CAPTURE_SELECT"/>
          <bitfield caption="Timer3 Capture Edge select" mask="0x18" name="T3CE" values="TIM3_CAPTURE_EDGE_SELECT"/>
          <bitfield caption="Timer3 input Capture Noise Canceller" mask="0x04" name="T3CNC"/>
          <bitfield caption="Timer3 Software Capture Enable" mask="0x02" name="T3SCE"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM3_CLOCK_SELECT">
        <value caption="clk_frc" name="VAL_0x00" value="0x00"/>
        <value caption="clk_T" name="VAL_0x01" value="0x01"/>
        <value caption="clk_xto4" name="VAL_0x02" value="0x02"/>
        <value caption="clk_TEI" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TIM3_CAPTURE_SELECT">
        <value caption="clk_T2" name="VAL_0x00" value="0x00"/>
        <value caption="clk_T1" name="VAL_0x01" value="0x01"/>
        <value caption="clk_T4" name="VAL_0x02" value="0x02"/>
        <value caption="TICP" name="VAL_0x03" value="0x03"/>
        <value caption="LFES" name="VAL_0x04" value="0x04"/>
        <value caption="clk_src" name="VAL_0x05" value="0x05"/>
        <value caption="TPGAP" name="VAL_0x06" value="0x06"/>
      </value-group>
      <value-group caption="" name="TIM3_CAPTURE_EDGE_SELECT">
        <value caption="disable" name="VAL_0x00" value="0x00"/>
        <value caption="rising edge" name="VAL_0x01" value="0x01"/>
        <value caption="falling edge" name="VAL_0x02" value="0x02"/>
        <value caption="both edges" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER4">
      <register-group caption="" name="TIMER4">
        <register caption="Timer4 counter Register" name="T4CNT" offset="0x0080" size="2" mask="0xFFFF" ocd-rw="R"/>
        <register caption="Timer4 compare Register" name="T4COR" offset="0x0082" size="2" mask="0xFFFF"/>
        <register caption="Timer4 control Register" name="T4CR" offset="0x0034" size="1">
          <bitfield caption="Timer4 Enable" mask="0x80" name="T4ENA"/>
          <bitfield caption="Timer4 Toggle with Start" mask="0x40" name="T4TOS"/>
          <bitfield caption="Timer4 Reset" mask="0x20" name="T4RES"/>
          <bitfield caption="Timer4 Toggle Output Preset" mask="0x10" name="T4TOP"/>
          <bitfield caption="Timer4 CaPture Reset Mask" mask="0x08" name="T4CPRM"/>
          <bitfield caption="Timer4 Compare Reset Mask" mask="0x04" name="T4CRM"/>
          <bitfield caption="Timer4 Compare Toggle Mask" mask="0x02" name="T4CTM"/>
          <bitfield caption="Timer4 Overflow Toggle Mask" mask="0x01" name="T4OTM"/>
        </register>
        <register caption="Timer4 input capture Register" name="T4ICR" offset="0x0084" size="2" mask="0xFFFF" ocd-rw="R"/>
        <register caption="Timer4 interrupt flag Register" name="T4IFR" offset="0x01D2" size="1">
          <bitfield caption="Timer4 Input Capture Flag" mask="0x04" name="T4ICF"/>
          <bitfield caption="Timer4 Compare Flag" mask="0x02" name="T4COF"/>
          <bitfield caption="Timer4 OverFlow Flag" mask="0x01" name="T4OFF"/>
        </register>
        <register caption="Timer4 interrupt mask Register" name="T4IMR" offset="0x0088" size="1">
          <bitfield caption="Timer4 Capture Interrupt Mask" mask="0x04" name="T4CPIM"/>
          <bitfield caption="Timer4 Compare Interrupt Mask" mask="0x02" name="T4CIM"/>
          <bitfield caption="Timer4 Overflow Interrupt Mask" mask="0x01" name="T4OIM"/>
        </register>
        <register caption="Timer4 mode Register" name="T4MRA" offset="0x0086" size="1">
          <bitfield caption="Timer4 Prescaler Select" mask="0x1C" name="T4PS"/>
          <bitfield caption="Timer4 Clock Select" mask="0x03" name="T4CS" values="TIM4_CLOCK_SELECT"/>
        </register>
        <register caption="Timer4 mode Register" name="T4MRB" offset="0x0087" size="1">
          <bitfield caption="Timer4 Input Capture Select" mask="0xE0" name="T4ICS" values="TIM4_CAPTURE_SELECT"/>
          <bitfield caption="Timer4 Capture Edge select" mask="0x18" name="T4CE" values="TIM4_CAPTURE_EDGE_SELECT"/>
          <bitfield caption="Timer4 input Capture Noise Canceller" mask="0x04" name="T4CNC"/>
          <bitfield caption="Timer4 Software Capture Enable" mask="0x02" name="T4SCE"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM4_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_T" name="VAL_0x01" value="0x01"/>
        <value caption="clk_mrc" name="VAL_0x02" value="0x02"/>
        <value caption="clk_frc" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TIM4_CAPTURE_SELECT">
        <value caption="clk_T2" name="VAL_0x00" value="0x00"/>
        <value caption="clk_T1" name="VAL_0x01" value="0x01"/>
        <value caption="clk_T3" name="VAL_0x02" value="0x02"/>
        <value caption="TICP" name="VAL_0x03" value="0x03"/>
        <value caption="LFES" name="VAL_0x04" value="0x04"/>
        <value caption="clk_src" name="VAL_0x05" value="0x05"/>
        <value caption="TPGAP" name="VAL_0x06" value="0x06"/>
      </value-group>
      <value-group caption="" name="TIM4_CAPTURE_EDGE_SELECT">
        <value caption="disable" name="VAL_0x00" value="0x00"/>
        <value caption="rising edge" name="VAL_0x01" value="0x01"/>
        <value caption="falling edge" name="VAL_0x02" value="0x02"/>
        <value caption="both edges" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER5">
      <register-group caption="" name="TIMER5">
        <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x00E3" size="1">
          <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
          <bitfield caption="PreScaler Reset" mask="0x01" name="PSR10"/>
        </register>
        <register caption="Timer5 Control Register" name="T5CCR" offset="0x008C" size="1">
          <bitfield caption="Clear Timer5 on Compare Match" mask="0x08" name="T5CTC"/>
          <bitfield caption="Timer5 Clock Select" mask="0x07" name="T5CS" values="CLK_SEL_3BIT"/>
        </register>
        <register caption="Timer5 Counter" name="T5CNT" offset="0x008D" size="2" mask="0xFFFF"/>
        <register caption="Timer5 Interrupt Flag Register" name="T5IFR" offset="0x01D5" size="1">
          <bitfield caption="Timer5 Output Compare Output Match Flag" mask="0x02" name="T5COF"/>
          <bitfield caption="Timer5 Output Overflow Flag" mask="0x01" name="T5OFF"/>
        </register>
        <register caption="Timer5 Interrupt Mask Register" name="T5IMR" offset="0x008F" size="1">
          <bitfield caption="Timer5 Output Compare Interrupt Mask" mask="0x02" name="T5CIM"/>
          <bitfield caption="Timer5 Output Overflow Interrupt Mask" mask="0x01" name="T5OIM"/>
        </register>
        <register caption="Timer5 Output Compare Register" name="T5OCR" offset="0x008A" size="2" mask="0xFFFF"/>
        <register caption="Timer5 Temp Register" name="T5TEMP" offset="0x0089" size="1" mask="0xFF"/>
      </register-group>
      <value-group caption="" name="CLK_SEL_3BIT">
        <value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
        <value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
        <value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
        <value caption="Running, CLK/32" name="VAL_0x03" value="0x03"/>
        <value caption="Running, CLK/64" name="VAL_0x04" value="0x04"/>
        <value caption="Running, CLK/128" name="VAL_0x05" value="0x05"/>
        <value caption="Running, CLK/256" name="VAL_0x06" value="0x06"/>
        <value caption="Running, CLK/1024" name="VAL_0x07" value="0x07"/>
      </value-group>
    </module>
    <module caption="" name="TMO">
      <register-group caption="" name="TMO">
        <register caption="Timer Modulator Output Control Register" name="TMOCR" offset="0x01F0" size="1">
          <bitfield caption="Timer modulator Output 4 Port Interface Select" mask="0xC0" name="TO4PIS" values="TO4PIS_SELECT"/>
          <bitfield caption="Timer modulator Output 3 Port Interface Select" mask="0x30" name="TO3PIS" values="TO3PIS_SELECT"/>
          <bitfield caption="Timer modulator Output 2 Port Interface Select" mask="0x0C" name="TO2PIS" values="TO2PIS_SELECT"/>
          <bitfield caption="Timer modulator Output 1 Port Interface Select" mask="0x03" name="TO1PIS" values="TO1PIS_SELECT"/>
        </register>
      </register-group>
      <value-group caption="" name="TO4PIS_SELECT">
        <value caption="Port D5 Data Register" name="VAL_0x00" value="0x00"/>
        <value caption="M1 - Toggle Register Timer1" name="VAL_0x01" value="0x01"/>
        <value caption="M2 - Toggle Register Timer2" name="VAL_0x02" value="0x02"/>
        <value caption="M3 - Toggle Register Timer3" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TO3PIS_SELECT">
        <value caption="Port D4 Data Register" name="VAL_0x00" value="0x00"/>
        <value caption="M1 - Toggle Register Timer1" name="VAL_0x01" value="0x01"/>
        <value caption="M3 - Toggle Register Timer3" name="VAL_0x02" value="0x02"/>
        <value caption="M4 - Toggle Register Timer4" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TO2PIS_SELECT">
        <value caption="Port D3 Data Register" name="VAL_0x00" value="0x00"/>
        <value caption="M1 - Toggle Register Timer1" name="VAL_0x01" value="0x01"/>
        <value caption="M2 - Toggle Register Timer2" name="VAL_0x02" value="0x02"/>
        <value caption="M4 - Toggle Register Timer4" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TO1PIS_SELECT">
        <value caption="Port D2 Data Register" name="VAL_0x00" value="0x00"/>
        <value caption="M1 - Toggle Register Timer1" name="VAL_0x01" value="0x01"/>
        <value caption="M2 - Toggle Register Timer2" name="VAL_0x02" value="0x02"/>
        <value caption="M3 - Toggle Register Timer3" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TPLF_CAL">
      <register-group caption="" name="TPLF_CAL">
        <register caption="LF Receiver Calibration Register 1" name="LFCALR1" offset="0x0090" size="1">
          <bitfield caption="Bandgap Calibration of VREF1" mask="0xE0" name="SEL150M"/>
          <bitfield caption="icomp_range_trim" mask="0x18" name="ICOMPRT"/>
          <bitfield caption="lf_stim_trim_current" mask="0x07" name="LFSTC"/>
        </register>
        <register caption="LF Receiver Calibration Register 10" name="LFCALR10" offset="0x0099" size="1" mask="0x7F"/>
        <register caption="LF Receiver Calibration Register 11" name="LFCALR11" offset="0x009A" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 12" name="LFCALR12" offset="0x009B" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 13" name="LFCALR13" offset="0x009C" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 14" name="LFCALR14" offset="0x009D" size="1" mask="0x7F"/>
        <register caption="LF Receiver Calibration Register 15" name="LFCALR15" offset="0x009E" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 16" name="LFCALR16" offset="0x009F" size="1" mask="0x1F"/>
        <register caption="LF Receiver Calibration Register 17" name="LFCALR17" offset="0x00A0" size="1" mask="0x1F"/>
        <register caption="LF Receiver Calibration Register 18" name="LFCALR18" offset="0x00A1" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 19" name="LFCALR19" offset="0x00A2" size="1" mask="0x7F"/>
        <register caption="LF Receiver Calibration Register 2" name="LFCALR2" offset="0x0091" size="1">
          <bitfield caption="trim_ikomp_data" mask="0x80" name="TIKOMPD"/>
          <bitfield caption="lf_stim_res_mode" mask="0x40" name="LFSRM"/>
          <bitfield caption="lf_stim_trim_res" mask="0x3F" name="LFSTRES"/>
        </register>
        <register caption="LF Receiver Calibration Register 20" name="LFCALR20" offset="0x00A3" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 21" name="LFCALR21" offset="0x00A4" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 22" name="LFCALR22" offset="0x00A5" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 23" name="LFCALR23" offset="0x00A6" size="1" mask="0x7F"/>
        <register caption="LF Receiver Calibration Register 24" name="LFCALR24" offset="0x00A7" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 25" name="LFCALR25" offset="0x00A8" size="1" mask="0x1F"/>
        <register caption="LF Receiver Calibration Register 26" name="LFCALR26" offset="0x00A9" size="1" mask="0x1F"/>
        <register caption="LF Receiver Calibration Register 27" name="LFCALR27" offset="0x00AA" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 28" name="LFCALR28" offset="0x00AB" size="1" mask="0x7F"/>
        <register caption="LF Receiver Calibration Register 29" name="LFCALR29" offset="0x00AC" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 3" name="LFCALR3" offset="0x0092" size="1">
          <bitfield caption="Trim coarse gain" mask="0xFF" name="TCGAIN1"/>
        </register>
        <register caption="LF Receiver Calibration Register 30" name="LFCALR30" offset="0x00AD" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 31" name="LFCALR31" offset="0x00AE" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 32" name="LFCALR32" offset="0x00AF" size="1" mask="0x7F"/>
        <register caption="LF Receiver Calibration Register 33" name="LFCALR33" offset="0x00B0" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 34" name="LFCALR34" offset="0x00B1" size="1" mask="0x1F"/>
        <register caption="LF Receiver Calibration Register 35" name="LFCALR35" offset="0x00B2" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 36" name="LFCALR36" offset="0x00B3" size="1" mask="0x7F"/>
        <register caption="LF Receiver Calibration Register 37" name="LFCALR37" offset="0x00B4" size="1" mask="0x3F"/>
        <register caption="LF Receiver Calibration Register 38" name="LFCALR38" offset="0x00B5" size="1" mask="0x0F"/>
        <register caption="LF Receiver Calibration Register 39" name="LFCALR39" offset="0x00B6" size="1" mask="0x0F"/>
        <register caption="LF Receiver Calibration Register 4" name="LFCALR4" offset="0x0093" size="1">
          <bitfield caption="Trim coarse gain bit 15" mask="0x80" name="TCGAIN27"/>
          <bitfield caption="Trim coarse gain bit 14" mask="0x40" name="TCGAIN26"/>
          <bitfield caption="Trim coarse gain bit 13" mask="0x20" name="TCGAIN25"/>
          <bitfield caption="Trim coarse gain bit 12" mask="0x10" name="TCGAIN24"/>
          <bitfield caption="Trim coarse gain bit 11" mask="0x08" name="TCGAIN23"/>
          <bitfield caption="Trim coarse gain bit 10" mask="0x04" name="TCGAIN22"/>
          <bitfield caption="Trim coarse gain bit 9" mask="0x02" name="TCGAIN21"/>
          <bitfield caption="Trim coarse gain bit 8" mask="0x01" name="TCGAIN20"/>
        </register>
        <register caption="LF Receiver Calibration Register 40" name="LFCALR40" offset="0x00B7" size="1" mask="0x0F"/>
        <register caption="LF Receiver Calibration Register 41" name="LFCALR41" offset="0x00B8" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 42" name="LFCALR42" offset="0x00B9" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 43" name="LFCALR43" offset="0x00BA" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 44" name="LFCALR44" offset="0x00BB" size="1" mask="0x3F"/>
        <register caption="LF Receiver Calibration Register 45" name="LFCALR45" offset="0x00BC" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 46" name="LFCALR46" offset="0x00BD" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 47" name="LFCALR47" offset="0x00BE" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 48" name="LFCALR48" offset="0x00BF" size="1" mask="0x3F"/>
        <register caption="LF Receiver Calibration Register 49" name="LFCALR49" offset="0x00C0" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 5" name="LFCALR5" offset="0x0094" size="1">
          <bitfield caption="Trim coarse gain bit 23" mask="0x80" name="TCGAIN37"/>
          <bitfield caption="Trim coarse gain bit 22" mask="0x40" name="TCGAIN36"/>
          <bitfield caption="Trim coarse gain bit 21" mask="0x20" name="TCGAIN35"/>
          <bitfield caption="Trim coarse gain bit 20" mask="0x10" name="TCGAIN34"/>
          <bitfield caption="Trim coarse gain bit 18" mask="0x04" name="TCGAIN32"/>
          <bitfield caption="Trim coarse gain bit 17" mask="0x02" name="TCGAIN31"/>
          <bitfield caption="Trim coarse gain bit 16" mask="0x01" name="TCGAIN30"/>
        </register>
        <register caption="LF Receiver Calibration Register 50" name="LFCALR50" offset="0x00C1" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 51" name="LFCALR51" offset="0x00C2" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 52" name="LFCALR52" offset="0x00C3" size="1" mask="0x3F"/>
        <register caption="LF Receiver Calibration Register 53" name="LFCALR53" offset="0x00C4" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 6" name="LFCALR6" offset="0x0095" size="1">
          <bitfield caption="Trim coarse gain bit 28" mask="0x10" name="TCGAIN44"/>
          <bitfield caption="Trim coarse gain bit 27" mask="0x08" name="TCGAIN43"/>
          <bitfield caption="Trim coarse gain bit 26" mask="0x04" name="TCGAIN42"/>
          <bitfield caption="Trim coarse gain bit 25" mask="0x02" name="TCGAIN41"/>
          <bitfield caption="Trim coarse gain bit 24" mask="0x01" name="TCGAIN40"/>
        </register>
        <register caption="LF Receiver Calibration Register 7" name="LFCALR7" offset="0x0096" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Register 8" name="LFCALR8" offset="0x0097" size="1" mask="0x1F"/>
        <register caption="LF Receiver Calibration Register 9" name="LFCALR9" offset="0x0098" size="1" mask="0xFF"/>
        <register caption="LF Receiver Calibration Protect Register" name="LFCPR" offset="0x018E" size="1">
          <bitfield caption="LF Calibration Protect Change Enable" mask="0x80" name="LFCPCE"/>
          <bitfield caption="Transponder Constant Disable" mask="0x40" name="TPCD"/>
          <bitfield caption="LF Calibration Ready" mask="0x02" name="LFCALRY"/>
          <bitfield caption="LF Calibration Protection" mask="0x01" name="LFCALP"/>
        </register>
        <register caption="Slow RC oscillator calibration" name="SRCCAL" offset="0x01F1" size="1">
          <bitfield caption="Slow RC oscillator calibration bit 8" mask="0x80" name="SRCCAL8"/>
          <bitfield caption="Slow RC oscillator calibration bit 7" mask="0x40" name="SRCCAL7"/>
          <bitfield caption="Slow RC oscillator calibration bit 6" mask="0x20" name="SRCCAL6"/>
          <bitfield caption="Slow RC oscillator calibration bit 5" mask="0x10" name="SRCCAL5"/>
          <bitfield caption="Slow RC oscillator calibration bit 4" mask="0x08" name="SRCCAL4"/>
          <bitfield caption="Slow RC oscillator calibration bit 3" mask="0x04" name="SRCCAL3"/>
          <bitfield caption="Slow RC oscillator calibration bit 2" mask="0x02" name="SRCCAL2"/>
          <bitfield caption="Slow RC oscillator calibration bit 1" mask="0x01" name="SRCCAL1"/>
        </register>
        <register caption="Slow RC oscillator calibration LSB" name="SRCCALL" offset="0x01FF" size="1">
          <bitfield caption="Slow RC oscillator calibration bit 0" mask="0x01" name="SRCCAL0"/>
        </register>
        <register caption="SRC oscillator Temperature Compensation register" name="SRCTCAL" offset="0x01F2" size="1">
          <bitfield caption="Stop SRC-Osccillator output" mask="0x80" name="HOLD_SRC"/>
          <bitfield caption="Disable SRC Bandgap" mask="0x40" name="DIS_SRC"/>
          <bitfield caption="SRC Oscillator Select delta current" mask="0x18" name="SRCS"/>
          <bitfield caption="SRC Oscillator Temperature Compensation" mask="0x07" name="SRCTC"/>
        </register>
        <register caption="Transponder Calibration Register 1" name="TPCALR1" offset="0x0175" size="1">
          <bitfield caption="Transponder Bandgap IREF" mask="0x3F" name="TPBG_IREF"/>
        </register>
        <register caption="Transponder Calibration Register 10" name="TPCALR10" offset="0x017E" size="1" mask="0x7F"/>
        <register caption="Transponder Calibration Register 11" name="TPCALR11" offset="0x01F9" size="1">
          <bitfield caption="" mask="0x80" name="TPCALR117"/>
          <bitfield caption="" mask="0x40" name="TPCALR116"/>
          <bitfield caption="" mask="0x20" name="TPCALR115"/>
          <bitfield caption="Enable VSW Brown Out Detection" mask="0x10" name="ENVSWBD"/>
          <bitfield caption="Enable LFVCC Brown Out Detection" mask="0x08" name="ENLFBD"/>
          <bitfield caption="Enable DVCC Brown Out Detection" mask="0x04" name="ENDVBD"/>
          <bitfield caption="Measurement Buffer Trimming bit 1" mask="0x02" name="MTBTR1"/>
          <bitfield caption="Measurement Buffer Trimming bit 0" mask="0x01" name="MTBTR0"/>
        </register>
        <register caption="Transponder Calibration Register 12" name="TPCALR12" offset="0x01FA" size="1">
          <bitfield caption="" mask="0x80" name="TPCALR127"/>
          <bitfield caption="" mask="0x40" name="TPCALR126"/>
          <bitfield caption="" mask="0x20" name="TPCALR125"/>
          <bitfield caption="" mask="0x10" name="TPCALR124"/>
          <bitfield caption="" mask="0x08" name="TPCALR123"/>
          <bitfield caption="" mask="0x04" name="TPCALR122"/>
          <bitfield caption="" mask="0x02" name="TPCALR121"/>
          <bitfield caption="Transponder Direct Modulation" mask="0x01" name="TPDMOD"/>
        </register>
        <register caption="Transponder Calibration Register 13" name="TPCALR13" offset="0x01FB" size="1" mask="0xFF"/>
        <register caption="Transponder Calibration Register 2" name="TPCALR2" offset="0x0176" size="1">
          <bitfield caption="Transponder Bandgap UREF" mask="0x7F" name="TPBG_UREF"/>
        </register>
        <register caption="Transponder Calibration Register 3" name="TPCALR3" offset="0x0177" size="1">
          <bitfield caption="Transponder Power On Reset Threshold" mask="0x18" name="TPORTH"/>
          <bitfield caption="Not used" mask="0x04" name="LFVCC_TPCAL2"/>
          <bitfield caption="Not used" mask="0x02" name="LFVCC_TPCAL1"/>
          <bitfield caption="Not used" mask="0x01" name="LFVCC_TPCAL0"/>
        </register>
        <register caption="Transponder Calibration Register 4" name="TPCALR4" offset="0x0178" size="1">
          <bitfield caption="Comparator VC Calibration" mask="0x18" name="COMPVC_CAL"/>
          <bitfield caption="Transponder Init Calibration" mask="0x07" name="TPINIT_CAL"/>
        </register>
        <register caption="Transponder Calibration Register 5" name="TPCALR5" offset="0x0179" size="1" mask="0x0F"/>
        <register caption="Transponder Calibration Register 6" name="TPCALR6" offset="0x017A" size="1" mask="0x1F"/>
        <register caption="Transponder Calibration Register 7" name="TPCALR7" offset="0x017B" size="1" mask="0x07"/>
        <register caption="Transponder Calibration Register 8" name="TPCALR8" offset="0x017C" size="1" mask="0x7F"/>
        <register caption="Transponder Calibration Register 9" name="TPCALR9" offset="0x017D" size="1" mask="0xFF"/>
     </register-group>
    </module>
    <module caption="" name="TWI1">
      <register-group caption="" name="TWI1">
        <register caption="TWI1 Address Mask Register" name="TW1AMR" offset="0x01EE" size="1">
          <bitfield caption="TWI1 Address Mask" mask="0xFE" name="TW1AM"/>
        </register>
        <register caption="TWI1 (Slave) Address Register" name="TW1AR" offset="0x01ED" size="1">
          <bitfield caption="TWI1 (Slave) Address" mask="0xFE" name="TW1A"/>
          <bitfield caption="TWI1 General Call Recognition Enable" mask="0x01" name="TW1GCE"/>
        </register>
        <register caption="TWI1 Bit Rate Register" name="TW1BR" offset="0x01E9" size="1" mask="0xFF"/>
        <register caption="TWI1 Control Register" name="TW1CR" offset="0x01EA" size="1">
          <bitfield caption="TWI1 Interrupt Flag" mask="0x80" name="TW1INT"/>
          <bitfield caption="TWI1 Enable Acknowledge" mask="0x40" name="TW1EA"/>
          <bitfield caption="TWI1 START Condition" mask="0x20" name="TW1STA"/>
          <bitfield caption="TWI1 STOP Condition" mask="0x10" name="TW1STO"/>
          <bitfield caption="TWI1 Write Collision Flag" mask="0x08" name="TW1WC"/>
          <bitfield caption="TWI1 Enable" mask="0x04" name="TW1EN"/>
          <bitfield caption="TWI1 Interrupt Enable" mask="0x01" name="TW1IE"/>
        </register>
        <register caption="TWI1 Data Register" name="TW1DR" offset="0x01EC" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="TWI1 Status Register" name="TW1SR" offset="0x01EB" size="1">
          <bitfield caption="TWI1 Status" mask="0xF8" name="TW1S"/>
          <bitfield caption="TWI1 Prescaler" mask="0x03" name="TW1PS" values="COMM_TWI1_PRESCALE"/>
        </register>
      </register-group>
      <value-group caption="" name="COMM_TWI1_PRESCALE">
        <value caption="1" name="VAL_0x00" value="0x00"/>
        <value caption="4" name="VAL_0x01" value="0x01"/>
        <value caption="16" name="VAL_0x02" value="0x02"/>
        <value caption="64" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TWI2">
      <register-group caption="" name="TWI2">
        <register caption="TWI2 Address Mask Register" name="TW2AMR" offset="0x01AF" size="1">
          <bitfield caption="TWI2 Address Mask" mask="0xFE" name="TW2AM"/>
        </register>
        <register caption="TWI2 (Slave) Address Register" name="TW2AR" offset="0x01AE" size="1">
          <bitfield caption="TWI2 (Slave) Address" mask="0xFE" name="TW2A"/>
          <bitfield caption="TWI2 General Call Recognition Enable" mask="0x01" name="TW2GCE"/>
        </register>
        <register caption="TWI2 Bit Rate Register" name="TW2BR" offset="0x01AA" size="1" mask="0xFF"/>
        <register caption="TWI2 Control Register" name="TW2CR" offset="0x01AB" size="1">
          <bitfield caption="TWI2 Interrupt Flag" mask="0x80" name="TW2INT"/>
          <bitfield caption="TWI2 Enable Acknowledge" mask="0x40" name="TW2EA"/>
          <bitfield caption="TWI2 START Condition" mask="0x20" name="TW2STA"/>
          <bitfield caption="TWI2 STOP Condition" mask="0x10" name="TW2STO"/>
          <bitfield caption="TWI2 Write Collision Flag" mask="0x08" name="TW2WC"/>
          <bitfield caption="TWI2 Enable" mask="0x04" name="TW2EN"/>
          <bitfield caption="TWI2 Interrupt Enable" mask="0x01" name="TW2IE"/>
        </register>
        <register caption="TWI2 Data Register" name="TW2DR" offset="0x01AD" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="TWI2 Status Register" name="TW2SR" offset="0x01AC" size="1">
          <bitfield caption="TWI2 Status" mask="0xF8" name="TW2S"/>
          <bitfield caption="TWI2 Prescaler" mask="0x03" name="TW2PS" values="COMM_TWI2_PRESCALE"/>
        </register>
      </register-group>
      <value-group caption="" name="COMM_TWI2_PRESCALE">
        <value caption="1" name="VAL_0x00" value="0x00"/>
        <value caption="4" name="VAL_0x01" value="0x01"/>
        <value caption="16" name="VAL_0x02" value="0x02"/>
        <value caption="64" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="VX_MODE">
      <register-group caption="" name="VX_MODE">
        <register caption="VX Mode Control Register" name="VXMCTRL" offset="0x00EB" size="1">
          <bitfield caption="Enable VX Inputs" mask="0x10" name="EN_VX_IN"/>
          <bitfield caption="Enable PB4 as an VX/VBAT Supply Output" mask="0x08" name="EN_VX_OUT"/>
          <bitfield caption="Enable the VX_LDO" mask="0x04" name="EN_VX"/>
          <bitfield caption="Select VX voltage level" mask="0x02" name="VX_SEL1"/>
          <bitfield caption="Select VX voltage level" mask="0x01" name="VX_SEL0"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="FUSE">
      <register-group caption="" name="FUSE">
        <register caption="" name="LOW" offset="0x00" size="1" initval="0xDF">
          <bitfield caption="MRC is selected during reset startup phase" mask="0x80" name="CKSTART"/>
          <bitfield caption="Debug Wire enable" mask="0x40" name="DWEN"/>
          <bitfield caption="Serial program downloading (SPI) enabled" mask="0x20" name="SPIEN"/>
          <bitfield caption="Watch-dog Timer always on" mask="0x10" name="WDTON"/>
          <bitfield caption="Preserve EEPROM memory through the Chip Erase cycle" mask="0x08" name="EESAVE"/>
          <bitfield caption="Select boot reset vector" mask="0x04" name="BOOTRST"/>
          <bitfield caption="EEPROM Access Control" mask="0x02" name="EEACC"/>
          <bitfield caption="Protect Customer EEPROM section" mask="0x01" name="PCEE1"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="LOCKBIT">
      <register-group caption="" name="LOCKBIT">
        <register caption="" name="LOCKBIT" offset="0x00" size="1">
          <bitfield caption="Memory Lock" mask="0x03" name="LB" values="ENUM_LB"/>
        </register>
      </register-group>
      <value-group caption="" name="ENUM_LB">
        <value caption="Further programming and verification disabled" name="VAL_0x00" value="0x00"/>
        <value caption="Further programming disabled" name="VAL_0x02" value="0x02"/>
        <value caption="No memory lock features enable" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
  </modules>
</avr-tools-device-file>
