<?xml version="1.0" encoding="UTF-8"?>
<avr-tools-device-file xmlns:xalan="http://xml.apache.org/xalan" xmlns:NumHelper="NumHelper" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
  <variants>
    <variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="2.4" vccmax="5.5"/>
  </variants>
  <devices>
    <device name="ATA5835" architecture="AVR8" family="megaAVR">
      <address-spaces>
        <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0xd200">
          <memory-segment start="0x0000" size="0x8000" type="rom" rw="R" exec="1" name="ROM" pagesize="0x40"/>
          <memory-segment start="0x8000" size="0x5200" type="flash" rw="RW" exec="1" name="FLASH" pagesize="0x40"/>
        </address-space>
        <address-space endianness="little" name="signatures" id="signatures" start="0" size="3">
          <memory-segment start="0" size="3" type="signatures" rw="R" exec="0" name="SIGNATURES"/>
        </address-space>
        <address-space endianness="little" name="fuses" id="fuses" start="0" size="0x0001">
          <memory-segment start="0" size="0x0001" type="fuses" rw="RW" exec="0" name="FUSES"/>
        </address-space>
        <address-space endianness="little" name="lockbits" id="lockbits" start="0" size="0x0001">
          <memory-segment start="0" size="0x0001" type="lockbits" rw="RW" exec="0" name="LOCKBITS"/>
        </address-space>
        <address-space endianness="little" name="data" id="data" start="0x0000" size="0x0a00">
          <memory-segment external="false" type="regs" size="0x0020" start="0x0000" name="REGISTERS"/>
          <memory-segment name="MAPPED_IO" start="0x0020" size="0x01e0" type="io" external="false"/>
          <memory-segment name="IRAM" start="0x0200" size="0x0800" type="ram" external="false"/>
        </address-space>
        <address-space endianness="little" name="eeprom" id="eeprom" start="0x0000" size="0x0480">
          <memory-segment start="0x0000" size="0x0400" type="eeprom" rw="RW" exec="0" name="EEPROM" pagesize="0x10"/>
          <memory-segment start="0x0400" size="0x0080" type="eeprom" rw="R" exec="0" name="CALDATA" pagesize="0x10"/>
        </address-space>
        <address-space size="0x40" start="0x00" endianness="little" name="io" id="io"/>
      </address-spaces>
      <peripherals>
        <module name="CALIB">
          <instance name="CALIB">
            <register-group name="CALIB" name-in-module="CALIB" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CHFLT">
          <instance name="CHFLT">
            <register-group name="CHFLT" name-in-module="CHFLT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CLK">
          <instance name="CLK">
            <register-group name="CLK" name-in-module="CLK" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CPU">
          <instance name="CPU">
            <register-group name="CPU" name-in-module="CPU" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CRC">
          <instance name="CRC">
            <register-group name="CRC" name-in-module="CRC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DEMOD">
          <instance name="DEMOD">
            <register-group name="DEMOD" name-in-module="DEMOD" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DFIFO">
          <instance name="DFIFO">
            <register-group name="DFIFO" name-in-module="DFIFO" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="EEPROM">
          <instance name="EEPROM">
            <register-group name="EEPROM" name-in-module="EEPROM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FE">
          <instance name="FE">
            <register-group name="FE" name-in-module="FE" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FREQS">
          <instance name="FREQS">
            <register-group name="FREQS" name-in-module="FREQS" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FRSYNC">
          <instance name="FRSYNC">
            <register-group name="FRSYNC" name-in-module="FRSYNC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="GPIOREGS">
          <instance name="GPIOREGS">
            <register-group name="GPIOREGS" name-in-module="GPIOREGS" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="IDCHK">
          <instance name="IDCHK">
            <register-group name="IDCHK" name-in-module="IDCHK" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="INT">
          <instance name="INT">
            <register-group name="INT" name-in-module="INT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="LIN_UART">
          <instance name="LIN_UART">
            <register-group name="LIN_UART" name-in-module="LIN_UART" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="OCCOUNT">
          <instance name="OCCOUNT">
            <register-group name="OCCOUNT" name-in-module="OCCOUNT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="PORTB">
          <instance name="PORTB">
            <register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="PORTC">
          <instance name="PORTC">
            <register-group name="PORTC" name-in-module="PORTC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="PORTS">
          <instance name="PORTS">
            <register-group name="PORTS" name-in-module="PORTS" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="RSSIB">
          <instance name="RSSIB">
            <register-group name="RSSIB" name-in-module="RSSIB" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="RXBUF">
          <instance name="RXBUF">
            <register-group name="RXBUF" name-in-module="RXBUF" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="RXDSP">
          <instance name="RXDSP">
            <register-group name="RXDSP" name-in-module="RXDSP" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SFIFO">
          <instance name="SFIFO">
            <register-group name="SFIFO" name-in-module="SFIFO" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SPI">
          <instance name="SPI">
            <register-group name="SPI" name-in-module="SPI" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SSM">
          <instance name="SSM">
            <register-group name="SSM" name-in-module="SSM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SUP">
          <instance name="SUP">
            <register-group name="SUP" name-in-module="SUP" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER0_WDT">
          <instance name="TIMER0_WDT">
            <register-group name="TIMER0_WDT" name-in-module="TIMER0_WDT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER1">
          <instance name="TIMER1">
            <register-group name="TIMER1" name-in-module="TIMER1" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER2">
          <instance name="TIMER2">
            <register-group name="TIMER2" name-in-module="TIMER2" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER3">
          <instance name="TIMER3">
            <register-group name="TIMER3" name-in-module="TIMER3" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER4">
          <instance name="TIMER4">
            <register-group name="TIMER4" name-in-module="TIMER4" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER5">
          <instance name="TIMER5">
            <register-group name="TIMER5" name-in-module="TIMER5" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TRACE">
          <instance name="TRACE">
            <register-group name="TRACE" name-in-module="TRACE" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TXM">
          <instance name="TXM">
            <register-group name="TXM" name-in-module="TXM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="VMON">
          <instance name="VMON">
            <register-group name="VMON" name-in-module="VMON" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FUSE">
          <instance name="FUSE">
            <register-group name="FUSE" name-in-module="FUSE" offset="0" address-space="fuses"/>
          </instance>
        </module>
        <module name="LOCKBIT">
          <instance name="LOCKBIT">
            <register-group name="LOCKBIT" name-in-module="LOCKBIT" offset="0" address-space="lockbits"/>
          </instance>
        </module>
      </peripherals>
      <interrupts>
        <interrupt index="0" name="RESET" caption="External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset"/>
        <interrupt index="1" name="INT0" caption="External Interrupt Request 0"/>
        <interrupt index="2" name="INT1" caption="External Interrupt Request 1"/>
        <interrupt index="3" name="PCI0" caption="Pin Change Interrupt Request 0"/>
        <interrupt index="4" name="PCI1" caption="Pin Change Interrupt Request 1"/>
        <interrupt index="5" name="VMON" caption="Voltage Monitoring Interrupt"/>
        <interrupt index="6" name="AVCCR" caption="AVCC Reset Interrupt"/>
        <interrupt index="7" name="AVCCL" caption="AVCC Low Interrupt"/>
        <interrupt index="8" name="T0INT" caption="Timer 0 Interval Interrupt"/>
        <interrupt index="9" name="T1COMP" caption="Timer/Counter1 Compare Match Interrupt"/>
        <interrupt index="10" name="T1OVF" caption="Timer/Counter1 Overflow Interrupt"/>
        <interrupt index="11" name="T2COMP" caption="Timer/Counter2 Compare Match Interrupt"/>
        <interrupt index="12" name="T2OVF" caption="Timer/Counter2 Overflow Interrupt"/>
        <interrupt index="13" name="T3CAP" caption="Timer/Counter3 Capture Event Interrupt"/>
        <interrupt index="14" name="T3COMP" caption="Timer/Counter3 Compare Match Interrupt"/>
        <interrupt index="15" name="T3OVF" caption="Timer/Counter3 Overflow Interrupt"/>
        <interrupt index="16" name="T4CAP" caption="Timer/Counter4 Capture Event Interrupt"/>
        <interrupt index="17" name="T4COMP" caption="Timer/Counter4 Compare Match Interrupt"/>
        <interrupt index="18" name="T4OVF" caption="Timer/Counter4 Overflow Interrupt"/>
        <interrupt index="19" name="T5COMP" caption="Timer/Counter5 Compare Match Interrupt"/>
        <interrupt index="20" name="T5OVF" caption="Timer/Counter5 Overflow Interrupt"/>
        <interrupt index="21" name="SPI" caption="SPI Serial Transfer Complete Interrupt"/>
        <interrupt index="22" name="SRX_FIFO" caption="SPI Rx Buffer Interrupt"/>
        <interrupt index="23" name="STX_FIFO" caption="SPI Tx Buffer Interrupt"/>
        <interrupt index="24" name="LINTC" caption="LIN/UART Transfer Complete Interrupt"/>
        <interrupt index="25" name="LINERR" caption="LIN/UART Error Interrupt"/>
        <interrupt index="26" name="SSM" caption="Sequencer State Machine Interrupt"/>
        <interrupt index="27" name="DFFLR" caption="Data FIFO fill level reached Interrupt"/>
        <interrupt index="28" name="DFOUE" caption="Data FIFO overflow or underflow error Interrupt"/>
        <interrupt index="29" name="SFFLR" caption="RSSI/Preamble FIFO fill level reached Interrupt"/>
        <interrupt index="30" name="SFOUE" caption="RSSI/Preamble FIFO overflow or underflow error Interrupt"/>
        <interrupt index="31" name="TMTCF" caption="Tx Modulator Telegram Finish Interrupt"/>
        <interrupt index="32" name="UHF_WCOA" caption="UHF receiver wake up ok on Rx path A"/>
        <interrupt index="33" name="UHF_WCOB" caption="UHF receiver wake up ok on Rx path B"/>
        <interrupt index="34" name="UHF_SOTA" caption="UHF receiver start of telegram ok on Rx path A"/>
        <interrupt index="35" name="UHF_SOTB" caption="UHF receiver start of telegram ok on Rx path B"/>
        <interrupt index="36" name="UHF_EOTA" caption="UHF receiver end of telegram on Rx path A"/>
        <interrupt index="37" name="UHF_EOTB" caption="UHF receiver end of telegram on Rx path B"/>
        <interrupt index="38" name="UHF_NBITA" caption="UHF receiver new bit on Rx path A"/>
        <interrupt index="39" name="UHF_NBITB" caption="UHF receiver new bit on Rx path B"/>
        <interrupt index="40" name="EXCM" caption="External input Clock monitoring Interrupt"/>
        <interrupt index="41" name="ERDY" caption="EEPROM Ready Interrupt"/>
        <interrupt index="42" name="SPMR" caption="Store Program Memory Ready"/>
        <interrupt index="43" name="IDFULL" caption="IDSCAN Full Interrupt"/>
      </interrupts>
      <interfaces>
        <interface name="ISP" type="isp"/>
        <interface name="debugWIRE" type="dw"/>
      </interfaces>
      <property-groups>
        <property-group name="SIGNATURES">
          <property name="JTAGID" value="0x946b"/>
          <property name="SIGNATURE0" value="0x1e"/>
          <property name="SIGNATURE1" value="0x94"/>
          <property name="SIGNATURE2" value="0x6b"/>
        </property-group>
        <property-group name="OCD">
          <property name="OCD_REVISION" value="2"/>
          <property name="OCD_DATAREG" value="0x31"/>
          <property name="PROGBASE" value="0x0000"/>
        </property-group>
        <property-group name="JTAG_INTERFACE">
          <property name="ALLOWFULLPAGESTREAM" value="0x00"/>
        </property-group>
        <property-group name="ISP_INTERFACE">
          <property name="IspEnterProgMode_timeout" value="255"/>
          <property name="IspEnterProgMode_stabDelay" value="255"/>
          <property name="IspEnterProgMode_cmdexeDelay" value="5"/>
          <property name="IspEnterProgMode_synchLoops" value="64"/>
          <property name="IspEnterProgMode_bitDelay" value="5"/>
          <property name="IspEnterProgMode_byteDelay" value="5"/>
          <property name="IspEnterProgMode_pollIndex" value="3"/>
          <property name="IspEnterProgMode_pollValue" value="0x53"/>
          <property name="IspLeaveProgMode_preDelay" value="1"/>
          <property name="IspLeaveProgMode_postDelay" value="1"/>
          <property name="IspChipErase_eraseDelay" value="45"/>
          <property name="IspChipErase_pollMethod" value="1"/>
          <property name="IspProgramFlash_mode" value="0x41"/>
          <property name="IspProgramFlash_blockSize" value="64"/>
          <property name="IspProgramFlash_delay" value="10"/>
          <property name="IspProgramFlash_cmd1" value="0x40"/>
          <property name="IspProgramFlash_cmd2" value="0x4C"/>
          <property name="IspProgramFlash_cmd3" value="0x00"/>
          <property name="IspProgramFlash_pollVal1" value="0x00"/>
          <property name="IspProgramFlash_pollVal2" value="0x00"/>
          <property name="IspProgramEeprom_mode" value="0x41"/>
          <property name="IspProgramEeprom_blockSize" value="16"/>
          <property name="IspProgramEeprom_delay" value="20"/>
          <property name="IspProgramEeprom_cmd1" value="0xC1"/>
          <property name="IspProgramEeprom_cmd2" value="0xC2"/>
          <property name="IspProgramEeprom_cmd3" value="0x00"/>
          <property name="IspProgramEeprom_pollVal1" value="0x00"/>
          <property name="IspProgramEeprom_pollVal2" value="0x00"/>
          <property name="IspReadFlash_blockSize" value="256"/>
          <property name="IspReadEeprom_blockSize" value="256"/>
          <property name="IspReadFuse_pollIndex" value="4"/>
          <property name="IspReadLock_pollIndex" value="4"/>
          <property name="IspReadSign_pollIndex" value="4"/>
          <property name="IspReadOsccal_pollIndex" value="4"/>
        </property-group>
        <property-group name="ISP_INTERFACE_STK600">
          <property name="IspEnterProgMode_timeout" value="255"/>
          <property name="IspEnterProgMode_stabDelay" value="255"/>
          <property name="IspEnterProgMode_cmdexeDelay" value="5"/>
          <property name="IspEnterProgMode_synchLoops" value="64"/>
          <property name="IspEnterProgMode_byteDelay" value="4"/>
          <property name="IspEnterProgMode_pollIndex" value="3"/>
          <property name="IspEnterProgMode_pollValue" value="0x53"/>
          <property name="IspLeaveProgMode_preDelay" value="1"/>
          <property name="IspLeaveProgMode_postDelay" value="1"/>
          <property name="IspChipErase_eraseDelay" value="45"/>
          <property name="IspChipErase_pollMethod" value="1"/>
          <property name="IspProgramFlash_mode" value="0x41"/>
          <property name="IspProgramFlash_blockSize" value="64"/>
          <property name="IspProgramFlash_delay" value="10"/>
          <property name="IspProgramFlash_cmd1" value="0x40"/>
          <property name="IspProgramFlash_cmd2" value="0x4C"/>
          <property name="IspProgramFlash_cmd3" value="0x00"/>
          <property name="IspProgramFlash_pollVal1" value="0x00"/>
          <property name="IspProgramFlash_pollVal2" value="0x00"/>
          <property name="IspProgramEeprom_mode" value="0x41"/>
          <property name="IspProgramEeprom_blockSize" value="16"/>
          <property name="IspProgramEeprom_delay" value="20"/>
          <property name="IspProgramEeprom_cmd1" value="0xC1"/>
          <property name="IspProgramEeprom_cmd2" value="0xC2"/>
          <property name="IspProgramEeprom_cmd3" value="0x00"/>
          <property name="IspProgramEeprom_pollVal1" value="0x00"/>
          <property name="IspProgramEeprom_pollVal2" value="0x00"/>
          <property name="IspReadFlash_blockSize" value="256"/>
          <property name="IspReadEeprom_blockSize" value="256"/>
          <property name="IspReadFuse_pollIndex" value="4"/>
          <property name="IspReadLock_pollIndex" value="4"/>
          <property name="IspReadSign_pollIndex" value="4"/>
          <property name="IspReadOsccal_pollIndex" value="4"/>
        </property-group>
      </property-groups>
    </device>
  </devices>
  <modules>
    <module caption="" name="FUSE">
      <register-group caption="" name="FUSE">
        <register caption="" name="LOW" offset="0x00" size="1">
          <bitfield caption="Divide clock by 8 internally" mask="0x80" name="CKDIV8"/>
          <bitfield caption="Debug Wire enable" mask="0x40" name="DWEN"/>
          <bitfield caption="Serial program downloading (SPI) enabled" mask="0x20" name="SPIEN"/>
          <bitfield caption="Watch-dog Timer always on" mask="0x10" name="WDTON"/>
          <bitfield caption="Preserve EEPROM memory through the Chip Erase cycle" mask="0x08" name="EESAVE"/>
          <bitfield caption="Select interrupt vector location" mask="0x04" name="BOOTRST"/>
          <bitfield caption="Disable external Reset" mask="0x02" name="RSTDISBL"/>
          <bitfield caption="External Clock enable" mask="0x01" name="EXTCLKEN"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="LOCKBIT">
      <register-group caption="" name="LOCKBIT">
        <register caption="" name="LOCKBIT" offset="0x00" size="1">
          <bitfield caption="Memory Lock" mask="0x03" name="LB" values="ENUM_LB"/>
          <bitfield caption="Application Protection" mask="0x0C" name="BLB0" values="ENUM_BLB0"/>
          <bitfield caption="Boot Loader Protection" mask="0x30" name="BLB1" values="ENUM_BLB1"/>
        </register>
      </register-group>
      <value-group caption="" name="ENUM_LB">
        <value caption="Further programming and verification disabled" name="VAL_0x00" value="0x00"/>
        <value caption="Further programming disabled" name="VAL_0x02" value="0x02"/>
        <value caption="No memory lock features enable" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="ENUM_BLB0">
        <value caption="LPM and SPM prohibited in Application Section" name="VAL_0x00" value="0x00"/>
        <value caption="LPM prohibited in Application Section" name="VAL_0x01" value="0x01"/>
        <value caption="SPM prohibited in Application Section" name="VAL_0x02" value="0x02"/>
        <value caption="No lock on SPM and LPM in Application Section" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="ENUM_BLB1">
        <value caption="LPM and SPM prohibited in Boot Loader Section" name="VAL_0x00" value="0x00"/>
        <value caption="LPM prohibited in Boot Loader Section" name="VAL_0x01" value="0x01"/>
        <value caption="SPM prohibited in Boot Loader Section" name="VAL_0x02" value="0x02"/>
        <value caption="No lock on SPM and LPM in Boot Loader Section" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="CALIB">
      <register-group caption="" name="CALIB">
        <register caption="Calibration Ready Signature" name="CALRDY" offset="0x00DA" size="1" mask="0xFF"/>
        <register caption="Fast RC Oscillator Calibration" name="FRCCAL" offset="0x00CD" size="1">
          <bitfield caption="Fast RC Oscillator Temperature Compensation" mask="0x20" name="FRCTC"/>
          <bitfield caption="Fast RC Oscillator Calibration" mask="0x1F" name="FRCCAL"/>
        </register>
        <register caption="Slow RC Oscillator Calibration" name="SRCCAL" offset="0x00CC" size="1">
          <bitfield caption="Slow RC Oscillator Temperature Compensation" mask="0xC0" name="SRCTC"/>
          <bitfield caption="Slow RC Oscillator Calibration" mask="0x3F" name="SRCCAL"/>
        </register>
        <register caption="Supply Calibration 1" name="SUPCA1" offset="0x00D2" size="1">
          <bitfield caption="PA Regulator Voltage Calibration" mask="0xC0" name="PVCAL"/>
          <bitfield caption="AVCC Regulator Voltage Calibration" mask="0x30" name="AVCAL"/>
          <bitfield caption="VMEM Regulator Voltage Calibration" mask="0x0C" name="VVCAL"/>
          <bitfield caption="DVCC Regulator Voltage Calibration" mask="0x03" name="DVCAL"/>
        </register>
        <register caption="Supply Calibration 2" name="SUPCA2" offset="0x00D3" size="1">
          <bitfield caption="Band Gap Calibration" mask="0x3F" name="BGCAL"/>
        </register>
        <register caption="Supply Calibration 3" name="SUPCA3" offset="0x00D4" size="1">
          <bitfield caption="Voltage Monitor Calibration" mask="0xC0" name="VMOCAL"/>
          <bitfield caption="AVCC Monitor Calibration" mask="0x30" name="AMCAL"/>
          <bitfield caption="VMEM Monitor Calibration" mask="0x0C" name="VMCAL"/>
          <bitfield caption="DVCC Monitor Calibration" mask="0x03" name="DMCAL"/>
        </register>
        <register caption="Supply Calibration 4" name="SUPCA4" offset="0x00D5" size="1">
          <bitfield caption="Bandgap PTAT Calibration" mask="0xFF" name="PTCAL"/>
        </register>
        <register caption="XROW Fuse" name="XFUSE" offset="0x00CB" size="1">
          <bitfield caption="CP2 Output on Port ckout" mask="0x40" name="CKOUT"/>
          <bitfield caption="NVM Variable Programming Time Enable" mask="0x10" name="NVPTE"/>
          <bitfield caption="EEPROM Programming Time" mask="0x0C" name="E2PT"/>
          <bitfield caption="Flash Memory Programming Time" mask="0x03" name="FLPT"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="CHFLT">
      <register-group caption="" name="CHFLT">
        <register caption="Channel Filter Configuration Register" name="CHCR" offset="0x00AF" size="1">
          <bitfield caption="Bandwidth Mode" mask="0x0F" name="BWM"/>
        </register>
        <register caption="Channel Filter Down Sampling Register" name="CHDN" offset="0x00B0" size="1">
          <bitfield caption="ADC Down Sampling Configuration" mask="0x20" name="ADCDN"/>
          <bitfield caption="Baseband Filter Down Sampling Ratio" mask="0x1F" name="BBDN"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="CLK">
      <register-group caption="" name="CLK">
        <register caption="Clock output control Register" name="CLKOCR" offset="0x00CA" size="1">
          <bitfield caption="Clock Output Driver Enable" mask="0x04" name="CLKOEN"/>
          <bitfield caption="Clock Output Source" mask="0x03" name="CLKOS" values="CLOCK_OUTPUT_SOURCE"/>
        </register>
        <register caption="Clock Output Divider" name="CLKOD" offset="0x00C9" size="1" mask="0xFF"/>
        <register caption="Clock Prescaler" name="CLPR" offset="0x005C" size="1">
          <bitfield caption="Clock Prescaler Change Enable" mask="0x80" name="CLPCE"/>
          <bitfield caption="Timer Clock Prescaler Select" mask="0x38" name="CLTPS" values="CPU_CLT_PRESCALE_3BITS_SMALL"/>
          <bitfield caption="System Clock Prescaler Select" mask="0x07" name="CLKPS" values="CPU_CLK_PRESCALE_3BITS_SMALL"/>
        </register>
        <register caption="Clock Management Control Register" name="CMCR" offset="0x005A" size="1">
          <bitfield caption="Clock Management Control Change Enable" mask="0x80" name="CMCCE"/>
          <bitfield caption="Clock Monitor Enable" mask="0x40" name="CMONEN"/>
          <bitfield caption="Core Clock Select" mask="0x08" name="CCS"/>
          <bitfield caption="Clock Management Mode" mask="0x07" name="CMM" values="CLOCK_MANAGEMENT_MODE"/>
        </register>
        <register caption="Clock Management Interrupt Mask Register" name="CMIMR" offset="0x005B" size="1">
          <bitfield caption="External Clock Interrupt Enable" mask="0x01" name="ECIE"/>
        </register>
        <register caption="Clock Management Override Control Register" name="CMOCR" offset="0x00CF" size="1">
          <bitfield caption="SRC Oscillator Active" mask="0x08" name="SRCACT"/>
          <bitfield caption="FRC Oscillator Active" mask="0x04" name="FRCACT"/>
          <bitfield caption="SRC Oscillator Always On" mask="0x02" name="SRCAO"/>
          <bitfield caption="FRC Oscillator Always On" mask="0x01" name="FRCAO"/>
        </register>
        <register caption="Clock Management Status Register" name="CMSR" offset="0x00CE" size="1">
          <bitfield caption="External Clock Fail" mask="0x01" name="ECF"/>
        </register>
        <register caption="Power Reduction Register 0" name="PRR0" offset="0x0021" size="1">
          <bitfield caption="Power Reduction Trace Unit" mask="0x80" name="PRTRC"/>
          <bitfield caption="Power Reduction UART" mask="0x40" name="PRUART"/>
          <bitfield caption="Power Reduction Clock Output" mask="0x20" name="PRCO"/>
          <bitfield caption="Power Reduction Voltage Monitor" mask="0x10" name="PRVM"/>
          <bitfield caption="Power Reduction CRC" mask="0x08" name="PRCRC"/>
          <bitfield caption="Power Reduction Transmit DSP Control" mask="0x04" name="PRTXDC"/>
          <bitfield caption="Power Reduction Receive DSP Control" mask="0x02" name="PRRXDC"/>
          <bitfield caption="Power Reduction Serial Peripheral Interface" mask="0x01" name="PRSPI"/>
        </register>
        <register caption="Power Reduction Register 1" name="PRR1" offset="0x0022" size="1">
          <bitfield caption="Power Reduction Timer 5" mask="0x10" name="PRT5"/>
          <bitfield caption="Power Reduction Timer 4" mask="0x08" name="PRT4"/>
          <bitfield caption="Power Reduction Timer 3" mask="0x04" name="PRT3"/>
          <bitfield caption="Power Reduction Timer 2" mask="0x02" name="PRT2"/>
          <bitfield caption="Power Reduction Timer 1" mask="0x01" name="PRT1"/>
        </register>
        <register caption="Power Reduction Register 2" name="PRR2" offset="0x0023" size="1">
          <bitfield caption="Power Reduction Sequencer State Machine" mask="0x80" name="PRSSM"/>
          <bitfield caption="Power Reduction Tx Modulator" mask="0x40" name="PRTM"/>
          <bitfield caption="Power Reduction RSSI Buffer" mask="0x20" name="PRRS"/>
          <bitfield caption="Power Reduction ID Check" mask="0x10" name="PRIDS"/>
          <bitfield caption="Power Reduction Data FIFO" mask="0x08" name="PRDF"/>
          <bitfield caption="Power Reduction Support FIFO" mask="0x04" name="PRSF"/>
          <bitfield caption="Power Reduction Rx Buffer A" mask="0x02" name="PRXA"/>
          <bitfield caption="Power Reduction Rx Buffer B" mask="0x01" name="PRXB"/>
        </register>
        <register caption="Sleep Mode Control Register" name="SMCR" offset="0x0059" size="1">
          <bitfield caption="Sleep Mode Select" mask="0x06" name="SM" values="CPU_SLEEP_MODE_2BITS"/>
          <bitfield caption="Sleep Mode Enable" mask="0x01" name="SE"/>
        </register>
      </register-group>
      <value-group caption="" name="CLOCK_OUTPUT_SOURCE">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_frc" name="VAL_0x01" value="0x01"/>
        <value caption="clk_adiv" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="CPU_CLT_PRESCALE_3BITS_SMALL">
        <value caption="disabled" name="VAL_0x00" value="0x00"/>
        <value caption="1" name="VAL_0x01" value="0x01"/>
        <value caption="2" name="VAL_0x02" value="0x02"/>
        <value caption="4" name="VAL_0x03" value="0x03"/>
        <value caption="8" name="VAL_0x04" value="0x04"/>
        <value caption="16" name="VAL_0x05" value="0x05"/>
        <value caption="32" name="VAL_0x06" value="0x06"/>
        <value caption="64" name="VAL_0x07" value="0x07"/>
      </value-group>
      <value-group caption="" name="CPU_CLK_PRESCALE_3BITS_SMALL">
        <value caption="1" name="VAL_0x00" value="0x00"/>
        <value caption="2" name="VAL_0x01" value="0x01"/>
        <value caption="4" name="VAL_0x02" value="0x02"/>
        <value caption="8" name="VAL_0x03" value="0x03"/>
        <value caption="16" name="VAL_0x04" value="0x04"/>
        <value caption="32" name="VAL_0x05" value="0x05"/>
        <value caption="64" name="VAL_0x06" value="0x06"/>
        <value caption="128" name="VAL_0x07" value="0x07"/>
      </value-group>
      <value-group caption="Sleep Mode" name="CPU_SLEEP_MODE_2BITS">
        <value caption="Idle" name="IDLE" value="0x00"/>
        <value caption="Power Down" name="PDOWN" value="0x01"/>
        <value caption="Reserved" name="VAL_0x02" value="0x02"/>
        <value caption="Power Off" name="POFF" value="0x03"/>
      </value-group>
      <value-group caption="" name="CLOCK_MANAGEMENT_MODE">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_adiv" name="VAL_0x01" value="0x01"/>
        <value caption="clk_ext" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto6" name="VAL_0x03" value="0x03"/>
        <value caption="clk_xto4" name="VAL_0x04" value="0x04"/>
      </value-group>
    </module>
    <module caption="" name="CPU">
      <register-group caption="" name="CPU">
        <register caption="Debug Wire Data Register" name="DWDR" offset="0x0051" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="MCU Control Register" name="MCUCR" offset="0x002E" size="1">
          <bitfield caption="Port B7 High Side Driver Enable" mask="0x80" name="PB7HS"/>
          <bitfield caption="Port B7 Low Side Driver Enable" mask="0x40" name="PB7LS"/>
          <bitfield caption="Port B4 High Side Driver Enable" mask="0x20" name="PB4HS"/>
          <bitfield caption="Pull-up Resistors Disable" mask="0x10" name="PUD"/>
          <bitfield caption="Enable Port Settings" mask="0x08" name="ENPS"/>
          <bitfield caption="SPI Interrupt Only" mask="0x04" name="SPIIO"/>
          <bitfield caption="Interrupt Vector Select" mask="0x02" name="IVSEL"/>
          <bitfield caption="Interrupt Vector Change Enable" mask="0x01" name="IVCE"/>
        </register>
        <register caption="MCU Status Register" name="MCUSR" offset="0x004B" size="1">
          <bitfield caption="DebugWire Reset Flag" mask="0x10" name="DWRF"/>
          <bitfield caption="Watchdog Reset Flag" mask="0x08" name="WDRF"/>
          <bitfield caption="External Reset Flag" mask="0x02" name="EXTRF"/>
          <bitfield caption="Power-On Reset Flag" mask="0x01" name="PORF"/>
        </register>
        <register caption="Stack Pointer" name="SP" offset="0x005D" size="2" mask="0x07FF"/>
        <register caption="Store Program Memory Control and Status Register" name="SPMCSR" offset="0x0057" size="1">
          <bitfield caption="SPM Interrupt Enable" mask="0x80" name="SPMIE"/>
          <bitfield caption="Boot Lock Bit Set" mask="0x08" name="BLBSET"/>
          <bitfield caption="Page Write" mask="0x04" name="PGWRT"/>
          <bitfield caption="Page Erase" mask="0x02" name="PGERS"/>
          <bitfield caption="Self Programming Enable" mask="0x01" name="SELFPRGEN"/>
        </register>
        <register caption="Status Register" name="SREG" offset="0x005F" size="1">
          <bitfield caption="Global Interrupt Enable" mask="0x80" name="I"/>
          <bitfield caption="Bit Copy Storage" mask="0x40" name="T"/>
          <bitfield caption="Half Carry Flag" mask="0x20" name="H"/>
          <bitfield caption="Sign Bit" mask="0x10" name="S"/>
          <bitfield caption="Two's Complement Overflow Flag" mask="0x08" name="V"/>
          <bitfield caption="Negative Flag" mask="0x04" name="N"/>
          <bitfield caption="Zero Flag" mask="0x02" name="Z"/>
          <bitfield caption="Carry Flag" mask="0x01" name="C"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="CRC">
      <register-group caption="" name="CRC">
        <register caption="CRC Control Register" name="CRCCR" offset="0x0154" size="1">
          <bitfield caption="Reflect Data Output Byte" mask="0x04" name="REFLO"/>
          <bitfield caption="Reflect Data Input Byte" mask="0x02" name="REFLI"/>
          <bitfield caption="CRC Data Register Reset" mask="0x01" name="CRCRS"/>
        </register>
        <register caption="CRC Data Input Register" name="CRCDIR" offset="0x0049" size="1" mask="0xFF"/>
        <register caption="CRC Data Output Register" name="CRCDOR" offset="0x0155" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="DEMOD">
      <register-group caption="" name="DEMOD">
        <register caption="Demodulator Carrier Detect Path A" name="DMCDA" offset="0x00AB" size="1">
          <bitfield caption="Demodulator Carrier Detect Time Path A" mask="0xE0" name="DMCTA"/>
          <bitfield caption="Demodulator Carrier Detect Limit Path A" mask="0x1F" name="DMCLA"/>
        </register>
        <register caption="Demodulator Carrier Detect Path B" name="DMCDB" offset="0x00AA" size="1">
          <bitfield caption="Demodulator Carrier Detect Time Path B" mask="0xE0" name="DMCTB"/>
          <bitfield caption="Demodulator Carrier Detect Limit Path B" mask="0x1F" name="DMCLB"/>
        </register>
        <register caption="Demodulator Control Path A" name="DMCRA" offset="0x00AD" size="1">
          <bitfield caption="Demodulator Automatic Restart Path A" mask="0x80" name="DMARA"/>
          <bitfield caption="Symbol Check with only 1T Path A" mask="0x40" name="SY1TA"/>
          <bitfield caption="Select ASK Demodulation Path A" mask="0x20" name="SASKA"/>
          <bitfield caption="Demodulator PLL Loop Gain Path A" mask="0x1F" name="DMPGA"/>
        </register>
        <register caption="Demodulator Control Path B" name="DMCRB" offset="0x00AC" size="1">
          <bitfield caption="Demodulator Automatic Restart Path B" mask="0x80" name="DMARB"/>
          <bitfield caption="Symbol Check with only 1T Path B" mask="0x40" name="SY1TB"/>
          <bitfield caption="Select ASK Demodulation Path B" mask="0x20" name="SASKB"/>
          <bitfield caption="Demodulator PLL Loop Gain Path B" mask="0x1F" name="DMPGB"/>
        </register>
        <register caption="Demodulator Down Sampling" name="DMDN" offset="0x00AE" size="1">
          <bitfield caption="Demodulator Down-sampling Path B" mask="0xF0" name="DMDNB"/>
          <bitfield caption="Demodulator Down-sampling Path A" mask="0x0F" name="DMDNA"/>
        </register>
        <register caption="Demodulator Mode Path A" name="DMMA" offset="0x00A9" size="1">
          <bitfield caption="Demodulator NRZ Enable Path A" mask="0x80" name="DMNEA"/>
          <bitfield caption="Demodulator Hold Mode Path A" mask="0x40" name="DMHA"/>
          <bitfield caption="Demodulator Data Polarity Path A" mask="0x20" name="DMPA"/>
          <bitfield caption="Demodulator Amplitude Threshold Path A" mask="0x1F" name="DMATA"/>
        </register>
        <register caption="Demodulator Mode Path B" name="DMMB" offset="0x00A8" size="1">
          <bitfield caption="Demodulator NRZ Enable Path B" mask="0x80" name="DMNEB"/>
          <bitfield caption="Demodulator Hold Mode Path B" mask="0x40" name="DMHB"/>
          <bitfield caption="Demodulator Data Polarity Path B" mask="0x20" name="DMPB"/>
          <bitfield caption="Demodulator Amplitude Threshold Path B" mask="0x1F" name="DMATB"/>
        </register>
        <register caption="Demodulator Signal Check Pattern Path A" name="DMPATA" offset="0x00A2" size="1" mask="0xFF"/>
        <register caption="Demodulator Signal Check Pattern Path B" name="DMPATB" offset="0x00A1" size="1" mask="0xFF"/>
        <register caption="Demodulator Pattern Check Control" name="DMPC" offset="0x00A3" size="1">
          <bitfield caption="Pattern Check Enable Path B" mask="0x80" name="PCENB"/>
          <bitfield caption="Pattern Check Signal Path B" mask="0x40" name="PCSIGB"/>
          <bitfield caption="Pattern Check Ignore Amplitude Low Path B" mask="0x20" name="PCIALB"/>
          <bitfield caption="Pattern Check Frequency Tracking Disable Path B" mask="0x10" name="PCFTDB"/>
          <bitfield caption="Pattern Check Enable Path A" mask="0x08" name="PCENA"/>
          <bitfield caption="Pattern Check Signal Path A" mask="0x04" name="PCSIGA"/>
          <bitfield caption="Pattern Check Ignore Amplitude Low Path A" mask="0x02" name="PCIALA"/>
          <bitfield caption="Pattern Check Frequency Tracking Disable Path A" mask="0x01" name="PCFTDA"/>
        </register>
        <register caption="Demodulator Pattern Check Control Path A" name="DMPCA" offset="0x00A5" size="1">
          <bitfield caption="Pattern Select Path A" mask="0xC0" name="PSELA" values="DM_PATTERN_SELECT"/>
          <bitfield caption="Pattern Check Length Path A" mask="0x38" name="PCLENA"/>
          <bitfield caption="Pattern Check Severity Path A" mask="0x07" name="PCSEVA" values="DM_PATTERN_SEVERITY"/>
        </register>
        <register caption="Demodulator Pattern Check Control Path B" name="DMPCB" offset="0x00A4" size="1">
          <bitfield caption="Pattern Select Path B" mask="0xC0" name="PSELB" values="DM_PATTERN_SELECT"/>
          <bitfield caption="Pattern Check Length Path B" mask="0x38" name="PCLENB"/>
          <bitfield caption="Pattern Check Severity Path B" mask="0x07" name="PCSEVB" values="DM_PATTERN_SEVERITY"/>
        </register>
        <register caption="Demodulator Symbol Rate Path A" name="DMSRA" offset="0x00A7" size="1" mask="0xFF"/>
        <register caption="Demodulator Symbol Rate Path B" name="DMSRB" offset="0x00A6" size="1" mask="0xFF"/>
        <register caption="Received Frequency Offset vs Intermediate Frequency Path A" name="RXFOA" offset="0x00A0" size="1" mask="0xFF"/>
        <register caption="Received Frequency Offset vs Intermediate Frequency Path B" name="RXFOB" offset="0x009F" size="1" mask="0xFF"/>
        <register caption="Symbol Check Configuration Path A" name="SYCA" offset="0x009E" size="1">
          <bitfield caption="Symbol Timing Limit Path A" mask="0xF0" name="SYTLA"/>
          <bitfield caption="Symbol Check Size Path A" mask="0x0F" name="SYCSA"/>
        </register>
        <register caption="Symbol Check Configuration Path B" name="SYCB" offset="0x009D" size="1">
          <bitfield caption="Symbol Timing Limit Path B" mask="0xF0" name="SYTLB"/>
          <bitfield caption="Symbol Check Size Path B" mask="0x0F" name="SYCSB"/>
        </register>
      </register-group>
      <value-group caption="Pattern Select" name="DM_PATTERN_SELECT">
        <value caption="1T alternating (0x55 0xAA)" name="VAL_0x00" value="0x00"/>
        <value caption="2T alternating (0x33 0xCC)" name="VAL_0x01" value="0x01"/>
        <value caption="DMPATx defined" name="VAL_0x02" value="0x02"/>
        <value caption="Manchester conformal" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="Pattern Severity" name="DM_PATTERN_SEVERITY">
        <value caption="12.5%" name="VAL_0x00" value="0x00"/>
        <value caption="25%" name="VAL_0x01" value="0x01"/>
        <value caption="37.5%" name="VAL_0x02" value="0x02"/>
        <value caption="50%" name="VAL_0x03" value="0x03"/>
        <value caption="62.5%" name="VAL_0x04" value="0x04"/>
        <value caption="75%" name="VAL_0x05" value="0x05"/>
        <value caption="87.5%" name="VAL_0x06" value="0x06"/>
        <value caption="100%" name="VAL_0x07" value="0x07"/>
      </value-group>
    </module>
    <module caption="" name="DFIFO">
      <register-group caption="" name="DFIFO">
        <register caption="Data FIFO Configuration" name="DFC" offset="0x00E7" size="1">
          <bitfield caption="Data FIFO Direct Read Access Operational Mode" mask="0x80" name="DFDRA"/>
          <bitfield caption="Data FIFO Fill Level Configuration" mask="0x3F" name="DFFLC"/>
        </register>
        <register caption="Data FIFO Data" name="DFD" offset="0x00E5" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="Data FIFO Interrupt Mask" name="DFI" offset="0x00E6" size="1">
          <bitfield caption="Data FIFO Error Interrupt Mask" mask="0x02" name="DFERIM"/>
          <bitfield caption="Data FIFO Fill Level Interrupt Mask" mask="0x01" name="DFFLIM"/>
        </register>
        <register caption="Data FIFO Fill Level" name="DFL" offset="0x00E2" size="1">
          <bitfield caption="Data FIFO Clear" mask="0x80" name="DFCLR"/>
          <bitfield caption="Data FIFO Fill Level Status" mask="0x3F" name="DFFLS"/>
        </register>
        <register caption="Data FIFO Read Pointer" name="DFRP" offset="0x00E4" size="1" mask="0x3F"/>
        <register caption="Data FIFO Status" name="DFS" offset="0x00DF" size="1">
          <bitfield caption="Data FIFO Overflow Flag" mask="0x04" name="DFOFL"/>
          <bitfield caption="Data FIFO Underflow Flag" mask="0x02" name="DFUFL"/>
          <bitfield caption="Data FIFO Fill Level Reached Status Flag" mask="0x01" name="DFFLRF"/>
        </register>
        <register caption="Data FIFO Telegram Length" name="DFTL" offset="0x00E0" size="2" mask="0x0FFF"/>
        <register caption="Data FIFO Write Pointer" name="DFWP" offset="0x00E3" size="1" mask="0x1F"/>
      </register-group>
    </module>
    <module caption="" name="EEPROM">
      <register-group caption="" name="EEPROM">
        <register caption="EEPROM Address Register" name="EEAR" offset="0x0041" size="2" mask="0x07FF"/>
        <register caption="EEPROM Control Register" name="EECR" offset="0x003F" size="1">
          <bitfield caption="Non-Volatile Memory Busy" mask="0x80" name="NVMBSY"/>
          <bitfield caption="EEPROM Page Access" mask="0x40" name="EEPAGE"/>
          <bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM" values="EEP_MODE"/>
          <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
          <bitfield caption="EEPROM Master Write Enable" mask="0x04" name="EEMWE"/>
          <bitfield caption="EEPROM Write Enable" mask="0x02" name="EEWE"/>
          <bitfield caption="EEPROM Read Enable" mask="0x01" name="EERE"/>
        </register>
        <register caption="EEPROM Control Register 2" name="EECR2" offset="0x0168" size="1">
          <bitfield caption="EEPROM Error Correction Flag" mask="0x80" name="EECF"/>
          <bitfield caption="EEPROM Error Fault Flag" mask="0x40" name="EEFF"/>
          <bitfield caption="EEPROM Burst Read Enable" mask="0x01" name="EEBRE"/>
        </register>
        <register caption="EEPROM Data Register" name="EEDR" offset="0x0040" size="1" mask="0xFF"/>
        <register caption="EEPROM Protect Register" name="EEPR" offset="0x0043" size="1">
          <bitfield caption="EEPROM Access Protect" mask="0x0F" name="EEAP"/>
        </register>
        <register caption="EEPROM Status Register" name="EEST" offset="0x016A" size="1">
          <bitfield caption="EEPROM Syndrome" mask="0x0F" name="EESYN"/>
        </register>
        <register caption="Program Memory Status Register" name="PGMST" offset="0x0169" size="1">
          <bitfield caption="Program Memory Syndrome" mask="0x1F" name="PGMSYN"/>
        </register>
      </register-group>
      <value-group caption="" name="EEP_MODE">
        <value caption="Erase and Write in one operation" name="VAL_0x00" value="0x00"/>
        <value caption="Erase Only" name="VAL_0x01" value="0x01"/>
        <value caption="Write Only" name="VAL_0x02" value="0x02"/>
      </value-group>
    </module>
    <module caption="" name="FE">
      <register-group caption="" name="FE">
        <register caption="RF Front End Antenna Switch" name="FEAS" offset="0x0104" size="1">
          <bitfield caption="SPDT RF Switch Tx 3" mask="0x20" name="SDTX3"/>
          <bitfield caption="SPDT RF Switch Rx 3" mask="0x10" name="SDRX3"/>
          <bitfield caption="SPDT RF Switch Tx 2" mask="0x08" name="SDTX2"/>
          <bitfield caption="SPDT RF Switch Rx 2" mask="0x04" name="SDRX2"/>
          <bitfield caption="SPDT RF Switch Tx 1" mask="0x02" name="SDTX1"/>
          <bitfield caption="SPDT RF Switch Rx 1" mask="0x01" name="SDRX1"/>
        </register>
        <register caption="RF Front End Amplifier Bias" name="FEBIA" offset="0x010C" size="1">
          <bitfield caption="IF Amplifier Enable" mask="0x80" name="IFAEN"/>
          <bitfield caption="High Sensitivity Enable" mask="0x40" name="HISEN"/>
        </register>
        <register caption="RF Front End RC Tuning" name="FEBT" offset="0x0107" size="1">
          <bitfield caption="2 Bit Resistor Tuning" mask="0x0C" name="RTN2"/>
          <bitfield caption="2 Bit Capacitor Tuning" mask="0x03" name="CTN2"/>
        </register>
        <register caption="RF Front End Control Register" name="FECR" offset="0x010A" size="1">
          <bitfield caption="ASK Not DPSK Switch" mask="0x20" name="ANPS"/>
          <bitfield caption="PLL Lock Detect Gate" mask="0x10" name="PLCKG"/>
          <bitfield caption="ADC High Sample Rate" mask="0x08" name="ADHS"/>
          <bitfield caption="Antenna Damping" mask="0x04" name="ANDP"/>
          <bitfield caption="Select 433MHz Not 315MHz Band" mask="0x02" name="S4N3"/>
          <bitfield caption="Low-Band Not High-Band" mask="0x01" name="LBNHB"/>
        </register>
        <register caption="RF Front End Enable 1" name="FEEN1" offset="0x0101" size="1">
          <bitfield caption="PLL Speedup 1" mask="0x40" name="PLSP1"/>
          <bitfield caption="ADC Clock Enable" mask="0x20" name="ADCLK"/>
          <bitfield caption="Analog Digital Converter Enable" mask="0x10" name="ADEN"/>
          <bitfield caption="Low Noise Amplifier Enable" mask="0x08" name="LNAEN"/>
          <bitfield caption="Crystal Oscillator Enable" mask="0x04" name="XTOEN"/>
          <bitfield caption="PLL Calibration Mode" mask="0x02" name="PLCAL"/>
          <bitfield caption="PLL Enable" mask="0x01" name="PLEN"/>
        </register>
        <register caption="RF Front End Enable 2" name="FEEN2" offset="0x0102" size="1">
          <bitfield caption="XTO External Clock" mask="0x80" name="XTOEXT"/>
          <bitfield caption="XTO Voltage Pump Enable" mask="0x20" name="XTPEN"/>
          <bitfield caption="PLL Post Enable" mask="0x10" name="PLPEN"/>
          <bitfield caption="Temperature Measurement" mask="0x08" name="TMPM"/>
          <bitfield caption="Power Amplifier Enable" mask="0x04" name="PAEN"/>
        </register>
        <register caption="RF Front End LNA Bias" name="FELNA" offset="0x0103" size="1">
          <bitfield caption="LNA Bias High Sense Mode" mask="0xF0" name="LNABH"/>
          <bitfield caption="LNA Bias Normal Sense Mode" mask="0x0F" name="LNABN"/>
        </register>
        <register caption="RF Front End Main and Swallow Counter" name="FEMS" offset="0x0108" size="1">
          <bitfield caption="PLL Main" mask="0xF0" name="PLLM"/>
          <bitfield caption="PLL Swallow" mask="0x0F" name="PLLS"/>
        </register>
        <register caption="RF Front End Power Amplifier Control" name="FEPAC" offset="0x0105" size="1">
          <bitfield caption="RF Front End Power Amplifier Control" mask="0xFF" name="FEPAC" values="FE_POWER_AMPLIFIER_CONTROL"/>
        </register>
        <register caption="RF Front End Status Register" name="FESR" offset="0x0100" size="1">
          <bitfield caption="PLL Locked" mask="0x08" name="PLCK"/>
          <bitfield caption="XTO Ready" mask="0x04" name="XRDY"/>
          <bitfield caption="LNA Saturated" mask="0x01" name="SAT"/>
        </register>
        <register caption="RF Front End RC Tuning 4bit Register" name="FETN4" offset="0x0109" size="1">
          <bitfield caption="4 Bit Resistor Tuning" mask="0xF0" name="RTN4"/>
          <bitfield caption="4 Bit Capacitor Tuning" mask="0x0F" name="CTN4"/>
        </register>
        <register caption="RF Front End VCO and PLL Control" name="FEVCO" offset="0x010B" size="1">
          <bitfield caption="VCO Bias" mask="0xF0" name="VCOB"/>
          <bitfield caption="Charge Pump Current Control" mask="0x0F" name="CPCC"/>
        </register>
        <register caption="RF Front End VCO Tuning" name="FEVCT" offset="0x0106" size="1" mask="0x0F"/>
        <register caption="RF Front End Spare Register 1" name="SPARE1" offset="0x010D" size="1">
          <bitfield caption="Calibration of High Band Image Rejection" mask="0xFF" name="CHBIR"/>
        </register>
      </register-group>
      <value-group caption="" name="FE_POWER_AMPLIFIER_CONTROL">
        <value caption="-11.80  -12.90" name="VAL_0x00" value="0x00"/>
        <value caption="-11.30  -12.33" name="VAL_0x01" value="0x01"/>
        <value caption="-10.70  -11.76" name="VAL_0x02" value="0x02"/>
        <value caption="-10.20  -11.10" name="VAL_0x03" value="0x03"/>
        <value caption=" -9.70  -10.60" name="VAL_0x04" value="0x04"/>
        <value caption=" -9.20  -10.00" name="VAL_0x05" value="0x05"/>
        <value caption=" -8.60   -9.50" name="VAL_0x06" value="0x06"/>
        <value caption=" -8.00   -9.00" name="VAL_0x07" value="0x07"/>
        <value caption=" -7.50   -8.50" name="VAL_0x08" value="0x08"/>
        <value caption=" -7.00   -7.90" name="VAL_0x09" value="0x09"/>
        <value caption=" -6.40   -7.30" name="VAL_0x0A" value="0x0A"/>
        <value caption=" -5.90   -6.80" name="VAL_0x0B" value="0x0B"/>
        <value caption=" -5.30   -6.30" name="VAL_0x0C" value="0x0C"/>
        <value caption=" -4.77   -5.70" name="VAL_0x0D" value="0x0D"/>
        <value caption=" -4.17   -5.20" name="VAL_0x0E" value="0x0E"/>
        <value caption=" -3.67   -4.60" name="VAL_0x0F" value="0x0F"/>
        <value caption=" -3.12   -4.07" name="VAL_0x10" value="0x10"/>
        <value caption=" -2.56   -3.47" name="VAL_0x11" value="0x11"/>
        <value caption=" -2.10   -2.97" name="VAL_0x12" value="0x12"/>
        <value caption=" -1.58   -2.42" name="VAL_0x13" value="0x13"/>
        <value caption=" -1.08   -1.86" name="VAL_0x14" value="0x14"/>
        <value caption=" -0.50   -1.40" name="VAL_0x15" value="0x15"/>
        <value caption="  0.00   -0.88" name="VAL_0x16" value="0x16"/>
        <value caption="  0.41   -0.38" name="VAL_0x17" value="0x17"/>
        <value caption="  1.00    0.20 " name="VAL_0x18" value="0x18"/>
        <value caption="  1.42    0.70 " name="VAL_0x19" value="0x19"/>
        <value caption="  1.83    1.11 " name="VAL_0x1A" value="0x1A"/>
        <value caption="  2.42    1.70 " name="VAL_0x1B" value="0x1B"/>
        <value caption="  2.88    2.12 " name="VAL_0x1C" value="0x1C"/>
        <value caption="  3.38    2.53 " name="VAL_0x1D" value="0x1D"/>
        <value caption="  3.81    3.12 " name="VAL_0x1E" value="0x1E"/>
        <value caption="  4.31    3.58 " name="VAL_0x1F" value="0x1F"/>
        <value caption="  4.72    4.08 " name="VAL_0x20" value="0x20"/>
        <value caption="  5.09    4.51 " name="VAL_0x21" value="0x21"/>
        <value caption="  5.57    5.01 " name="VAL_0x22" value="0x22"/>
        <value caption="  6.00    5.42 " name="VAL_0x23" value="0x23"/>
        <value caption="  6.41    5.79 " name="VAL_0x24" value="0x24"/>
        <value caption="  6.77    6.27 " name="VAL_0x25" value="0x25"/>
        <value caption="  7.19    6.70 " name="VAL_0x26" value="0x26"/>
        <value caption="  7.55    7.11 " name="VAL_0x27" value="0x27"/>
        <value caption="  7.98    7.47 " name="VAL_0x28" value="0x28"/>
        <value caption="  8.40    7.89 " name="VAL_0x29" value="0x29"/>
        <value caption="  8.79    8.25 " name="VAL_0x2A" value="0x2A"/>
        <value caption="  9.11    8.68 " name="VAL_0x2B" value="0x2B"/>
        <value caption="  9.46    9.10 " name="VAL_0x2C" value="0x2C"/>
        <value caption="  9.82    9.49 " name="VAL_0x2D" value="0x2D"/>
        <value caption=" 10.18    9.81 " name="VAL_0x2E" value="0x2E"/>
        <value caption=" 10.60   10.16" name="VAL_0x2F" value="0x2F"/>
        <value caption=" 10.89   10.52" name="VAL_0x30" value="0x30"/>
        <value caption=" 11.30   10.88" name="VAL_0x31" value="0x31"/>
        <value caption=" 11.62   11.30" name="VAL_0x32" value="0x32"/>
        <value caption=" 12.06   11.59" name="VAL_0x33" value="0x33"/>
        <value caption=" 12.39   12.00" name="VAL_0x34" value="0x34"/>
        <value caption=" 12.82   12.32" name="VAL_0x35" value="0x35"/>
        <value caption=" 13.22   12.76" name="VAL_0x36" value="0x36"/>
        <value caption=" 13.58   13.09" name="VAL_0x37" value="0x37"/>
        <value caption=" 13.95   13.52" name="VAL_0x38" value="0x38"/>
        <value caption=" 14.22   13.92" name="VAL_0x39" value="0x39"/>
        <value caption=" 14.41   14.28" name="VAL_0x3A" value="0x3A"/>
        <value caption=" 14.49   14.65" name="VAL_0x3B" value="0x3B"/>
        <value caption=" 14.60   14.65" name="VAL_0x3C" value="0x3C"/>
        <value caption=" 14.60   14.65" name="VAL_0x3D" value="0x3D"/>
        <value caption=" 14.60   14.65" name="VAL_0x3E" value="0x3E"/>
        <value caption=" 14.60   14.65" name="VAL_0x3F" value="0x3F"/>
      </value-group>
    </module>
    <module caption="" name="FREQS">
      <register-group caption="" name="FREQS">
        <register caption="Fractional Frequency 1 High Byte" name="FFREQ1H" offset="0x0066" size="1" mask="0x03"/>
        <register caption="Fractional Frequency 1 Low Byte" name="FFREQ1L" offset="0x0064" size="1" mask="0xFF"/>
        <register caption="Fractional Frequency 1 Middle Byte" name="FFREQ1M" offset="0x0065" size="1" mask="0xFF"/>
        <register caption="Fractional Frequency 2 High Byte" name="FFREQ2H" offset="0x0069" size="1" mask="0x03"/>
        <register caption="Fractional Frequency 2 Low Byte" name="FFREQ2L" offset="0x0067" size="1" mask="0xFF"/>
        <register caption="Fractional Frequency 2 Middle Byte" name="FFREQ2M" offset="0x0068" size="1" mask="0xFF"/>
        <register caption="Frequency Synthesizer Control Register" name="FSCR" offset="0x002B" size="1">
          <bitfield caption="Power Amplifier Output is On" mask="0x80" name="PAON"/>
          <bitfield caption="Power Amplifier Output Enable Register" mask="0x10" name="PAOER"/>
          <bitfield caption="Tx Modulation Source" mask="0x0C" name="TXMS" values="TX_MODULATION_SOURCE"/>
          <bitfield caption="Select FSK Modulation" mask="0x02" name="SFM"/>
          <bitfield caption="Tx Modulation" mask="0x01" name="TXMOD"/>
        </register>
        <register caption="Frequency Synthesizer Enable" name="FSEN" offset="0x0060" size="1">
          <bitfield caption="ASK Shaping Enable" mask="0x10" name="ASEN"/>
          <bitfield caption="Pre-emphasis Filtering Enable" mask="0x08" name="PEEN"/>
          <bitfield caption="Gauss Filtering Enable" mask="0x04" name="GAEN"/>
          <bitfield caption="Sigma-delta Modulator Enable" mask="0x02" name="SDEN"/>
          <bitfield caption="Sigma-delta Modulator Power Up" mask="0x01" name="SDPU"/>
        </register>
        <register caption="Frequency Synthesizer Filter Control Register" name="FSFCR" offset="0x0061" size="1">
          <bitfield caption="ASK Shaping Divider" mask="0xF0" name="ASDIV"/>
          <bitfield caption="Gauss Filter BT Selection" mask="0x03" name="BTSEL" values="GAUSS_BT_SELECT"/>
        </register>
        <register caption="Gauss Clock Divider" name="GACDIV" offset="0x0062" size="2" mask="0x1FFF"/>
      </register-group>
      <value-group caption="" name="TX_MODULATION_SOURCE">
        <value caption="TXMOD Register" name="VAL_0x00" value="0x00"/>
        <value caption="TMDI Input" name="VAL_0x01" value="0x01"/>
        <value caption="Tx Modulator Serial Out" name="VAL_0x02" value="0x02"/>
      </value-group>
      <value-group caption="" name="GAUSS_BT_SELECT">
        <value caption="BT=2" name="VAL_0x00" value="0x00"/>
        <value caption="BT=1.5" name="VAL_0x01" value="0x01"/>
        <value caption="BT=1" name="VAL_0x02" value="0x02"/>
        <value caption="BT=0.5" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="FRSYNC">
      <register-group caption="" name="FRSYNC">
        <register caption="Start Frame ID Byte 1 Path A" name="SFID1A" offset="0x00C1" size="1" mask="0xFF"/>
        <register caption="Start Frame ID Byte 1 Path B" name="SFID1B" offset="0x00B5" size="1" mask="0xFF"/>
        <register caption="Start Frame ID Byte 2 Path A" name="SFID2A" offset="0x00C2" size="1" mask="0xFF"/>
        <register caption="Start Frame ID Byte 2 Path B" name="SFID2B" offset="0x00B6" size="1" mask="0xFF"/>
        <register caption="Start Frame ID Byte 3 Path A" name="SFID3A" offset="0x00C3" size="1" mask="0xFF"/>
        <register caption="Start Frame ID Byte 3 Path B" name="SFID3B" offset="0x00B7" size="1" mask="0xFF"/>
        <register caption="Start Frame ID Byte 4 Path A" name="SFID4A" offset="0x00C4" size="1" mask="0xFF"/>
        <register caption="Start Frame ID Byte 4 Path B" name="SFID4B" offset="0x00B8" size="1" mask="0xFF"/>
        <register caption="Start Frame ID Configuration Path A" name="SFIDCA" offset="0x00BD" size="1">
          <bitfield caption="Serial Mode Enable Path A" mask="0x80" name="SEMEA"/>
          <bitfield caption="Start Frame ID Threshold Path A" mask="0x1F" name="SFIDTA"/>
        </register>
        <register caption="Start Frame ID Configuration Path B" name="SFIDCB" offset="0x00B1" size="1">
          <bitfield caption="Serial Mode Enable Path B" mask="0x80" name="SEMEB"/>
          <bitfield caption="Start Frame ID Threshold Path B" mask="0x1F" name="SFIDTB"/>
        </register>
        <register caption="Start Frame ID Length Path A" name="SFIDLA" offset="0x00BE" size="1" mask="0x3F"/>
        <register caption="Start Frame ID Length Path B" name="SFIDLB" offset="0x00B2" size="1" mask="0x3F"/>
        <register caption="Wake-Up Pattern Byte 1 Path A" name="WUP1A" offset="0x00C5" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Byte 1 Path B" name="WUP1B" offset="0x00B9" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Byte 2 Path A" name="WUP2A" offset="0x00C6" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Byte 2 Path B" name="WUP2B" offset="0x00BA" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Byte 3 Path A" name="WUP3A" offset="0x00C7" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Byte 3 Path B" name="WUP3B" offset="0x00BB" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Byte 4 Path A" name="WUP4A" offset="0x00C8" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Byte 4 Path B" name="WUP4B" offset="0x00BC" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Length Path A" name="WUPLA" offset="0x00C0" size="1" mask="0x3F"/>
        <register caption="Wake-Up Pattern Length Path B" name="WUPLB" offset="0x00B4" size="1" mask="0x3F"/>
        <register caption="Wake-Up Pattern Threshold Path A" name="WUPTA" offset="0x00BF" size="1" mask="0x1F"/>
        <register caption="Wake-Up Pattern Threshold Path B" name="WUPTB" offset="0x00B3" size="1" mask="0x1F"/>
      </register-group>
    </module>
    <module caption="" name="GPIOREGS">
      <register-group caption="" name="GPIOREGS">
        <register caption="General Purpose I/O Register 0" name="GPIOR0" offset="0x003A" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 1" name="GPIOR1" offset="0x0044" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 2" name="GPIOR2" offset="0x0045" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 3" name="GPIOR3" offset="0x003B" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 4" name="GPIOR4" offset="0x003C" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 5" name="GPIOR5" offset="0x003D" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 6" name="GPIOR6" offset="0x003E" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="IDCHK">
      <register-group caption="" name="IDCHK">
        <register caption="ID Check Byte 0" name="IDB0" offset="0x0156" size="1" mask="0xFF"/>
        <register caption="ID Check Byte 1" name="IDB1" offset="0x0157" size="1" mask="0xFF"/>
        <register caption="ID Check Byte 2" name="IDB2" offset="0x0158" size="1" mask="0xFF"/>
        <register caption="ID Check Byte 3" name="IDB3" offset="0x0159" size="1" mask="0xFF"/>
        <register caption="ID Check Configuration" name="IDC" offset="0x015A" size="1">
          <bitfield caption="ID Check Execute" mask="0x80" name="IDCE"/>
          <bitfield caption="ID Clear" mask="0x40" name="IDCLR"/>
          <bitfield caption="ID Full Interrupt Mask" mask="0x20" name="IDFIM"/>
          <bitfield caption="ID Byte Offset" mask="0x0C" name="IDBO"/>
          <bitfield caption="ID Length" mask="0x03" name="IDL"/>
        </register>
        <register caption="ID Check Status" name="IDS" offset="0x015B" size="1">
          <bitfield caption="ID Full Flag" mask="0x02" name="IDFULL"/>
          <bitfield caption="ID Check Ok Flag" mask="0x01" name="IDOK"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="INT">
      <register-group caption="" name="INT">
        <register caption="External Interrupt Control Register A" name="EICRA" offset="0x006B" size="1">
          <bitfield caption="Interrupt Sense Control 1" mask="0x0C" name="ISC1" values="INTERRUPT_SENSE_CONTROL"/>
          <bitfield caption="Interrupt Sense Control 0" mask="0x03" name="ISC0" values="INTERRUPT_SENSE_CONTROL"/>
        </register>
        <register caption="External Interrupt Flag Register" name="EIFR" offset="0x0048" size="1">
          <bitfield caption="External Interrupt Flag 1" mask="0x02" name="INTF1"/>
          <bitfield caption="External Interrupt Flag 0" mask="0x01" name="INTF0"/>
        </register>
        <register caption="External Interrupt Mask" name="EIMSK" offset="0x0047" size="1">
          <bitfield caption="External Interrupt Request 1 Enable" mask="0x02" name="INT1"/>
          <bitfield caption="External Interrupt Request 0 Enable" mask="0x01" name="INT0"/>
        </register>
        <register caption="Pin Change Interrupt Control Register" name="PCICR" offset="0x0046" size="1">
          <bitfield caption="Pin Change Interrupt Enable 1" mask="0x02" name="PCIE1"/>
          <bitfield caption="Pin Change Interrupt Enable 0" mask="0x01" name="PCIE0"/>
        </register>
        <register caption="Pin Change Interrupt Flag Register" name="PCIFR" offset="0x002F" size="1">
          <bitfield caption="Pin Change Interrupt Flag 1" mask="0x02" name="PCIF1"/>
          <bitfield caption="Pin Change Interrupt Flag 0" mask="0x01" name="PCIF0"/>
        </register>
        <register caption="Pin Change Mask Register 0" name="PCMSK0" offset="0x006C" size="1">
          <bitfield caption="Pin Change Enable Mask" mask="0xFF" name="PCINT"/>
        </register>
        <register caption="Pin Change Mask Register 1" name="PCMSK1" offset="0x006D" size="1">
          <bitfield caption="Pin Change Enable Mask" mask="0x3F" name="PCINT" lsb="8"/>
        </register>
      </register-group>
      <value-group caption="Interrupt Sense Control" name="INTERRUPT_SENSE_CONTROL">
        <value caption="Low Level of INTX" name="VAL_0x00" value="0x00"/>
        <value caption="Logical Change of INTX" name="VAL_0x01" value="0x01"/>
        <value caption="Falling Edge of INTX" name="VAL_0x02" value="0x02"/>
        <value caption="Rising Edge of INTX" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="LIN_UART">
      <register-group caption="" name="LIN_UART">
        <register caption="LIN/UART Baud Rate Register High Byte" name="LINBRRH" offset="0x0179" size="1">
          <bitfield caption="LIN/UART Clock Divider" mask="0x0F" name="LDIV" lsb="8"/>
        </register>
        <register caption="LIN/UART Baud Rate Register Low Byte" name="LINBRRL" offset="0x0178" size="1">
          <bitfield caption="LIN/UART Clock Divider" mask="0xFF" name="LDIV"/>
        </register>
        <register caption="LIN/UART Bit Timing Register" name="LINBTR" offset="0x0177" size="1">
          <bitfield caption="LIN/UART Disable Bit Timing Resynchronization" mask="0x80" name="LDISR"/>
          <bitfield caption="LIN/UART Bit Timing" mask="0x3F" name="LBT"/>
        </register>
        <register caption="LIN/UART Control Register" name="LINCR" offset="0x0173" size="1">
          <bitfield caption="LIN/UART Software Reset" mask="0x80" name="LSWRES"/>
          <bitfield caption="LIN 1.3 Mode" mask="0x40" name="LIN13"/>
          <bitfield caption="LIN/UART Configuration" mask="0x30" name="LCONF"/>
          <bitfield caption="LIN/UART Enable" mask="0x08" name="LENA"/>
          <bitfield caption="LIN/UART Command and Mode" mask="0x07" name="LCMD"/>
        </register>
        <register caption="LIN/UART Data Register" name="LINDAT" offset="0x017D" size="1" ocd-rw="">
          <bitfield caption="LIN/UART Data" mask="0xFF" name="LDATA"/>
        </register>
        <register caption="LIN/UART Data Length Register" name="LINDLR" offset="0x017A" size="1">
          <bitfield caption="LIN Transmit Data Length" mask="0xF0" name="LTXDL"/>
          <bitfield caption="LIN Receive Data Length" mask="0x0F" name="LRXDL"/>
        </register>
        <register caption="LIN/UART Enable Interrupt Register" name="LINENIR" offset="0x0175" size="1">
          <bitfield caption="LIN/UART Enable Error Interrupt" mask="0x08" name="LENERR"/>
          <bitfield caption="LIN Enable Identifier Ok Interrupt" mask="0x04" name="LENIDOK"/>
          <bitfield caption="LIN/UART Enable Transmit Ok Interrupt" mask="0x02" name="LENTXOK"/>
          <bitfield caption="LIN/UART Enable Receive Ok Interrupt" mask="0x01" name="LENRXOK"/>
        </register>
        <register caption="LIN/UART Error Register" name="LINERR" offset="0x0176" size="1">
          <bitfield caption="LIN Abort Flag" mask="0x80" name="LABORT"/>
          <bitfield caption="LIN Frame Time Out Error Flag" mask="0x40" name="LTOERR"/>
          <bitfield caption="LIN/UART Overrun Error Flag" mask="0x20" name="LOVERR"/>
          <bitfield caption="LIN/UART Framing Error Flag" mask="0x10" name="LFERR"/>
          <bitfield caption="LIN Synchronization Error Flag" mask="0x08" name="LSERR"/>
          <bitfield caption="LIN Parity Error Flag" mask="0x04" name="LPERR"/>
          <bitfield caption="LIN Checksum Error Flag" mask="0x02" name="LCERR"/>
          <bitfield caption="LIN Bit Error Flag" mask="0x01" name="LBERR"/>
        </register>
        <register caption="LIN/UART Identifier Register" name="LINIDR" offset="0x017B" size="1">
          <bitfield caption="LIN Parity" mask="0xC0" name="LP"/>
          <bitfield caption="LIN Identifier" mask="0x3F" name="LID"/>
        </register>
        <register caption="LIN/UART Data Buffer Selection" name="LINSEL" offset="0x017C" size="1">
          <bitfield caption="LIN Auto Increment of Data Buffer Index Disable" mask="0x08" name="LAINC"/>
          <bitfield caption="LIN Data Buffer Index" mask="0x07" name="LINDX"/>
        </register>
        <register caption="LIN Status and Interrupt Register" name="LINSIR" offset="0x0174" size="1">
          <bitfield caption="LIN Identifier Status" mask="0xE0" name="LIDST"/>
          <bitfield caption="LIN/UART Busy Flag" mask="0x10" name="LBUSY"/>
          <bitfield caption="LIN/UART Error Flag" mask="0x08" name="LERR"/>
          <bitfield caption="LIN Identifier Ok Flag" mask="0x04" name="LIDOK"/>
          <bitfield caption="LIN/UART Transmit Ok Flag" mask="0x02" name="LTXOK"/>
          <bitfield caption="LIN/UART Receive Ok Flag" mask="0x01" name="LRXOK"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="OCCOUNT">
      <register-group caption="" name="OCCOUNT">
        <register caption="Oscillator Calibration Counter Value" name="OCCNT" offset="0x0171" size="1" mask="0xFF"/>
        <register caption="Oscillator Calibration Counter Configuration Register" name="OCCR" offset="0x0170" size="1">
          <bitfield caption="Oscillator Calibration Select Target" mask="0x02" name="OCSEL"/>
          <bitfield caption="Oscillator Calibration Counter Enable" mask="0x01" name="OCEN"/>
        </register>
        <register caption="Oscillator Calibration Counter Gate" name="OCGATE" offset="0x0172" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="PORTB">
      <register-group caption="" name="PORTB">
        <register caption="Port B Input Pins" name="PINB" offset="0x0025" size="1" mask="0xFF"/>
        <register caption="Port B Data Direction" name="DDRB" offset="0x0026" size="1" mask="0xFF"/>
        <register caption="Port B Data Register" name="PORTB" offset="0x0027" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="PORTC">
      <register-group caption="" name="PORTC">
        <register caption="Port C Input Pins" name="PINC" offset="0x0028" size="1" mask="0x3F"/>
        <register caption="Port C Data Direction" name="DDRC" offset="0x0029" size="1" mask="0x3F"/>
        <register caption="Port C Data Register" name="PORTC" offset="0x002A" size="1" mask="0x3F"/>
      </register-group>
    </module>
    <module caption="" name="PORTS">
      <register-group caption="" name="PORTS">
        <register caption="Debounce Control Register" name="DBCR" offset="0x0161" size="1">
          <bitfield caption="Debounce Timer Mask Select" mask="0x04" name="DBTMS"/>
          <bitfield caption="Debounce Clock Select" mask="0x02" name="DBCS"/>
          <bitfield caption="Debounce Mode" mask="0x01" name="DBMD"/>
        </register>
        <register caption="Debounce Enable Port B" name="DBENB" offset="0x0163" size="1" mask="0xFF"/>
        <register caption="Debounce Enable Port C" name="DBENC" offset="0x0164" size="1" mask="0x3F"/>
        <register caption="Debug Support Switch" name="DBGSW" offset="0x0165" size="1">
          <bitfield caption="Debug Support Switch Enable" mask="0x80" name="DBGSE"/>
          <bitfield caption="CPU Busy Flag" mask="0x40" name="CPBF"/>
          <bitfield caption="CPU Busy Flag Output Select" mask="0x30" name="CPBFOS" values="CPU_BUSY_FLAG_OUT"/>
          <bitfield caption="Debug Support Group Select" mask="0x0F" name="DBGGS"/>
        </register>
        <register caption="Debounce Timer Compare" name="DBTC" offset="0x0162" size="1" mask="0xFF"/>
      </register-group>
      <value-group caption="CPU Busy Flag Output" name="CPU_BUSY_FLAG_OUT">
        <value caption="no output" name="VAL_0x00" value="0x00"/>
        <value caption="PB0" name="VAL_0x01" value="0x01"/>
        <value caption="PB4" name="VAL_0x02" value="0x02"/>
        <value caption="PC1" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="RSSIB">
      <register-group caption="" name="RSSIB">
        <register caption="RSSI Compensation Register" name="RSCOM" offset="0x016F" size="1">
          <bitfield caption="RSSI LNA High Sensitivity Compensation" mask="0x04" name="RSHISC"/>
          <bitfield caption="RSSI IF Amplifier Compensation" mask="0x02" name="RSIFC"/>
          <bitfield caption="RSSI Damping Compensation" mask="0x01" name="RSDC"/>
        </register>
        <register caption="RSSI High Band Damping Value" name="RSHDV" offset="0x016E" size="1" mask="0xFF"/>
        <register caption="RSSI LNA High Sensitivity Gain" name="RSHSG" offset="0x016B" size="1" mask="0xFF"/>
        <register caption="RSSI IF Amplifier Gain" name="RSIFG" offset="0x016C" size="1" mask="0xFF"/>
        <register caption="RSSI Low Band Damping Value" name="RSLDV" offset="0x016D" size="1" mask="0xFF"/>
        <register caption="RSSI Average Value" name="RSSAV" offset="0x015C" size="1" mask="0xFF"/>
        <register caption="RSSI Configuration Register" name="RSSC" offset="0x0160" size="1">
          <bitfield caption="RSSI Peak Values to SFIFO" mask="0x40" name="RSPKF"/>
          <bitfield caption="RSSI High Band Reception" mask="0x20" name="RSHRX"/>
          <bitfield caption="RSSI Within Low and High Limits" mask="0x10" name="RSWLH"/>
          <bitfield caption="RSSI Update Period" mask="0x0F" name="RSUP"/>
        </register>
        <register caption="RSSI High Threshold" name="RSSH" offset="0x015F" size="1" mask="0xFF"/>
        <register caption="RSSI Low Threshold" name="RSSL" offset="0x015E" size="1" mask="0xFF"/>
        <register caption="RSSI Peak Value" name="RSSPK" offset="0x015D" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="RXBUF">
      <register-group caption="" name="RXBUF">
        <register caption="Rx Buffer Configuration 1" name="RXBC1" offset="0x013E" size="1">
          <bitfield caption="Receive Data LSB-First Path B" mask="0x80" name="RXLSBB"/>
          <bitfield caption="Receive CRC Bit Length Path B" mask="0x60" name="RXCBLB" values="RXBUF_CRC_LENGTH"/>
          <bitfield caption="RX CRC Enable data path B" mask="0x10" name="RXCEB"/>
          <bitfield caption="Receive Data LSB-First Path A" mask="0x08" name="RXLSBA"/>
          <bitfield caption="Receive CRC Bit Length Path A" mask="0x06" name="RXCBLA" values="RXBUF_CRC_LENGTH"/>
          <bitfield caption="RX CRC Enable data path A" mask="0x01" name="RXCEA"/>
        </register>
        <register caption="Rx Buffer Configuration 2" name="RXBC2" offset="0x013F" size="1">
          <bitfield caption="RX Buffer Clear" mask="0x04" name="RXBCLR"/>
          <bitfield caption="RX Buffer Finish" mask="0x02" name="RXBF"/>
          <bitfield caption="RX Buffer Path Select" mask="0x01" name="RXBPB"/>
        </register>
        <register caption="Rx CRC Init Value High Byte Path A" name="RXCIHA" offset="0x0150" size="1" mask="0xFF"/>
        <register caption="Rx CRC Init Value High Byte Path B" name="RXCIHB" offset="0x0146" size="1" mask="0xFF"/>
        <register caption="Rx CRC Init Value Low Byte Path A" name="RXCILA" offset="0x014F" size="1" mask="0xFF"/>
        <register caption="Rx CRC Init Value Low Byte Path B" name="RXCILB" offset="0x0145" size="1" mask="0xFF"/>
        <register caption="Rx CRC Polynomial High Byte Path A" name="RXCPHA" offset="0x0152" size="1" mask="0xFF"/>
        <register caption="Rx CRC Polynomial High Byte Path B" name="RXCPHB" offset="0x0148" size="1" mask="0xFF"/>
        <register caption="Rx CRC Polynomial Low Byte Path A" name="RXCPLA" offset="0x0151" size="1" mask="0xFF"/>
        <register caption="Rx CRC Polynomial Low Byte Path B" name="RXCPLB" offset="0x0147" size="1" mask="0xFF"/>
        <register caption="Rx CRC Result High Byte Path A" name="RXCRHA" offset="0x014D" size="1" mask="0xFF"/>
        <register caption="Rx CRC Result High Byte Path B" name="RXCRHB" offset="0x0143" size="1" mask="0xFF"/>
        <register caption="Rx CRC Result Low Byte Path A" name="RXCRLA" offset="0x014C" size="1" mask="0xFF"/>
        <register caption="Rx CRC Result Low Byte Path B" name="RXCRLB" offset="0x0142" size="1" mask="0xFF"/>
        <register caption="Rx CRC Skip Bit Number Path A" name="RXCSBA" offset="0x014E" size="1" mask="0xFF"/>
        <register caption="Rx CRC Skip Bit Number Path B" name="RXCSBB" offset="0x0144" size="1" mask="0xFF"/>
        <register caption="Receive Data Shift Register Path A" name="RXDSA" offset="0x0153" size="1" mask="0xFF"/>
        <register caption="Receive Data Shift Register Path B" name="RXDSB" offset="0x0149" size="1" mask="0xFF"/>
        <register caption="Rx Telegram Length High Byte Path A" name="RXTLHA" offset="0x014B" size="1" mask="0x0F"/>
        <register caption="Rx Telegram Length High Byte Path B" name="RXTLHB" offset="0x0141" size="1" mask="0x0F"/>
        <register caption="Rx Telegram Length Low Byte Path A" name="RXTLLA" offset="0x014A" size="1" mask="0xFF"/>
        <register caption="Rx Telegram Length Low Byte Path B" name="RXTLLB" offset="0x0140" size="1" mask="0xFF"/>
      </register-group>
      <value-group caption="RX Buffer CRC Length" name="RXBUF_CRC_LENGTH">
        <value caption="CRC 4-bit" name="VAL_0x00" value="0x00"/>
        <value caption="CRC 8-bit" name="VAL_0x01" value="0x01"/>
        <value caption="CRC 16-bit" name="VAL_0x02" value="0x02"/>
      </value-group>
    </module>
    <module caption="" name="RXDSP">
      <register-group caption="" name="RXDSP">
        <register caption="End Of Telegram Conditions Path A" name="EOTCA" offset="0x0054" size="1">
          <bitfield caption="End Of Telegram Path B Fail Enable" mask="0x80" name="EOTBFE"/>
          <bitfield caption="RSSI Range Fail Enable Path A" mask="0x40" name="RRFEA"/>
          <bitfield caption="Telegram Length Reached Enable Path A" mask="0x20" name="TELREA"/>
          <bitfield caption="Time-Out Fail Enable Path A" mask="0x10" name="TMOFEA"/>
          <bitfield caption="Manchester Coding Fail Enable Path A" mask="0x08" name="MANFEA"/>
          <bitfield caption="Symbol Timing Fail Enable Path A" mask="0x04" name="SYTFEA"/>
          <bitfield caption="Modulation Amplitude Fail Enable Path A" mask="0x02" name="AMPFEA"/>
          <bitfield caption="RF Carrier Fail Enable Path A" mask="0x01" name="CARFEA"/>
        </register>
        <register caption="End Of Telegram Conditions Path B" name="EOTCB" offset="0x0056" size="1">
          <bitfield caption="End Of Telegram Path A Fail Enable" mask="0x80" name="EOTAFE"/>
          <bitfield caption="RSSI Range Fail Enable Path B" mask="0x40" name="RRFEB"/>
          <bitfield caption="Telegram Length Reached Enable Path B" mask="0x20" name="TELREB"/>
          <bitfield caption="Time-Out Fail Enable Path B" mask="0x10" name="TMOFEB"/>
          <bitfield caption="Manchester Coding Fail Enable Path B" mask="0x08" name="MANFEB"/>
          <bitfield caption="Symbol Timing Fail Enable Path B" mask="0x04" name="SYTFEB"/>
          <bitfield caption="Modulation Amplitude Fail Enable Path B" mask="0x02" name="AMPFEB"/>
          <bitfield caption="RF Carrier Fail Enable Path B" mask="0x01" name="CARFEB"/>
        </register>
        <register caption="End Of Telegram Status Path A" name="EOTSA" offset="0x0053" size="1">
          <bitfield caption="End Of Telegram Path B Fail" mask="0x80" name="EOTBF"/>
          <bitfield caption="RSSI Range Fail Path A" mask="0x40" name="RRFA"/>
          <bitfield caption="Telegram Length Reached Path A" mask="0x20" name="TELRA"/>
          <bitfield caption="Time-Out Fail Path A" mask="0x10" name="TMOFA"/>
          <bitfield caption="Manchester Coding Fail Path A" mask="0x08" name="MANFA"/>
          <bitfield caption="Symbol Timing Fail Path A" mask="0x04" name="SYTFA"/>
          <bitfield caption="Modulation Amplitude Fail Path A" mask="0x02" name="AMPFA"/>
          <bitfield caption="RF Carrier Fail Path A" mask="0x01" name="CARFA"/>
        </register>
        <register caption="End Of Telegram Status Path B" name="EOTSB" offset="0x0055" size="1">
          <bitfield caption="End Of Telegram Path A Fail" mask="0x80" name="EOTAF"/>
          <bitfield caption="RSSI Range Fail Path B" mask="0x40" name="RRFB"/>
          <bitfield caption="Telegram Length Reached Path B" mask="0x20" name="TELRB"/>
          <bitfield caption="Time-Out Fail Path B" mask="0x10" name="TMOFB"/>
          <bitfield caption="Manchester Coding Fail Path B" mask="0x08" name="MANFB"/>
          <bitfield caption="Symbol Timing Fail Path B" mask="0x04" name="SYTFB"/>
          <bitfield caption="Modulation Amplitude Fail Path B" mask="0x02" name="AMPFB"/>
          <bitfield caption="RF Carrier Fail Path B" mask="0x01" name="CARFB"/>
        </register>
        <register caption="Rx DSP Control Register" name="RDCR" offset="0x0052" size="1">
          <bitfield caption="Rx DSP Enable" mask="0x04" name="RDEN"/>
          <bitfield caption="Divided ADC Clock Enable" mask="0x02" name="ADIVEN"/>
          <bitfield caption="Rx DSP Power Up" mask="0x01" name="RDPU"/>
        </register>
        <register caption="Rx DSP Output Control" name="RDOCR" offset="0x0099" size="1">
          <bitfield caption="Rx DSP Start Bit Is Data Path B" mask="0x40" name="RDSIDB"/>
          <bitfield caption="Rx DSP Start Bit Is Data Path A" mask="0x20" name="RDSIDA"/>
          <bitfield caption="Enable Transparent Raw Data Path B" mask="0x10" name="ETRPB"/>
          <bitfield caption="Enable Transparent Raw Data Path A" mask="0x08" name="ETRPA"/>
          <bitfield caption="Transparent Mode Data Select" mask="0x06" name="TMDS"/>
        </register>
        <register caption="Rx DSP Power Reduction" name="RDPR" offset="0x0024" size="1">
          <bitfield caption="Rx DSP Power Reduction Register Busy Flag" mask="0x80" name="RDPRF"/>
          <bitfield caption="Automatic Rx DSP Power Reduction Flag" mask="0x40" name="ARDPRF"/>
          <bitfield caption="Automatic Power Reduction Path A" mask="0x20" name="APRPTA"/>
          <bitfield caption="Automatic Power Reduction Path B" mask="0x10" name="APRPTB"/>
          <bitfield caption="Power Reduction Temperature Measurement" mask="0x08" name="PRTMP"/>
          <bitfield caption="Power Reduction Digital Channel Filter" mask="0x04" name="PRFLT"/>
          <bitfield caption="Power Reduction Demodulator and Receiving Path A" mask="0x02" name="PRPTA"/>
          <bitfield caption="Power Reduction Demodulator and Receiving Path B" mask="0x01" name="PRPTB"/>
        </register>
        <register caption="Rx DSP Status Interrupt Flag Register" name="RDSIFR" offset="0x002D" size="1">
          <bitfield caption="Wake Check Ok Path B" mask="0x80" name="WCOB"/>
          <bitfield caption="Wake Check Ok Path A" mask="0x40" name="WCOA"/>
          <bitfield caption="Start Of Telegram Path B" mask="0x20" name="SOTB"/>
          <bitfield caption="Start Of Telegram Path A" mask="0x10" name="SOTA"/>
          <bitfield caption="End Of Telegram Path B" mask="0x08" name="EOTB"/>
          <bitfield caption="End Of Telegram Path A" mask="0x04" name="EOTA"/>
          <bitfield caption="New Bit Path B" mask="0x02" name="NBITB"/>
          <bitfield caption="New Bit Path A" mask="0x01" name="NBITA"/>
        </register>
        <register caption="Rx DSP Status Interrupt Mask Register" name="RDSIMR" offset="0x0098" size="1">
          <bitfield caption="Wake Check Ok Path B Interrupt Mask" mask="0x80" name="WCOBM"/>
          <bitfield caption="Wake Check Ok Path A Interrupt Mask" mask="0x40" name="WCOAM"/>
          <bitfield caption="Start Of Telegram Path B Interrupt Mask" mask="0x20" name="SOTBM"/>
          <bitfield caption="Start Of Telegram Path A Interrupt Mask" mask="0x10" name="SOTAM"/>
          <bitfield caption="End Of Telegram Path B Interrupt Mask" mask="0x08" name="EOTBM"/>
          <bitfield caption="End Of Telegram Path A Interrupt Mask" mask="0x04" name="EOTAM"/>
          <bitfield caption="New Bit Path B Interrupt Mask" mask="0x02" name="NBITBM"/>
          <bitfield caption="New Bit Path A Interrupt Mask" mask="0x01" name="NBITAM"/>
        </register>
        <register caption="Start Of Telegram Conditions Path A" name="SOTCA" offset="0x0094" size="1">
          <bitfield caption="Wake Check Ok Path B Ok Enable" mask="0x80" name="WCOBOE"/>
          <bitfield caption="RSSI Range Ok Enable Path A" mask="0x40" name="RROEA"/>
          <bitfield caption="Start of Frame Identifier Enable Path A" mask="0x20" name="SFIDEA"/>
          <bitfield caption="Wake Up Pattern Enable Path A" mask="0x10" name="WUPEA"/>
          <bitfield caption="Manchester Coding Ok Enable Path A" mask="0x08" name="MANOEA"/>
          <bitfield caption="Symbol Timing Ok Enable Path A" mask="0x04" name="SYTOEA"/>
          <bitfield caption="Modulation Amplitude Ok Enable Path A" mask="0x02" name="AMPOEA"/>
          <bitfield caption="RF Carrier Ok Enable Path A" mask="0x01" name="CAROEA"/>
        </register>
        <register caption="Start Of Telegram Conditions Path B" name="SOTCB" offset="0x0093" size="1">
          <bitfield caption="Wake Check Ok Path A Ok Enable" mask="0x80" name="WCOAOE"/>
          <bitfield caption="RSSI Range Ok Enable Path B" mask="0x40" name="RROEB"/>
          <bitfield caption="Start of Frame Identifier Enable Path B" mask="0x20" name="SFIDEB"/>
          <bitfield caption="Wake Up Pattern Enable Path B" mask="0x10" name="WUPEB"/>
          <bitfield caption="Manchester Coding Ok Enable Path B" mask="0x08" name="MANOEB"/>
          <bitfield caption="Symbol Timing Ok Enable Path B" mask="0x04" name="SYTOEB"/>
          <bitfield caption="Modulation Amplitude Ok Enable Path B" mask="0x02" name="AMPOEB"/>
          <bitfield caption="RF Carrier Ok Enable Path B" mask="0x01" name="CAROEB"/>
        </register>
        <register caption="Start Of Telegram Status Path A" name="SOTSA" offset="0x0092" size="1">
          <bitfield caption="Wake Check Ok Path B Ok" mask="0x80" name="WCOBO"/>
          <bitfield caption="RSSI Range Ok Path A" mask="0x40" name="RROA"/>
          <bitfield caption="Start of Frame Identifier Ok Path A" mask="0x20" name="SFIDOA"/>
          <bitfield caption="Wake Up Pattern Ok Path A" mask="0x10" name="WUPOA"/>
          <bitfield caption="Manchester Coding Ok Path A" mask="0x08" name="MANOA"/>
          <bitfield caption="Symbol Timing Ok Path A" mask="0x04" name="SYTOA"/>
          <bitfield caption="Modulation Amplitude Ok Path A" mask="0x02" name="AMPOA"/>
          <bitfield caption="RF Carrier Ok Path A" mask="0x01" name="CAROA"/>
        </register>
        <register caption="Start Of Telegram Status Path B" name="SOTSB" offset="0x0091" size="1">
          <bitfield caption="Wake Check Ok Path A Ok" mask="0x80" name="WCOAO"/>
          <bitfield caption="RSSI Range Ok Path B" mask="0x40" name="RROB"/>
          <bitfield caption="Start of Frame Identifier Ok Path B" mask="0x20" name="SFIDOB"/>
          <bitfield caption="Wake Up Pattern Ok Path B" mask="0x10" name="WUPOB"/>
          <bitfield caption="Manchester Coding Ok Path B" mask="0x08" name="MANOB"/>
          <bitfield caption="Symbol Timing Ok Path B" mask="0x04" name="SYTOB"/>
          <bitfield caption="Modulation Amplitude Ok Path B" mask="0x02" name="AMPOB"/>
          <bitfield caption="RF Carrier Ok Path B" mask="0x01" name="CAROB"/>
        </register>
        <register caption="Temperature" name="TEMP" offset="0x009B" size="2" mask="0xFFFF"/>
        <register caption="Telegram Status Register Path A" name="TESRA" offset="0x0096" size="1">
          <bitfield caption="End of Telegram Location Path A" mask="0x06" name="EOTLA" values="SSM_EOT_LOCATION"/>
          <bitfield caption="Cyclic Redundancy Check Ok Path A" mask="0x01" name="CRCOA"/>
        </register>
        <register caption="Telegram Status Register Path B" name="TESRB" offset="0x0095" size="1">
          <bitfield caption="End of Telegram Location Path B" mask="0x06" name="EOTLB" values="SSM_EOT_LOCATION"/>
          <bitfield caption="Cyclic Redundancy Check Ok Path B" mask="0x01" name="CRCOB"/>
        </register>
      </register-group>
      <value-group caption="SSM EndOfTelegram Location" name="SSM_EOT_LOCATION">
        <value caption="No EOT" name="VAL_0x00" value="0x00"/>
        <value caption="Before WCO" name="VAL_0x01" value="0x01"/>
        <value caption="Between WCO and SOT" name="VAL_0x02" value="0x02"/>
        <value caption="After SOT" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="SFIFO">
      <register-group caption="" name="SFIFO">
        <register caption="Support FIFO Configuration" name="SFC" offset="0x00EE" size="1">
          <bitfield caption="Support FIFO Direct Read Access Operational Mode" mask="0x80" name="SFDRA"/>
          <bitfield caption="Support FIFO Fill Level Configuration" mask="0x1F" name="SFFLC"/>
        </register>
        <register caption="Support FIFO Data" name="SFD" offset="0x00EC" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="Support FIFO Interrupt Mask" name="SFI" offset="0x00ED" size="1">
          <bitfield caption="Support FIFO Error Interrupt Mask" mask="0x02" name="SFERIM"/>
          <bitfield caption="Support FIFO Fill Level Interrupt Mask" mask="0x01" name="SFFLIM"/>
        </register>
        <register caption="Support FIFO Fill Level" name="SFL" offset="0x00E9" size="1">
          <bitfield caption="Support FIFO Clear" mask="0x80" name="SFCLR"/>
          <bitfield caption="Support FIFO Fill Level Status" mask="0x1F" name="SFFLS"/>
        </register>
        <register caption="Support FIFO Read Pointer" name="SFRP" offset="0x00EB" size="1" mask="0x1F"/>
        <register caption="Support FIFO Status" name="SFS" offset="0x00E8" size="1">
          <bitfield caption="Support FIFO Overflow Flag" mask="0x04" name="SFOFL"/>
          <bitfield caption="Support FIFO Underflow Flag" mask="0x02" name="SFUFL"/>
          <bitfield caption="Support FIFO Fill Level Reached Status Flag" mask="0x01" name="SFFLRF"/>
        </register>
        <register caption="Support FIFO Write Pointer" name="SFWP" offset="0x00EA" size="1" mask="0x1F"/>
      </register-group>
    </module>
    <module caption="" name="SPI">
      <register-group caption="" name="SPI">
        <register caption="SPI FIFO Fill Status Register" name="SFFR" offset="0x0166" size="1">
          <bitfield caption="Transmit Buffer Clear" mask="0x80" name="TFC"/>
          <bitfield caption="Transmit Buffer Fill Level" mask="0x70" name="TFL"/>
          <bitfield caption="Rx Buffer Clear" mask="0x08" name="RFC"/>
          <bitfield caption="Receive Buffer Fill Level" mask="0x07" name="RFL"/>
        </register>
        <register caption="SPI FIFO Interrupt Register" name="SFIR" offset="0x0167" size="1">
          <bitfield caption="SPI Transmit Buffer Interrupt Enable" mask="0x80" name="STIE"/>
          <bitfield caption="Transmit Buffer Interrupt Level" mask="0x70" name="TIL"/>
          <bitfield caption="SPI Rx Buffer Interrupt Enable" mask="0x08" name="SRIE"/>
          <bitfield caption="Receive Buffer Interrupt Level" mask="0x07" name="RIL"/>
        </register>
        <register caption="SPI Control Register" name="SPCR" offset="0x004C" size="1">
          <bitfield caption="SPI Interrupt Enable" mask="0x80" name="SPIE"/>
          <bitfield caption="SPI Enable" mask="0x40" name="SPE"/>
          <bitfield caption="Data Order" mask="0x20" name="DORD"/>
          <bitfield caption="Master/Slave Select" mask="0x10" name="MSTR"/>
          <bitfield caption="Clock Polarity" mask="0x08" name="CPOL"/>
          <bitfield caption="Clock Phase" mask="0x04" name="CPHA"/>
          <bitfield caption="SPI Clock Rate Select" mask="0x03" name="SPR" values="COMM_SCK_RATE_3BIT"/>
        </register>
        <register caption="SPI Data Register" name="SPDR" offset="0x004E" size="1" mask="0xFF" ocd-rw=""/>
        <register caption="SPI Status Register" name="SPSR" offset="0x004D" size="1">
          <bitfield caption="SPI Interrupt Flag" mask="0x80" name="SPIF"/>
          <bitfield caption="Tx Buffer Interrupt Flag" mask="0x20" name="TXIF"/>
          <bitfield caption="Rx Buffer Interrupt Flag" mask="0x10" name="RXIF"/>
          <bitfield caption="Double SPI Speed Bit" mask="0x01" name="SPI2X"/>
        </register>
      </register-group>
      <value-group caption="" name="COMM_SCK_RATE_3BIT">
        <value caption="clkio/4" name="VAL_0x00" value="0x00"/>
        <value caption="clkio/16" name="VAL_0x01" value="0x01"/>
        <value caption="clkio/64" name="VAL_0x02" value="0x02"/>
        <value caption="clkio/128" name="VAL_0x03" value="0x03"/>
        <value caption="clkio/2" name="VAL_0x04" value="0x04"/>
        <value caption="clkio/8" name="VAL_0x05" value="0x05"/>
        <value caption="clkio/32" name="VAL_0x06" value="0x06"/>
        <value caption="clkio/64" name="VAL_0x07" value="0x07"/>
      </value-group>
    </module>
    <module caption="" name="SSM">
      <register-group caption="" name="SSM">
        <register caption="End Of Telegram Conditions 1 Path A" name="EOTC1A" offset="0x0124" size="1">
          <bitfield caption="End Of Telegram Path B Fail Enable" mask="0x80" name="EOTBFE1"/>
          <bitfield caption="RSSI Range Fail Enable Path A" mask="0x40" name="RRFEA1"/>
          <bitfield caption="Telegram Length Reached Enable Path A" mask="0x20" name="TELREA1"/>
          <bitfield caption="Time-Out Fail Enable Path A" mask="0x10" name="TMOFEA1"/>
          <bitfield caption="Manchester Coding Fail Enable Path A" mask="0x08" name="MANFEA1"/>
          <bitfield caption="Symbol Timing Fail Enable Path A" mask="0x04" name="SYTFEA1"/>
          <bitfield caption="Modulation Amplitude Fail Enable Path A" mask="0x02" name="AMPFEA1"/>
          <bitfield caption="RF Carrier Fail Enable Path A" mask="0x01" name="CARFEA1"/>
        </register>
        <register caption="End Of Telegram Conditions 1 Path B" name="EOTC1B" offset="0x0127" size="1">
          <bitfield caption="End Of Telegram Path A Fail Enable" mask="0x80" name="EOTAFE1"/>
          <bitfield caption="RSSI Range Fail Enable Path B" mask="0x40" name="RRFEB1"/>
          <bitfield caption="Telegram Length Reached Enable Path B" mask="0x20" name="TELREB1"/>
          <bitfield caption="Time-Out Fail Enable Path B" mask="0x10" name="TMOFEB1"/>
          <bitfield caption="Manchester Coding Fail Enable Path B" mask="0x08" name="MANFEB1"/>
          <bitfield caption="Symbol Timing Fail Enable Path B" mask="0x04" name="SYTFEB1"/>
          <bitfield caption="Modulation Amplitude Fail Enable Path B" mask="0x02" name="AMPFEB1"/>
          <bitfield caption="RF Carrier Fail Enable Path B" mask="0x01" name="CARFEB1"/>
        </register>
        <register caption="End Of Telegram Conditions 2 Path A" name="EOTC2A" offset="0x0125" size="1">
          <bitfield caption="End Of Telegram Path B Fail Enable" mask="0x80" name="EOTBFE2"/>
          <bitfield caption="RSSI Range Fail Enable Path A" mask="0x40" name="RRFEA2"/>
          <bitfield caption="Telegram Length Reached Enable Path A" mask="0x20" name="TELREA2"/>
          <bitfield caption="Time-Out Fail Enable Path A" mask="0x10" name="TMOFEA2"/>
          <bitfield caption="Manchester Coding Fail Enable Path A" mask="0x08" name="MANFEA2"/>
          <bitfield caption="Symbol Timing Fail Enable Path A" mask="0x04" name="SYTFEA2"/>
          <bitfield caption="Modulation Amplitude Fail Enable Path A" mask="0x02" name="AMPFEA2"/>
          <bitfield caption="RF Carrier Fail Enable Path A" mask="0x01" name="CARFEA2"/>
        </register>
        <register caption="End Of Telegram Conditions 2 Path B" name="EOTC2B" offset="0x0128" size="1">
          <bitfield caption="End Of Telegram Path A Fail Enable" mask="0x80" name="EOTAFE2"/>
          <bitfield caption="RSSI Range Fail Enable Path B" mask="0x40" name="RRFEB2"/>
          <bitfield caption="Telegram Length Reached Enable Path B" mask="0x20" name="TELREB2"/>
          <bitfield caption="Time-Out Fail Enable Path B" mask="0x10" name="TMOFEB2"/>
          <bitfield caption="Manchester Coding Fail Enable Path B" mask="0x08" name="MANFEB2"/>
          <bitfield caption="Symbol Timing Fail Enable Path B" mask="0x04" name="SYTFEB2"/>
          <bitfield caption="Modulation Amplitude Fail Enable Path B" mask="0x02" name="AMPFEB2"/>
          <bitfield caption="RF Carrier Fail Enable Path B" mask="0x01" name="CARFEB2"/>
        </register>
        <register caption="End Of Telegram Conditions 3 Path A" name="EOTC3A" offset="0x0126" size="1">
          <bitfield caption="End Of Telegram Path B Fail Enable" mask="0x80" name="EOTBFE3"/>
          <bitfield caption="RSSI Range Fail Enable Path A" mask="0x40" name="RRFEA3"/>
          <bitfield caption="Telegram Length Reached Enable Path A" mask="0x20" name="TELREA3"/>
          <bitfield caption="Time-Out Fail Enable Path A" mask="0x10" name="TMOFEA3"/>
          <bitfield caption="Manchester Coding Fail Enable Path A" mask="0x08" name="MANFEA3"/>
          <bitfield caption="Symbol Timing Fail Enable Path A" mask="0x04" name="SYTFEA3"/>
          <bitfield caption="Modulation Amplitude Fail Enable Path A" mask="0x02" name="AMPFEA3"/>
          <bitfield caption="RF Carrier Fail Enable Path A" mask="0x01" name="CARFEA3"/>
        </register>
        <register caption="End Of Telegram Conditions 3 Path B" name="EOTC3B" offset="0x0129" size="1">
          <bitfield caption="End Of Telegram Path A Fail Enable" mask="0x80" name="EOTAFE3"/>
          <bitfield caption="RSSI Range Fail Enable Path B" mask="0x40" name="RRFEB3"/>
          <bitfield caption="Telegram Length Reached Enable Path B" mask="0x20" name="TELREB3"/>
          <bitfield caption="Time-Out Fail Enable Path B" mask="0x10" name="TMOFEB3"/>
          <bitfield caption="Manchester Coding Fail Enable Path B" mask="0x08" name="MANFEB3"/>
          <bitfield caption="Symbol Timing Fail Enable Path B" mask="0x04" name="SYTFEB3"/>
          <bitfield caption="Modulation Amplitude Fail Enable Path B" mask="0x02" name="AMPFEB3"/>
          <bitfield caption="RF Carrier Fail Enable Path B" mask="0x01" name="CARFEB3"/>
        </register>
        <register caption="Get Telegram Control Register" name="GTCR" offset="0x00FD" size="1">
          <bitfield caption="Intermittent WUP Mode Path B" mask="0x80" name="IWUPB"/>
          <bitfield caption="Demodulator Automatic Restart Path B" mask="0x40" name="DARB"/>
          <bitfield caption="Gap Mode Path B" mask="0x20" name="GAPMB"/>
          <bitfield caption="Rx Telegram End Handling Path B" mask="0x10" name="RXTEHB"/>
          <bitfield caption="Intermittent WUP Mode Path A" mask="0x08" name="IWUPA"/>
          <bitfield caption="Demodulator Automatic Restart Path A" mask="0x04" name="DARA"/>
          <bitfield caption="Gap Mode Path A" mask="0x02" name="GAPMA"/>
          <bitfield caption="Rx Telegram End Handling Path A" mask="0x01" name="RXTEHA"/>
        </register>
        <register caption="Master State Machine Control Register 1" name="MSMCR1" offset="0x00F9" size="1">
          <bitfield caption="Master State Machine Sub-State Machine Select 1" mask="0xF0" name="MSMSM1" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine Sub-State Machine Select 0" mask="0x0F" name="MSMSM0" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 2" name="MSMCR2" offset="0x00FA" size="1">
          <bitfield caption="Master State Machine Sub-State Machine Select 3" mask="0xF0" name="MSMSM3" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine Sub-State Machine Select 2" mask="0x0F" name="MSMSM2" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 3" name="MSMCR3" offset="0x00FB" size="1">
          <bitfield caption="Master State Machine Sub-State Machine Select 5" mask="0xF0" name="MSMSM5" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine Sub-State Machine Select 4" mask="0x0F" name="MSMSM4" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 4" name="MSMCR4" offset="0x00FC" size="1">
          <bitfield caption="Master State Machine Sub-State Machine Select 7" mask="0xF0" name="MSMSM7" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine Sub-State Machine Select 6" mask="0x0F" name="MSMSM6" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine State Register" name="MSMSTR" offset="0x00F6" size="1">
          <bitfield caption="Sequencer State Machine Master State" mask="0x1F" name="SSMMST"/>
        </register>
        <register caption="Start Of Telegram Conditions 1 Path A" name="SOTC1A" offset="0x0120" size="1">
          <bitfield caption="Wake Check Ok Path B Ok Enable" mask="0x80" name="WCOBOE1"/>
          <bitfield caption="RSSI Range Ok Enable Path A" mask="0x40" name="RROEA1"/>
          <bitfield caption="Start of Frame Identifier Enable Path A" mask="0x20" name="SFIDEA1"/>
          <bitfield caption="Wake Up Pattern Enable Path A" mask="0x10" name="WUPEA1"/>
          <bitfield caption="Manchester Coding Ok Enable Path A" mask="0x08" name="MANOEA1"/>
          <bitfield caption="Symbol Timing Ok Enable Path A" mask="0x04" name="SYTOEA1"/>
          <bitfield caption="Modulation Amplitude Ok Enable Path A" mask="0x02" name="AMPOEA1"/>
          <bitfield caption="RF Carrier Ok Enable Path A" mask="0x01" name="CAROEA1"/>
        </register>
        <register caption="Start Of Telegram Conditions 1 Path B" name="SOTC1B" offset="0x0122" size="1">
          <bitfield caption="Wake Check Ok Path A Ok Enable" mask="0x80" name="WCOAOE1"/>
          <bitfield caption="RSSI Range Ok Enable Path B" mask="0x40" name="RROEB1"/>
          <bitfield caption="Start of Frame Identifier Enable Path B" mask="0x20" name="SFIDEB1"/>
          <bitfield caption="Wake Up Pattern Enable Path B" mask="0x10" name="WUPEB1"/>
          <bitfield caption="Manchester Coding Ok Enable Path B" mask="0x08" name="MANOEB1"/>
          <bitfield caption="Symbol Timing Ok Enable Path B" mask="0x04" name="SYTOEB1"/>
          <bitfield caption="Modulation Amplitude Ok Enable Path B" mask="0x02" name="AMPOEB1"/>
          <bitfield caption="RF Carrier Ok Enable Path B" mask="0x01" name="CAROEB1"/>
        </register>
        <register caption="Start Of Telegram Conditions 2 Path A" name="SOTC2A" offset="0x0121" size="1">
          <bitfield caption="Wake Check Ok Path B Ok Enable" mask="0x80" name="WCOBOE2"/>
          <bitfield caption="RSSI Range Ok Enable Path A" mask="0x40" name="RROEA2"/>
          <bitfield caption="Start of Frame Identifier Enable Path A" mask="0x20" name="SFIDEA2"/>
          <bitfield caption="Wake Up Pattern Enable Path A" mask="0x10" name="WUPEA2"/>
          <bitfield caption="Manchester Coding Ok Enable Path A" mask="0x08" name="MANOEA2"/>
          <bitfield caption="Symbol Timing Ok Enable Path A" mask="0x04" name="SYTOEA2"/>
          <bitfield caption="Modulation Amplitude Ok Enable Path A" mask="0x02" name="AMPOEA2"/>
          <bitfield caption="RF Carrier Ok Enable Path A" mask="0x01" name="CAROEA2"/>
        </register>
        <register caption="Start Of Telegram Conditions 2 Path B" name="SOTC2B" offset="0x0123" size="1">
          <bitfield caption="Wake Check Ok Path A Ok Enable" mask="0x80" name="WCOAOE2"/>
          <bitfield caption="RSSI Range Ok Enable Path B" mask="0x40" name="RROEB2"/>
          <bitfield caption="Start of Frame Identifier Enable Path B" mask="0x20" name="SFIDEB2"/>
          <bitfield caption="Wake Up Pattern Enable Path B" mask="0x10" name="WUPEB2"/>
          <bitfield caption="Manchester Coding Ok Enable Path B" mask="0x08" name="MANOEB2"/>
          <bitfield caption="Symbol Timing Ok Enable Path B" mask="0x04" name="SYTOEB2"/>
          <bitfield caption="Modulation Amplitude Ok Enable Path B" mask="0x02" name="AMPOEB2"/>
          <bitfield caption="RF Carrier Ok Enable Path B" mask="0x01" name="CAROEB2"/>
        </register>
        <register caption="Start Of Telegram Time Out Path A" name="SOTTOA" offset="0x012C" size="1" mask="0xFF"/>
        <register caption="Start Of Telegram Time Out Path B" name="SOTTOB" offset="0x012D" size="1" mask="0xFF"/>
        <register caption="Sequencer State Machine Control Register" name="SSMCR" offset="0x00EF" size="1">
          <bitfield caption="SSM Enable Raw Transparent Path B" mask="0x80" name="SETRPB"/>
          <bitfield caption="SSM Enable Transparent Path A" mask="0x40" name="SETRPA"/>
          <bitfield caption="SSM Tx ASK-Shaping Enable" mask="0x20" name="SSMTAE"/>
          <bitfield caption="SSM PA Voltage Enable" mask="0x10" name="SSMPVE"/>
          <bitfield caption="SSM Tx Preemphasis Enable" mask="0x08" name="SSMTPE"/>
          <bitfield caption="SSM Tx Gauss Shaping Enable" mask="0x04" name="SSMTGE"/>
          <bitfield caption="SSM Temperature Measurement" mask="0x02" name="SSMTM"/>
          <bitfield caption="SSM Tx" mask="0x01" name="SSMTX"/>
        </register>
        <register caption="Sequencer State Machine Filter Bandwidth Register" name="SSMFBR" offset="0x00F1" size="1">
          <bitfield caption="SSM PLL Lock Delay Time" mask="0x20" name="SSMPLDT"/>
          <bitfield caption="SSM Half Antenna Damping Delay Time" mask="0x10" name="SSMHADT"/>
          <bitfield caption="SSM Double Filter Delay Time" mask="0x08" name="SSMDFDT"/>
          <bitfield caption="SSM Filter Delay" mask="0x07" name="SSMFID" values="SSM_FILTER_DELAY"/>
        </register>
        <register caption="Sequencer State Machine Flow Control Register" name="SSMFCR" offset="0x012E" size="1">
          <bitfield caption="SSM Continuous Start Telegram End Handling" mask="0x08" name="SSMCEH"/>
          <bitfield caption="SSM Single Start Telegram End Handling" mask="0x04" name="SSMSEH"/>
          <bitfield caption="SSM ID Scan Fail" mask="0x02" name="SSMIDSF"/>
          <bitfield caption="SSM ID Scan OK" mask="0x01" name="SSMIDSO"/>
        </register>
        <register caption="Sequencer State Machine Interrupt Flag Register" name="SSMIFR" offset="0x00F4" size="1">
          <bitfield caption="SSM Interrupt Flag" mask="0x01" name="SSMIF"/>
        </register>
        <register caption="Sequencer State Machine Interrupt Mask Register" name="SSMIMR" offset="0x00F5" size="1">
          <bitfield caption="SSM Interrupt Mask" mask="0x01" name="SSMIM"/>
        </register>
        <register caption="Sequencer State Machine Rx Control Register" name="SSMRCR" offset="0x00F0" size="1">
          <bitfield caption="SSM Transparent Output Enable" mask="0x80" name="SSMTMOE"/>
          <bitfield caption="SSM ID Check Enable" mask="0x40" name="SSMIDSE"/>
          <bitfield caption="SSM IF Amplifier Enable" mask="0x20" name="SSMIFA"/>
          <bitfield caption="SSM Path Valid After SOT" mask="0x10" name="SSMPVS"/>
          <bitfield caption="SSM High Sensitivity Enable" mask="0x08" name="SSMHIS"/>
          <bitfield caption="SSM Antenna Damping Disable" mask="0x04" name="SSMAD"/>
          <bitfield caption="SSM Path B" mask="0x02" name="SSMPB"/>
          <bitfield caption="SSM Path A" mask="0x01" name="SSMPA"/>
        </register>
        <register caption="Sequencer State Machine Run Register" name="SSMRR" offset="0x00F2" size="1">
          <bitfield caption="SSM Stop" mask="0x02" name="SSMST"/>
          <bitfield caption="SSM Run" mask="0x01" name="SSMR"/>
        </register>
        <register caption="Sequencer State Machine Status Register" name="SSMSR" offset="0x00F3" size="1">
          <bitfield caption="SSM Error" mask="0x80" name="SSMERR"/>
          <bitfield caption="SSM Error State Machine" mask="0x0F" name="SSMESM"/>
        </register>
        <register caption="Sequencer State Machine State Register" name="SSMSTR" offset="0x00F7" size="1">
          <bitfield caption="SSM State A" mask="0x3F" name="SSMSTA"/>
        </register>
        <register caption="Sequencer State Machine Extended State Register" name="SSMXSR" offset="0x00F8" size="1">
          <bitfield caption="SSM State B" mask="0x3F" name="SSMSTB"/>
        </register>
        <register caption="Wake Check Ok Time-Out Path A" name="WCOTOA" offset="0x012A" size="1" mask="0xFF"/>
        <register caption="Wake Check Ok Time-Out Path B" name="WCOTOB" offset="0x012B" size="1" mask="0xFF"/>
      </register-group>
      <value-group caption="" name="SSM_SUB_STATE_MACHINE">
        <value caption="None/Stop" name="VAL_0x00" value="0x00"/>
        <value caption="PLL en" name="VAL_0x01" value="0x01"/>
        <value caption="PLL lock" name="VAL_0x02" value="0x02"/>
        <value caption="RX DSP enable" name="VAL_0x03" value="0x03"/>
        <value caption="RX DSP disable" name="VAL_0x04" value="0x04"/>
        <value caption="TX DSP enable" name="VAL_0x05" value="0x05"/>
        <value caption="TX DSP disable" name="VAL_0x06" value="0x06"/>
        <value caption="RX to TX" name="VAL_0x07" value="0x07"/>
        <value caption="TX to RX" name="VAL_0x08" value="0x08"/>
        <value caption="Get telegram" name="VAL_0x09" value="0x09"/>
        <value caption="Send telegram" name="VAL_0x0A" value="0x0A"/>
        <value caption="Shut down" name="VAL_0x0B" value="0x0B"/>
        <value caption="VCO Tuning" name="VAL_0x0C" value="0x0C"/>
      </value-group>
      <value-group caption="" name="SSM_FILTER_DELAY">
        <value caption="380us (25kHz)" name="VAL_0x00" value="0x00"/>
        <value caption="202us (50kHz)" name="VAL_0x01" value="0x01"/>
        <value caption="135us (80kHz)" name="VAL_0x02" value="0x02"/>
        <value caption=" 75us (165kHz)" name="VAL_0x03" value="0x03"/>
        <value caption=" 58.5us (235kHz)" name="VAL_0x04" value="0x04"/>
        <value caption=" 45us (360kHz)" name="VAL_0x05" value="0x05"/>
      </value-group>
    </module>
    <module caption="" name="SUP">
      <register-group caption="" name="SUP">
        <register caption="DCDC Converter Control 1" name="DCC1" offset="0x00DD" size="1">
          <bitfield caption="DCDC Converter Clock Divider" mask="0x30" name="DCCDIV" values="DCDC_CLOCK_DIVIDER"/>
          <bitfield caption="DCDC Converter High Side Switch" mask="0x02" name="DCHSSW"/>
          <bitfield caption="DCDC Converter Enable" mask="0x01" name="DCEN"/>
        </register>
        <register caption="DCDC Converter Control 2" name="DCC2" offset="0x00DE" size="1">
          <bitfield caption="DCDC Converter Driver Strength" mask="0x30" name="DCDRV"/>
          <bitfield caption="DCDC Converter Current Limit" mask="0x0C" name="DCCLIM"/>
          <bitfield caption="DCDC Converter Output Voltage" mask="0x03" name="DCVOUT" values="DCDC_OUTPUT_VOLTAGE"/>
        </register>
        <register caption="DCDC Converter Calibration 1" name="DCCAL1" offset="0x00D6" size="1">
          <bitfield caption="Zero Crossing Calibration" mask="0xF0" name="ZCCAL"/>
          <bitfield caption="Current Limit Calibration" mask="0x0F" name="CCAL"/>
        </register>
        <register caption="DCDC Converter Calibration 2" name="DCCAL2" offset="0x00D7" size="1">
          <bitfield caption="Offset Calibration" mask="0xF0" name="OFCAL"/>
          <bitfield caption="Dead Time Calibration" mask="0x0F" name="DTCAL"/>
        </register>
        <register caption="DCDC Converter Calibration 3" name="DCCAL3" offset="0x00D8" size="1">
          <bitfield caption="Ramp Calibration" mask="0x03" name="SAWCAL"/>
        </register>
        <register caption="DCDC Converter Test Mode" name="DCTST" offset="0x00D9" size="1">
          <bitfield caption="DCDC Converter Test Mode" mask="0x1F" name="DCTST"/>
        </register>
        <register caption="Resistor Capacitor 4 Bit Tuning" name="RCTUNE4" offset="0x00DC" size="1">
          <bitfield caption="4 Bit Resistor Tuning" mask="0xF0" name="RTUNE4"/>
          <bitfield caption="4 Bit Capacitor Tuning" mask="0x0F" name="CTUNE4"/>
        </register>
        <register caption="Supply Control Register" name="SUPCR" offset="0x00D1" size="1">
          <bitfield caption="AVCC Double Internal Current" mask="0x40" name="AVDIC"/>
          <bitfield caption="AVCC Enable" mask="0x20" name="AVEN"/>
          <bitfield caption="Power Amplifier Regulator Double Internal Current" mask="0x10" name="PVDIC"/>
          <bitfield caption="Power Amplifier Voltage 2.2V" mask="0x08" name="PV22"/>
          <bitfield caption="Power Amplifier Voltage Supply Enable" mask="0x04" name="PVEN"/>
          <bitfield caption="AVCC Low Interrupt Mask" mask="0x02" name="AVCCLM"/>
          <bitfield caption="AVCC Reset Interrupt Mask" mask="0x01" name="AVCCRM"/>
        </register>
        <register caption="Supply Flag Register" name="SUPFR" offset="0x00D0" size="1">
          <bitfield caption="DCDC Converter Error Flag" mask="0x08" name="DCERF"/>
          <bitfield caption="DCDC Converter Ready Flag" mask="0x04" name="DCRDYF"/>
          <bitfield caption="AVCC Low Flag" mask="0x02" name="AVCCLF"/>
          <bitfield caption="AVCC Reset Flag" mask="0x01" name="AVCCRF"/>
        </register>
      </register-group>
      <value-group caption="" name="DCDC_CLOCK_DIVIDER">
        <value caption="16 (375kHz)" name="VAL_0x00" value="0x00"/>
        <value caption="12 (500kHz)" name="VAL_0x01" value="0x01"/>
        <value caption=" 8 (750kHz)" name="VAL_0x02" value="0x02"/>
        <value caption=" 6 (1MHz)" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="DCDC_OUTPUT_VOLTAGE">
        <value caption="2.2V" name="VAL_0x00" value="0x00"/>
        <value caption="2.5V" name="VAL_0x01" value="0x01"/>
        <value caption="2.8V" name="VAL_0x02" value="0x02"/>
        <value caption="3.3V" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER0_WDT">
      <register-group caption="" name="TIMER0_WDT">
        <register caption="Timer0 Control Register" name="T0CR" offset="0x0030" size="1">
          <bitfield caption="Timer0 Prescaler Reset" mask="0x10" name="T0PR"/>
          <bitfield caption="Timer0 Interrupt Enable" mask="0x08" name="T0IE"/>
          <bitfield caption="Timer0 Prescaler Select" mask="0x07" name="T0PS"/>
        </register>
        <register caption="Timer0 Interrupt Flag Register" name="T0IFR" offset="0x004F" size="1">
          <bitfield caption="Timer0 Flag" mask="0x01" name="T0F"/>
        </register>
        <register caption="Watchdog Timer0 Control Register" name="WDTCR" offset="0x006E" size="1">
          <bitfield caption="Watchdog Change Enable" mask="0x10" name="WDCE"/>
          <bitfield caption="Watchdog Enable" mask="0x08" name="WDE"/>
          <bitfield caption="Watchdog Prescaler Select" mask="0x07" name="WDPS"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="TIMER1">
      <register-group caption="" name="TIMER1">
        <register caption="Timer1 Counter Register" name="T1CNT" offset="0x006F" size="1" mask="0xFF"/>
        <register caption="Timer1 Compare Register" name="T1COR" offset="0x0070" size="1" mask="0xFF"/>
        <register caption="Timer1 Control Register" name="T1CR" offset="0x0031" size="1">
          <bitfield caption="Timer1 Enable" mask="0x80" name="T1ENA"/>
          <bitfield caption="Timer1 Toggle with Start" mask="0x40" name="T1TOS"/>
          <bitfield caption="Timer1 Reset" mask="0x20" name="T1RES"/>
          <bitfield caption="Timer1 Toggle Output Preset" mask="0x10" name="T1TOP"/>
          <bitfield caption="Timer1 Compare Reset Mask" mask="0x04" name="T1CRM"/>
          <bitfield caption="Timer1 Compare Toggle Mask" mask="0x02" name="T1CTM"/>
          <bitfield caption="Timer1 Overflow Toggle Mask" mask="0x01" name="T1OTM"/>
        </register>
        <register caption="Timer1 Interrupt Flag Register" name="T1IFR" offset="0x0035" size="1">
          <bitfield caption="Timer1 Compare Flag" mask="0x02" name="T1COF"/>
          <bitfield caption="Timer1 Overflow Flag" mask="0x01" name="T1OFF"/>
        </register>
        <register caption="Timer1 Interrupt Mask Register" name="T1IMR" offset="0x0072" size="1">
          <bitfield caption="Timer1 Compare Interrupt Mask" mask="0x02" name="T1CIM"/>
          <bitfield caption="Timer1 Overflow Interrupt Mask" mask="0x01" name="T1OIM"/>
        </register>
        <register caption="Timer1 Mode Register" name="T1MR" offset="0x0071" size="1">
          <bitfield caption="Timer1 Duty Cycle" mask="0xC0" name="T1DC"/>
          <bitfield caption="Timer1 Prescaler Select" mask="0x3C" name="T1PS"/>
          <bitfield caption="Timer1 Clock Select" mask="0x03" name="T1CS" values="TIM1_CLOCK_SELECT"/>
        </register>
      </register-group>
      <value-group caption="Timer1 Clock Select" name="TIM1_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_frc" name="VAL_0x01" value="0x01"/>
        <value caption="clk_T" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto4" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER2">
      <register-group caption="" name="TIMER2">
        <register caption="Timer2 Counter Register" name="T2CNT" offset="0x0073" size="1" mask="0xFF"/>
        <register caption="Timer2 Compare Register" name="T2COR" offset="0x0074" size="1" mask="0xFF"/>
        <register caption="Timer2 Control Register" name="T2CR" offset="0x0032" size="1">
          <bitfield caption="Timer2 Enable" mask="0x80" name="T2ENA"/>
          <bitfield caption="Timer2 Toggle with Start" mask="0x40" name="T2TOS"/>
          <bitfield caption="Timer2 Reset" mask="0x20" name="T2RES"/>
          <bitfield caption="Timer2 Toggle Output Preset" mask="0x10" name="T2TOP"/>
          <bitfield caption="Timer2 Compare Reset Mask" mask="0x04" name="T2CRM"/>
          <bitfield caption="Timer2 Compare Toggle Mask" mask="0x02" name="T2CTM"/>
          <bitfield caption="Timer2 Overflow Toggle Mask" mask="0x01" name="T2OTM"/>
        </register>
        <register caption="Timer2 Interrupt Flag Register" name="T2IFR" offset="0x0036" size="1">
          <bitfield caption="Timer2 Compare Flag" mask="0x02" name="T2COF"/>
          <bitfield caption="Timer2 Overflow Flag" mask="0x01" name="T2OFF"/>
        </register>
        <register caption="Timer2 Interrupt Mask Register" name="T2IMR" offset="0x0076" size="1">
          <bitfield caption="Timer2 Compare Interrupt Mask" mask="0x02" name="T2CIM"/>
          <bitfield caption="Timer2 Overflow Interrupt Mask" mask="0x01" name="T2OIM"/>
        </register>
        <register caption="Timer2 Mode Register" name="T2MR" offset="0x0075" size="1">
          <bitfield caption="Timer2 Duty Cycle" mask="0xC0" name="T2DC"/>
          <bitfield caption="Timer2 Prescaler Select" mask="0x3C" name="T2PS"/>
          <bitfield caption="Timer2 Clock Select" mask="0x03" name="T2CS" values="TIM2_CLOCK_SELECT"/>
        </register>
      </register-group>
      <value-group caption="Timer2 Clock Select" name="TIM2_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_vdiv" name="VAL_0x01" value="0x01"/>
        <value caption="clk_T" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto4" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER3">
      <register-group caption="" name="TIMER3">
        <register caption="Timer3 Counter" name="T3CNT" offset="0x0077" size="2" mask="0xFFFF"/>
        <register caption="Timer3 Compare" name="T3COR" offset="0x0079" size="2" mask="0xFFFF"/>
        <register caption="Timer3 Control Register" name="T3CR" offset="0x0033" size="1">
          <bitfield caption="Timer3 Enable" mask="0x80" name="T3ENA"/>
          <bitfield caption="Timer3 Toggle with Start" mask="0x40" name="T3TOS"/>
          <bitfield caption="Timer3 Reset" mask="0x20" name="T3RES"/>
          <bitfield caption="Timer3 Toggle Output Preset" mask="0x10" name="T3TOP"/>
          <bitfield caption="Timer3 Capture Reset Mask" mask="0x08" name="T3CPRM"/>
          <bitfield caption="Timer3 Compare Reset Mask" mask="0x04" name="T3CRM"/>
          <bitfield caption="Timer3 Compare Toggle Mask" mask="0x02" name="T3CTM"/>
          <bitfield caption="Timer3 Overflow Toggle Mask" mask="0x01" name="T3OTM"/>
        </register>
        <register caption="Timer3 Input Capture" name="T3ICR" offset="0x007B" size="2" mask="0xFFFF"/>
        <register caption="Timer3 Interrupt Flag Register" name="T3IFR" offset="0x0037" size="1">
          <bitfield caption="Timer3 Input Capture Flag" mask="0x04" name="T3ICF"/>
          <bitfield caption="Timer3 Compare Flag" mask="0x02" name="T3COF"/>
          <bitfield caption="Timer3 Overflow Flag" mask="0x01" name="T3OFF"/>
        </register>
        <register caption="Timer3 Interrupt Mask Register" name="T3IMR" offset="0x007F" size="1">
          <bitfield caption="Timer3 Capture Interrupt Mask" mask="0x04" name="T3CPIM"/>
          <bitfield caption="Timer3 Compare Interrupt Mask" mask="0x02" name="T3CIM"/>
          <bitfield caption="Timer3 Overflow Interrupt Mask" mask="0x01" name="T3OIM"/>
        </register>
        <register caption="Timer3 Mode Register A" name="T3MRA" offset="0x007D" size="1">
          <bitfield caption="Timer3 Prescaler Select" mask="0x1C" name="T3PS"/>
          <bitfield caption="Timer3 Clock Select" mask="0x03" name="T3CS" values="TIM3_CLOCK_SELECT"/>
        </register>
        <register caption="Timer3 Mode Register B" name="T3MRB" offset="0x007E" size="1">
          <bitfield caption="Timer3 Input Capture Select" mask="0xE0" name="T3ICS" values="TIM3_CAPTURE_SELECT"/>
          <bitfield caption="Timer3 Capture Edge Select" mask="0x18" name="T3CE" values="TIM3_CAPTURE_EDGE_SELECT"/>
          <bitfield caption="Timer3 Input Capture Noise Canceller" mask="0x04" name="T3CNC"/>
          <bitfield caption="Timer3 Software Capture Enable" mask="0x02" name="T3SCE"/>
        </register>
      </register-group>
      <value-group caption="Timer3 Clock Select" name="TIM3_CLOCK_SELECT">
        <value caption="clk_frc" name="VAL_0x00" value="0x00"/>
        <value caption="clk_T" name="VAL_0x01" value="0x01"/>
        <value caption="clk_xto4" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto2" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="Timer3 Capture Select" name="TIM3_CAPTURE_SELECT">
        <value caption="clk_T2" name="VAL_0x00" value="0x00"/>
        <value caption="trpa" name="VAL_0x01" value="0x01"/>
        <value caption="trpb" name="VAL_0x02" value="0x02"/>
        <value caption="ticp" name="VAL_0x03" value="0x03"/>
        <value caption="clk_src" name="VAL_0x04" value="0x04"/>
      </value-group>
      <value-group caption="Timer3 Capture Edge Select" name="TIM3_CAPTURE_EDGE_SELECT">
        <value caption="disable" name="VAL_0x00" value="0x00"/>
        <value caption="rising edge" name="VAL_0x01" value="0x01"/>
        <value caption="falling edge" name="VAL_0x02" value="0x02"/>
        <value caption="both edges" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER4">
      <register-group caption="" name="TIMER4">
        <register caption="Timer4 Counter" name="T4CNT" offset="0x0080" size="2" mask="0xFFFF"/>
        <register caption="Timer4 Compare" name="T4COR" offset="0x0082" size="2" mask="0xFFFF"/>
        <register caption="Timer4 Control Register" name="T4CR" offset="0x0034" size="1">
          <bitfield caption="Timer4 Enable" mask="0x80" name="T4ENA"/>
          <bitfield caption="Timer4 Toggle with Start" mask="0x40" name="T4TOS"/>
          <bitfield caption="Timer4 Reset" mask="0x20" name="T4RES"/>
          <bitfield caption="Timer4 Toggle Output Preset" mask="0x10" name="T4TOP"/>
          <bitfield caption="Timer4 Capture Reset Mask" mask="0x08" name="T4CPRM"/>
          <bitfield caption="Timer4 Compare Reset Mask" mask="0x04" name="T4CRM"/>
          <bitfield caption="Timer4 Compare Toggle Mask" mask="0x02" name="T4CTM"/>
          <bitfield caption="Timer4 Overflow Toggle Mask" mask="0x01" name="T4OTM"/>
        </register>
        <register caption="Timer4 Input Capture" name="T4ICR" offset="0x0084" size="2" mask="0xFFFF"/>
        <register caption="Timer4 Interrupt Flag Register" name="T4IFR" offset="0x0038" size="1">
          <bitfield caption="Timer4 Input Capture Flag" mask="0x04" name="T4ICF"/>
          <bitfield caption="Timer4 Compare Flag" mask="0x02" name="T4COF"/>
          <bitfield caption="Timer4 Overflow Flag" mask="0x01" name="T4OFF"/>
        </register>
        <register caption="Timer4 Interrupt Mask Register" name="T4IMR" offset="0x0088" size="1">
          <bitfield caption="Timer4 Capture Interrupt Mask" mask="0x04" name="T4CPIM"/>
          <bitfield caption="Timer4 Compare Interrupt Mask" mask="0x02" name="T4CIM"/>
          <bitfield caption="Timer4 Overflow Interrupt Mask" mask="0x01" name="T4OIM"/>
        </register>
        <register caption="Timer4 Mode Register A" name="T4MRA" offset="0x0086" size="1">
          <bitfield caption="Timer4 Prescaler Select" mask="0x1C" name="T4PS"/>
          <bitfield caption="Timer4 Clock Select" mask="0x03" name="T4CS" values="TIM4_CLOCK_SELECT"/>
        </register>
        <register caption="Timer4 Mode Register B" name="T4MRB" offset="0x0087" size="1">
          <bitfield caption="Timer4 Input Capture Select" mask="0xE0" name="T4ICS" values="TIM4_CAPTURE_SELECT"/>
          <bitfield caption="Timer4 Capture Edge Select" mask="0x18" name="T4CE" values="TIM4_CAPTURE_EDGE_SELECT"/>
          <bitfield caption="Timer4 Input Capture Noise Canceller" mask="0x04" name="T4CNC"/>
          <bitfield caption="Timer4 Software Capture Enable" mask="0x02" name="T4SCE"/>
        </register>
      </register-group>
      <value-group caption="Timer4 Clock Select" name="TIM4_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_T" name="VAL_0x01" value="0x01"/>
        <value caption="clk_xto6" name="VAL_0x02" value="0x02"/>
        <value caption="clk_frc" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="Timer4 Capture Select" name="TIM4_CAPTURE_SELECT">
        <value caption="clk_T2" name="VAL_0x00" value="0x00"/>
        <value caption="trpa" name="VAL_0x01" value="0x01"/>
        <value caption="trpb" name="VAL_0x02" value="0x02"/>
        <value caption="ticp" name="VAL_0x03" value="0x03"/>
        <value caption="clk_src" name="VAL_0x04" value="0x04"/>
      </value-group>
      <value-group caption="Timer4 Capture Edge Select" name="TIM4_CAPTURE_EDGE_SELECT">
        <value caption="disable" name="VAL_0x00" value="0x00"/>
        <value caption="rising edge" name="VAL_0x01" value="0x01"/>
        <value caption="falling edge" name="VAL_0x02" value="0x02"/>
        <value caption="both edges" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER5">
      <register-group caption="" name="TIMER5">
        <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x0090" size="1">
          <bitfield caption="Timer Synchronization Mode" mask="0x80" name="TSM"/>
          <bitfield caption="Prescaler Reset" mask="0x01" name="PSR10"/>
        </register>
        <register caption="Timer5 Configuration and Control Register" name="T5CCR" offset="0x008C" size="1">
          <bitfield caption="Timer5 Clear Counter on Compare Match" mask="0x08" name="T5CTC"/>
          <bitfield caption="Timer5 Clock Select" mask="0x07" name="T5CS" values="CLK_SEL_3BIT"/>
        </register>
        <register caption="Timer5 Counter" name="T5CNT" offset="0x008D" size="2" mask="0xFFFF"/>
        <register caption="Timer5 Interrupt Flag Register" name="T5IFR" offset="0x0039" size="1">
          <bitfield caption="Timer5 Compare Flag" mask="0x02" name="T5COF"/>
          <bitfield caption="Timer5 Overflow Flag" mask="0x01" name="T5OFF"/>
        </register>
        <register caption="Timer5 Interrupt Mask Register" name="T5IMR" offset="0x008F" size="1">
          <bitfield caption="Timer5 Compare Interrupt Mask" mask="0x02" name="T5CIM"/>
          <bitfield caption="Timer5 Overflow Interrupt Mask" mask="0x01" name="T5OIM"/>
        </register>
        <register caption="Timer5 Output Compare" name="T5OCR" offset="0x008A" size="2" mask="0xFFFF"/>
      </register-group>
      <value-group caption="" name="CLK_SEL_3BIT">
        <value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
        <value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
        <value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
        <value caption="Running, CLK/32" name="VAL_0x03" value="0x03"/>
        <value caption="Running, CLK/64" name="VAL_0x04" value="0x04"/>
        <value caption="Running, CLK/128" name="VAL_0x05" value="0x05"/>
        <value caption="Running, CLK/256" name="VAL_0x06" value="0x06"/>
        <value caption="Running, CLK/1024" name="VAL_0x07" value="0x07"/>
      </value-group>
    </module>
    <module caption="" name="TRACE">
      <register-group caption="" name="TRACE">
        <register caption="Trace Unit Control Register" name="TRCCR" offset="0x017E" size="1">
          <bitfield caption="Trace Unit Enable" mask="0x02" name="TRCEN"/>
          <bitfield caption="Trace Unit Change Enable" mask="0x01" name="TRCCE"/>
        </register>
        <register caption="Trace Unit Data Register" name="TRCDR" offset="0x017F" size="1" mask="0xFF"/>
        <register caption="Trace Identifier" name="TRCID" offset="0x0180" size="2" mask="0xFFFF"/>
      </register-group>
    </module>
    <module caption="" name="TXM">
      <register-group caption="" name="TXM">
        <register caption="Tx Modulator CRC Init Value" name="TMCI" offset="0x0134" size="2" mask="0xFFFF"/>
        <register caption="Tx Modulator CRC Polynomial" name="TMCP" offset="0x0135" size="2" mask="0xFFFF"/>
        <register caption="Tx Modulator Control Register 1" name="TMCR1" offset="0x013D" size="1">
          <bitfield caption="Tx Modulator Transmission Complete Interrupt Mask" mask="0x10" name="TMCIM"/>
          <bitfield caption="Tx Modulator Serial Output Clock Select" mask="0x08" name="TMSCS"/>
          <bitfield caption="Tx Modulator Port Interface Select" mask="0x07" name="TMPIS" values="TXM_PINTERFACE_SELECT"/>
        </register>
        <register caption="Tx Modulator Control Register 2" name="TMCR2" offset="0x013C" size="1">
          <bitfield caption="Tx Modulator Most Significant Bit First" mask="0x40" name="TMLSB"/>
          <bitfield caption="Tx Modulator Stop Sequence Enable" mask="0x20" name="TMSSE"/>
          <bitfield caption="Tx Modulator Polarity" mask="0x10" name="TMPOL"/>
          <bitfield caption="Tx Modulator NRZ Mode Enable" mask="0x08" name="TMNRZE"/>
          <bitfield caption="Tx Modulator CRC Length" mask="0x06" name="TMCRCL" values="TXM_CRC_LENGTH"/>
          <bitfield caption="Tx Modulator CRC Enable" mask="0x01" name="TMCRCE"/>
        </register>
        <register caption="Tx Modulator CRC Result" name="TMCR" offset="0x0130" size="2" mask="0xFFFF"/>
        <register caption="Tx Modulator CRC Skip Bit Number" name="TMCSB" offset="0x0132" size="1" mask="0xFF"/>
        <register caption="Tx Modulator Finite State Machine" name="TMFSM" offset="0x012F" size="1">
          <bitfield caption="Tx Modulator Master State Machine" mask="0x70" name="TMMSM"/>
          <bitfield caption="Tx Modulator Sub State Machine" mask="0x0F" name="TMSSM"/>
        </register>
        <register caption="Tx Modulator Shift Register" name="TMSHR" offset="0x0137" size="1" mask="0xFF"/>
        <register caption="Tx Modulator Status Register" name="TMSR" offset="0x013B" size="1">
          <bitfield caption="Tx Modulator Transmission Complete Status Flag" mask="0x01" name="TMTCF"/>
        </register>
        <register caption="Tx Modulator Stop Sequence Configuration" name="TMSSC" offset="0x013A" size="1">
          <bitfield caption="Tx Modulator Stop Sequence Hold Mode" mask="0x80" name="TMSSH"/>
          <bitfield caption="Tx Modulator Stop Sequence Length" mask="0x70" name="TMSSL"/>
          <bitfield caption="Tx Modulator Stop Sequence Pattern" mask="0x0F" name="TMSSP"/>
        </register>
        <register caption="Tx Modulator Telegram Length" name="TMTL" offset="0x0138" size="2" mask="0x0FFF"/>
      </register-group>
      <value-group caption="" name="TXM_CRC_LENGTH">
        <value caption="CRC 4-bit" name="VAL_0x00" value="0x00"/>
        <value caption="CRC 8-bit" name="VAL_0x01" value="0x01"/>
        <value caption="CRC 16-bit" name="VAL_0x02" value="0x02"/>
      </value-group>
      <value-group caption="" name="TXM_PINTERFACE_SELECT">
        <value caption="Port C3" name="VAL_0x00" value="0x00"/>
        <value caption="M2 - Toggle Register Timer2" name="VAL_0x01" value="0x01"/>
        <value caption="M3 - Toggle Register Timer3" name="VAL_0x02" value="0x02"/>
        <value caption="M4 - Toggle Register Timer4" name="VAL_0x03" value="0x03"/>
        <value caption="SO Tx Modulator Serial Output" name="VAL_0x04" value="0x04"/>
        <value caption="M1 - Toggle Register Timer1" name="VAL_0x05" value="0x05"/>
      </value-group>
    </module>
    <module caption="" name="VMON">
      <register-group caption="" name="VMON">
        <register caption="Voltage Monitor Control and Status Register" name="VMCSR" offset="0x004A" size="1">
          <bitfield caption="Voltage Monitor Flag" mask="0x20" name="VMF"/>
          <bitfield caption="Voltage Monitor Interrupt Mask" mask="0x10" name="VMIM"/>
          <bitfield caption="Voltage Monitor Level Select" mask="0x0F" name="VMLS" values="VMON_LEVEL_SELECT"/>
        </register>
      </register-group>
      <value-group caption="" name="VMON_LEVEL_SELECT">
        <value caption="disable" name="VAL_0x00" value="0x00"/>
        <value caption="2.0V" name="VAL_0x01" value="0x01"/>
        <value caption="2.1V" name="VAL_0x02" value="0x02"/>
        <value caption="2.2V" name="VAL_0x03" value="0x03"/>
        <value caption="2.3V" name="VAL_0x04" value="0x04"/>
        <value caption="2.4V" name="VAL_0x05" value="0x05"/>
        <value caption="2.5V" name="VAL_0x06" value="0x06"/>
        <value caption="2.6V" name="VAL_0x07" value="0x07"/>
        <value caption="2.7V" name="VAL_0x08" value="0x08"/>
        <value caption="2.8V" name="VAL_0x09" value="0x09"/>
        <value caption="2.9V" name="VAL_0x0A" value="0x0A"/>
        <value caption="3.0V" name="VAL_0x0B" value="0x0B"/>
        <value caption="3.1V" name="VAL_0x0C" value="0x0C"/>
        <value caption="3.2V" name="VAL_0x0D" value="0x0D"/>
        <value caption="3.3V" name="VAL_0x0E" value="0x0E"/>
        <value caption="3.4V" name="VAL_0x0F" value="0x0F"/>
      </value-group>
    </module>
  </modules>
</avr-tools-device-file>
