<?xml version='1.0' encoding='UTF-8'?>
<avr-tools-device-file xmlns:xalan="http://xml.apache.org/xalan" xmlns:NumHelper="NumHelper" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
  <variants>
    <variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="1.9" vccmax="3.6"/>
  </variants>
  <devices>
    <device name="ATA8210" architecture="AVR8" family="megaAVR">
      <address-spaces>
        <address-space endianness="little" name="prog" id="prog" start="0x0000" size="0xd000">
          <memory-segment start="0x0000" size="0x8000" type="rom" rw="R" exec="1" name="ROM" pagesize="0x40"/>
          <memory-segment start="0x8000" size="0x5000" type="flash" rw="RW" exec="1" name="FLASH" pagesize="0x40"/>
          <memory-segment start="0x8000" size="0x5000" type="flash" rw="RW" exec="1" name="BOOT_SECTION_1" pagesize="0x40"/>
        </address-space>
        <address-space endianness="little" name="signatures" id="signatures" start="0" size="3">
          <memory-segment start="0" size="3" type="signatures" rw="R" exec="0" name="SIGNATURES"/>
        </address-space>
        <address-space endianness="little" name="fuses" id="fuses" start="0" size="0x0001">
          <memory-segment start="0" size="0x0001" type="fuses" rw="RW" exec="0" name="FUSES"/>
        </address-space>
        <address-space endianness="little" name="lockbits" id="lockbits" start="0" size="0x0001">
          <memory-segment start="0" size="0x0001" type="lockbits" rw="RW" exec="0" name="LOCKBITS"/>
        </address-space>
        <address-space endianness="little" name="data" id="data" start="0x0000" size="0x0600">
          <memory-segment external="false" type="regs" size="0x0020" start="0x0000" name="REGISTERS"/>
          <memory-segment name="MAPPED_IO" start="0x0020" size="0x01e0" type="io" external="false"/>
          <memory-segment name="IRAM" start="0x0200" size="0x0400" type="ram" external="false"/>
        </address-space>
        <address-space endianness="little" name="eeprom" id="eeprom" start="0x0000" size="0x0480">
          <memory-segment start="0x0000" size="0x0400" type="eeprom" rw="RW" exec="0" name="EEPROM" pagesize="0x10"/>
          <memory-segment start="0x0400" size="0x0080" type="eeprom" rw="R" exec="0" name="CALDATA" pagesize="0x10"/>
        </address-space>
        <address-space size="0x40" start="0x00" endianness="little" name="io" id="io"/>
      </address-spaces>
      <peripherals>
        <module name="CHFLT">
          <instance name="CHFLT">
            <register-group name="CHFLT" name-in-module="CHFLT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CLK">
          <instance name="CLK">
            <register-group name="CLK" name-in-module="CLK" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CPU">
          <instance name="CPU">
            <register-group name="CPU" name-in-module="CPU" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="CRC">
          <instance name="CRC">
            <register-group name="CRC" name-in-module="CRC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DEBOUNCE">
          <instance name="DEBOUNCE">
            <register-group name="DEBOUNCE" name-in-module="DEBOUNCE" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DEBUG">
          <instance name="DEBUG">
            <register-group name="DEBUG" name-in-module="DEBUG" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DEMOD">
          <instance name="DEMOD">
            <register-group name="DEMOD" name-in-module="DEMOD" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="DFIFO">
          <instance name="DFIFO">
            <register-group name="DFIFO" name-in-module="DFIFO" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="EEPROM">
          <instance name="EEPROM">
            <register-group name="EEPROM" name-in-module="EEPROM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FE">
          <instance name="FE">
            <register-group name="FE" name-in-module="FE" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FREQS">
          <instance name="FREQS">
            <register-group name="FREQS" name-in-module="FREQS" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FRSYNC">
          <instance name="FRSYNC">
            <register-group name="FRSYNC" name-in-module="FRSYNC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="GPIOREGS">
          <instance name="GPIOREGS">
            <register-group name="GPIOREGS" name-in-module="GPIOREGS" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="IDSCAN">
          <instance name="IDSCAN">
            <register-group name="IDSCAN" name-in-module="IDSCAN" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="INT">
          <instance name="INT">
            <register-group name="INT" name-in-module="INT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="MEM">
          <instance name="MEM">
            <register-group name="MEM" name-in-module="MEM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="PORTB">
          <instance name="PORTB">
            <register-group name="PORTB" name-in-module="PORTB" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="PORTC">
          <instance name="PORTC">
            <register-group name="PORTC" name-in-module="PORTC" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="RSSIB">
          <instance name="RSSIB">
            <register-group name="RSSIB" name-in-module="RSSIB" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="RXBUF">
          <instance name="RXBUF">
            <register-group name="RXBUF" name-in-module="RXBUF" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="RXDSP">
          <instance name="RXDSP">
            <register-group name="RXDSP" name-in-module="RXDSP" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SFIFO">
          <instance name="SFIFO">
            <register-group name="SFIFO" name-in-module="SFIFO" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SPI">
          <instance name="SPI">
            <register-group name="SPI" name-in-module="SPI" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SSM">
          <instance name="SSM">
            <register-group name="SSM" name-in-module="SSM" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SUP">
          <instance name="SUP">
            <register-group name="SUP" name-in-module="SUP" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="SYMCH">
          <instance name="SYMCH">
            <register-group name="SYMCH" name-in-module="SYMCH" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TEMPER">
          <instance name="TEMPER">
            <register-group name="TEMPER" name-in-module="TEMPER" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER0_WDT">
          <instance name="TIMER0_WDT">
            <register-group name="TIMER0_WDT" name-in-module="TIMER0_WDT" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER1">
          <instance name="TIMER1">
            <register-group name="TIMER1" name-in-module="TIMER1" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER2">
          <instance name="TIMER2">
            <register-group name="TIMER2" name-in-module="TIMER2" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER3">
          <instance name="TIMER3">
            <register-group name="TIMER3" name-in-module="TIMER3" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER4">
          <instance name="TIMER4">
            <register-group name="TIMER4" name-in-module="TIMER4" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="TIMER5">
          <instance name="TIMER5">
            <register-group name="TIMER5" name-in-module="TIMER5" offset="0x00" address-space="data"/>
          </instance>
        </module>
        <module name="FUSE">
          <instance name="FUSE">
            <register-group name="FUSE" name-in-module="FUSE" offset="0" address-space="fuses"/>
          </instance>
        </module>
        <module name="LOCKBIT">
          <instance name="LOCKBIT">
            <register-group name="LOCKBIT" name-in-module="LOCKBIT" offset="0" address-space="lockbits"/>
          </instance>
        </module>
      </peripherals>
      <interrupts>
        <interrupt index="0" name="RESET" caption="External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset"/>
        <interrupt index="1" name="INT0" caption="External Interrupt Request 0"/>
        <interrupt index="2" name="INT1" caption="External Interrupt Request 1"/>
        <interrupt index="3" name="PCI0" caption="Pin Change Interrupt Request 0"/>
        <interrupt index="4" name="PCI1" caption="Pin Change Interrupt Request 1"/>
        <interrupt index="5" name="VMON" caption="Voltage Monitoring Interrupt"/>
        <interrupt index="6" name="AVCCR" caption="AVCC Reset Interrupt"/>
        <interrupt index="7" name="AVCCL" caption="AVCC Low Interrupt"/>
        <interrupt index="8" name="T0INT" caption="Timer 0 Interval Interrupt"/>
        <interrupt index="9" name="T1COMP" caption="Timer/Counter1 Compare Match Interrupt"/>
        <interrupt index="10" name="T1OVF" caption="Timer/Counter1 Overflow Interrupt"/>
        <interrupt index="11" name="T2COMP" caption="Timer/Counter2 Compare Match Interrupt"/>
        <interrupt index="12" name="T2OVF" caption="Timer/Counter2 Overflow Interrupt"/>
        <interrupt index="13" name="T3CAP" caption="Timer/Counter3 Capture Event Interrupt"/>
        <interrupt index="14" name="T3COMP" caption="Timer/Counter3 Compare Match Interrupt"/>
        <interrupt index="15" name="T3OVF" caption="Timer/Counter3 Overflow Interrupt"/>
        <interrupt index="16" name="T4CAP" caption="Timer/Counter4 Capture Event Interrupt"/>
        <interrupt index="17" name="T4COMP" caption="Timer/Counter4 Compare Match Interrupt"/>
        <interrupt index="18" name="T4OVF" caption="Timer/Counter4 Overflow Interrupt"/>
        <interrupt index="19" name="T5COMP" caption="Timer/Counter5 Compare Match Interrupt"/>
        <interrupt index="20" name="T5OVF" caption="Timer/Counter5 Overflow Interrupt"/>
        <interrupt index="21" name="SPI" caption="SPI Serial Transfer Complete Interrupt"/>
        <interrupt index="22" name="SRX_FIFO" caption="SPI Rx Buffer Interrupt"/>
        <interrupt index="23" name="STX_FIFO" caption="SPI Tx Buffer Interrupt"/>
        <interrupt index="24" name="SSM" caption="Sequencer State Machine Interrupt"/>
        <interrupt index="25" name="DFFLR" caption="Data FIFO fill level reached Interrupt"/>
        <interrupt index="26" name="DFOUE" caption="Data FIFO overflow or underflow error Interrupt"/>
        <interrupt index="27" name="SFFLR" caption="RSSI/Preamble FIFO fill level reached Interrupt"/>
        <interrupt index="28" name="SFOUE" caption="RSSI/Preamble FIFO overflow or underflow error Interrupt"/>
        <interrupt index="29" name="TMTCF" caption="Tx Modulator Telegram Finish Interrupt"/>
        <interrupt index="30" name="UHF_WCOB" caption="UHF receiver wake up ok on Rx path B"/>
        <interrupt index="31" name="UHF_WCOA" caption="UHF receiver wake up ok on Rx path A"/>
        <interrupt index="32" name="UHF_SOTB" caption="UHF receiver start of telegram ok on Rx path B"/>
        <interrupt index="33" name="UHF_SOTA" caption="UHF receiver start of telegram ok on Rx path A"/>
        <interrupt index="34" name="UHF_EOTB" caption="UHF receiver end of telegram on Rx path B"/>
        <interrupt index="35" name="UHF_EOTA" caption="UHF receiver end of telegram on Rx path A"/>
        <interrupt index="36" name="UHF_NBITB" caption="UHF receiver new bit on Rx path B"/>
        <interrupt index="37" name="UHF_NBITA" caption="UHF receiver new bit on Rx path A"/>
        <interrupt index="38" name="EXCM" caption="External input Clock monitoring Interrupt"/>
        <interrupt index="39" name="ERDY" caption="EEPROM Ready Interrupt"/>
        <interrupt index="40" name="SPMR" caption="Store Program Memory Ready"/>
        <interrupt index="41" name="IDFULL" caption="IDSCAN Full Interrupt"/>
      </interrupts>
      <interfaces>
        <interface name="ISP" type="isp"/>
        <interface name="debugWIRE" type="dw"/>
      </interfaces>
      <property-groups>
        <property-group name="SIGNATURES">
          <property name="JTAGID" value="0x9565"/>
          <property name="SIGNATURE0" value="0x1e"/>
          <property name="SIGNATURE1" value="0x95"/>
          <property name="SIGNATURE2" value="0x65"/>
        </property-group>
        <property-group name="OCD">
          <property name="OCD_REVISION" value="1"/>
          <property name="OCD_DATAREG" value="0x31"/>
          <property name="PROGBASE" value="0x0000"/>
        </property-group>
        <property-group name="JTAG_INTERFACE">
          <property name="ALLOWFULLPAGESTREAM" value="0x00"/>
        </property-group>
        <property-group name="ISP_INTERFACE">
          <property name="IspEnterProgMode_timeout" value="255"/>
          <property name="IspEnterProgMode_stabDelay" value="255"/>
          <property name="IspEnterProgMode_cmdexeDelay" value="45"/>
          <property name="IspEnterProgMode_synchLoops" value="64"/>
          <property name="IspEnterProgMode_bitDelay" value="5"/>
          <property name="IspEnterProgMode_byteDelay" value="5"/>
          <property name="IspEnterProgMode_pollIndex" value="3"/>
          <property name="IspEnterProgMode_pollValue" value="0x53"/>
          <property name="IspLeaveProgMode_preDelay" value="1"/>
          <property name="IspLeaveProgMode_postDelay" value="1"/>
          <property name="IspChipErase_eraseDelay" value="45"/>
          <property name="IspChipErase_pollMethod" value="1"/>
          <property name="IspProgramFlash_mode" value="0x41"/>
          <property name="IspProgramFlash_blockSize" value="32"/>
          <property name="IspProgramFlash_delay" value="10"/>
          <property name="IspProgramFlash_cmd1" value="0x40"/>
          <property name="IspProgramFlash_cmd2" value="0x4C"/>
          <property name="IspProgramFlash_cmd3" value="0x00"/>
          <property name="IspProgramFlash_pollVal1" value="0x00"/>
          <property name="IspProgramFlash_pollVal2" value="0x00"/>
          <property name="IspProgramEeprom_mode" value="0x41"/>
          <property name="IspProgramEeprom_blockSize" value="8"/>
          <property name="IspProgramEeprom_delay" value="20"/>
          <property name="IspProgramEeprom_cmd1" value="0xC1"/>
          <property name="IspProgramEeprom_cmd2" value="0xC2"/>
          <property name="IspProgramEeprom_cmd3" value="0x00"/>
          <property name="IspProgramEeprom_pollVal1" value="0x00"/>
          <property name="IspProgramEeprom_pollVal2" value="0x00"/>
          <property name="IspReadFlash_blockSize" value="256"/>
          <property name="IspReadEeprom_blockSize" value="256"/>
          <property name="IspReadFuse_pollIndex" value="4"/>
          <property name="IspReadLock_pollIndex" value="4"/>
          <property name="IspReadSign_pollIndex" value="4"/>
          <property name="IspReadOsccal_pollIndex" value="4"/>
        </property-group>
        <property-group name="ISP_INTERFACE_STK600">
          <property name="IspEnterProgMode_timeout" value="255"/>
          <property name="IspEnterProgMode_stabDelay" value="255"/>
          <property name="IspEnterProgMode_cmdexeDelay" value="45"/>
          <property name="IspEnterProgMode_synchLoops" value="64"/>
          <property name="IspEnterProgMode_byteDelay" value="4"/>
          <property name="IspEnterProgMode_pollIndex" value="3"/>
          <property name="IspEnterProgMode_pollValue" value="0x53"/>
          <property name="IspLeaveProgMode_preDelay" value="1"/>
          <property name="IspLeaveProgMode_postDelay" value="1"/>
          <property name="IspChipErase_eraseDelay" value="45"/>
          <property name="IspChipErase_pollMethod" value="1"/>
          <property name="IspProgramFlash_mode" value="0x41"/>
          <property name="IspProgramFlash_blockSize" value="32"/>
          <property name="IspProgramFlash_delay" value="10"/>
          <property name="IspProgramFlash_cmd1" value="0x40"/>
          <property name="IspProgramFlash_cmd2" value="0x4C"/>
          <property name="IspProgramFlash_cmd3" value="0x00"/>
          <property name="IspProgramFlash_pollVal1" value="0x00"/>
          <property name="IspProgramFlash_pollVal2" value="0x00"/>
          <property name="IspProgramEeprom_mode" value="0x41"/>
          <property name="IspProgramEeprom_blockSize" value="8"/>
          <property name="IspProgramEeprom_delay" value="20"/>
          <property name="IspProgramEeprom_cmd1" value="0xC1"/>
          <property name="IspProgramEeprom_cmd2" value="0xC2"/>
          <property name="IspProgramEeprom_cmd3" value="0x00"/>
          <property name="IspProgramEeprom_pollVal1" value="0x00"/>
          <property name="IspProgramEeprom_pollVal2" value="0x00"/>
          <property name="IspReadFlash_blockSize" value="256"/>
          <property name="IspReadEeprom_blockSize" value="256"/>
          <property name="IspReadFuse_pollIndex" value="4"/>
          <property name="IspReadLock_pollIndex" value="4"/>
          <property name="IspReadSign_pollIndex" value="4"/>
          <property name="IspReadOsccal_pollIndex" value="4"/>
        </property-group>
      </property-groups>
    </device>
  </devices>
  <modules>
    <module caption="" name="FUSE">
      <register-group caption="" name="FUSE">
        <register caption="" name="LOW" offset="0x00" size="1" initval="0xDF">
          <bitfield caption="Divide clock by 8 internally" mask="0x80" name="CKDIV8"/>
          <bitfield caption="Debug Wire enable" mask="0x40" name="DWEN"/>
          <bitfield caption="Serial program downloading (SPI) enabled" mask="0x20" name="SPIEN"/>
          <bitfield caption="Watch-dog Timer always on" mask="0x10" name="WDTON"/>
          <bitfield caption="Preserve EEPROM memory through the Chip Erase cycle" mask="0x08" name="EESAVE"/>
          <bitfield caption="Select interrupt vector location" mask="0x04" name="BOOTRST"/>
          <bitfield caption="Disable external Reset" mask="0x02" name="RSTDISBL"/>
          <bitfield caption="External Clock enable" mask="0x01" name="EXTCLKEN"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="LOCKBIT">
      <register-group caption="" name="LOCKBIT">
        <register caption="" name="LOCKBIT" offset="0x00" size="1">
          <bitfield caption="Memory Lock" mask="0x03" name="LB" values="ENUM_LB"/>
          <bitfield caption="Application Protection" mask="0x0C" name="AP" values="ENUM_AP"/>
          <bitfield caption="Boot Loader Protection" mask="0x30" name="BLP" values="ENUM_BLP"/>
        </register>
      </register-group>
      <value-group caption="" name="ENUM_LB">
        <value caption="Further programming and verification disabled" name="VAL_0x00" value="0x00"/>
        <value caption="Further programming disabled" name="VAL_0x02" value="0x02"/>
        <value caption="No memory lock features enable" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="ENUM_AP">
        <value caption="LPM and SPM prohibited in Application Section" name="VAL_0x00" value="0x00"/>
        <value caption="LPM prohibited in Application Section" name="VAL_0x04" value="0x04"/>
        <value caption="SPM prohibited in Application Section" name="VAL_0x08" value="0x08"/>
        <value caption="No lock on SPM and LPM in Application Section" name="VAL_0x0C" value="0x0C"/>
      </value-group>
      <value-group caption="" name="ENUM_BLP">
        <value caption="LPM and SPM prohibited in Boot Loader Section" name="VAL_0x00" value="0x00"/>
        <value caption="LPM prohibited in Boot Loader Section" name="VAL_0x10" value="0x10"/>
        <value caption="SPM prohibited in Boot Loader Section" name="VAL_0x20" value="0x20"/>
        <value caption="No lock on SPM and LPM in Boot Loader Section" name="VAL_0x30" value="0x30"/>
      </value-group>
    </module>
    <module caption="" name="CHFLT">
      <register-group caption="" name="CHFLT">
        <register caption="Channel Filter Configuration Register" name="CHCR" offset="0x00A9" size="1">
          <bitfield caption="Bandwidth Mode" mask="0x0F" name="BWM"/>
        </register>
        <register caption="Channel Filter Down Sampling Register" name="CHDN" offset="0x00AA" size="1">
          <bitfield caption="ADC Down Sampling Configuration" mask="0x20" name="ADCDN"/>
          <bitfield caption="Baseband Filter Down Sampling Ratio" mask="0x1F" name="BBDN"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="CLK">
      <register-group caption="" name="CLK">
        <register caption="Clock output control Register" name="CLKOCR" offset="0x00C4" size="1">
          <bitfield caption="Clock output driver enable" mask="0x04" name="CLKOEN"/>
          <bitfield caption="Clock output source" mask="0x03" name="CLKOS"/>
        </register>
        <register caption="Clock output divider settings Register" name="CLKOD" offset="0x00C3" size="1" mask="0xFF"/>
        <register caption="Clock management override control register" name="CMOCR" offset="0x00C9" size="1">
          <bitfield caption="SRC Active" mask="0x08" name="SRCACT"/>
          <bitfield caption="FRC Active" mask="0x04" name="FRCACT"/>
          <bitfield caption="SRC Always On" mask="0x02" name="SRCAO"/>
          <bitfield caption="FRC Always On" mask="0x01" name="FRCAO"/>
        </register>
        <register caption="Clock management status Register" name="CMSR" offset="0x00C8" size="1">
          <bitfield caption="External clock fail" mask="0x01" name="ECF"/>
        </register>
        <register caption="Fast RC oscillator calibration Register" name="FRCCAL" offset="0x00C7" size="1">
          <bitfield caption="Fast RC oscillator temperature compensation" mask="0x20" name="FRCTC"/>
          <bitfield caption="Fast RC oscillator calibration" mask="0x1F" name="FRCCAL"/>
        </register>
        <register caption="Power Reduction Register 0" name="PRR0" offset="0x21" size="1">
          <bitfield caption="Power Reduction Clock Output" mask="0x20" name="PRCO"/>
          <bitfield caption="Power Reduction Voltage Monitor" mask="0x10" name="PRVM"/>
          <bitfield caption="Power Reduction CRC" mask="0x08" name="PRCRC"/>
          <bitfield caption="Power Reduction Transmit DSP Control" mask="0x04" name="PRTXDC"/>
          <bitfield caption="Power Reduction Receive DSP Control" mask="0x02" name="PRRXDC"/>
          <bitfield caption="Power Reduction Serial Peripheral Interface" mask="0x01" name="PRSPI"/>
        </register>
        <register caption="Power Reduction Register 1" name="PRR1" offset="0x22" size="1">
          <bitfield caption="Power Reduction Timer 5" mask="0x10" name="PRT5"/>
          <bitfield caption="Power Reduction Timer 4" mask="0x08" name="PRT4"/>
          <bitfield caption="Power Reduction Timer 3" mask="0x04" name="PRT3"/>
          <bitfield caption="Power Reduction Timer 2" mask="0x02" name="PRT2"/>
          <bitfield caption="Power Reduction Timer 1" mask="0x01" name="PRT1"/>
        </register>
        <register caption="Power Reduction Register 2" name="PRR2" offset="0x23" size="1">
          <bitfield caption="Power Reduction Sequencer State Machine" mask="0x80" name="PRSSM"/>
          <bitfield caption="Power Reduction RSSI Buffer" mask="0x20" name="PRRS"/>
          <bitfield caption="Power Reduction ID Scan" mask="0x10" name="PRIDS"/>
          <bitfield caption="Power Reduction Data FIFO" mask="0x08" name="PRDF"/>
          <bitfield caption="Power Reduction Preamble/RSSI FIFO" mask="0x04" name="PRSF"/>
          <bitfield caption="Power Reduction Rx Buffer A" mask="0x02" name="PRXA"/>
          <bitfield caption="Power Reduction Rx Buffer B" mask="0x01" name="PRXB"/>
        </register>
        <register caption="Rx DSP power reduction register" name="RDPR" offset="0x0024" size="1">
          <bitfield caption="Rx DSP power reduction register(RDPR) busy flag" mask="0x80" name="RDPRF"/>
          <bitfield caption="Automatic Rx DSP Power Reduction Flag" mask="0x40" name="ARDPRF"/>
          <bitfield caption="Automatic Power Reduction of Path A" mask="0x20" name="APRPTA"/>
          <bitfield caption="Automatic Power Reduction of Path B" mask="0x10" name="APRPTB"/>
          <bitfield caption="Power reduction register for temperature measurement" mask="0x08" name="PRTMP"/>
          <bitfield caption="Power reduction register for the digital channel filter" mask="0x04" name="PRFLT"/>
          <bitfield caption="Power reduction register for the demodulator and receiving path B" mask="0x02" name="PRPTA"/>
          <bitfield caption="Power reduction register for the demodulator and receiving path A" mask="0x01" name="PRPTB"/>
        </register>
        <register caption="Slow RC oscillator calibration Register" name="SRCCAL" offset="0x00C6" size="1">
          <bitfield caption="Slow RC oscillator temperature compensation" mask="0xC0" name="SRCTC"/>
          <bitfield caption="Slow RC oscillator calibration" mask="0x3F" name="SRCCAL"/>
        </register>
        <register caption="" name="XFUSE" offset="0x00C5" size="1"/>
      </register-group>
    </module>
    <module caption="" name="CPU">
      <register-group caption="" name="CPU">
        <register caption="Clock Prescaler Register" name="CLPR" offset="0x5B" size="1">
          <bitfield caption="Clock Prescaler Change Enable" mask="0x80" name="CLPCE"/>
          <bitfield caption="Timer Clock Prescaler Select" mask="0x38" name="CLTPS" values="CPU_CLT_PRESCALE_3_BITS_SMALL"/>
          <bitfield caption="Clock Prescaler Select" mask="0x07" name="CLKPS" values="CPU_CLK_PRESCALE_3_BITS_SMALL"/>
        </register>
        <register caption="Clock Management Control Register" name="CMCR" offset="0x0059" size="1">
          <bitfield caption="Clock management control change enable" mask="0x80" name="CMCCE"/>
          <bitfield caption="Clock monitor enable" mask="0x40" name="CMONEN"/>
          <bitfield caption="Slow RC oscillator disable" mask="0x10" name="SRCD"/>
          <bitfield caption="Core Clock Select" mask="0x08" name="CCS"/>
          <bitfield caption="Clock Management Mode" mask="0x07" name="CMM"/>
        </register>
        <register caption="Clock Interrupt Mask Register" name="CMIMR" offset="0x005A" size="1">
          <bitfield caption="External clock interrupt enable" mask="0x01" name="ECIE"/>
        </register>
        <register caption="Status Register" name="SREG" offset="0x5F" size="1">
          <bitfield caption="Global Interrupt Enable" mask="0x80" name="I"/>
          <bitfield caption="Bit Copy Storage" mask="0x40" name="T"/>
          <bitfield caption="Half Carry Flag" mask="0x20" name="H"/>
          <bitfield caption="Sign Bit" mask="0x10" name="S"/>
          <bitfield caption="Two's Complement Overflow Flag" mask="0x08" name="V"/>
          <bitfield caption="Negative Flag" mask="0x04" name="N"/>
          <bitfield caption="Zero Flag" mask="0x02" name="Z"/>
          <bitfield caption="Carry Flag" mask="0x01" name="C"/>
        </register>
        <register caption="Stack Pointer " name="SP" offset="0x5D" size="2" mask="0x07FF"/>
        <register caption="Store Program Memory Control and Status Register" name="SPMCSR" offset="0x5C" size="1">
          <bitfield caption="SPM Interrupt Enable" mask="0x80" name="SPMIE"/>
          <bitfield caption="Boot Lock Bit Set" mask="0x08" name="BLBSET"/>
          <bitfield caption="Page Write" mask="0x04" name="PGWRT"/>
          <bitfield caption="Page Erase" mask="0x02" name="PGERS"/>
          <bitfield caption="Self Programming Enable" mask="0x01" name="SELFPRGEN"/>
        </register>
        <register caption="MCU Control Register" name="MCUCR" offset="0x2E" size="1">
          <bitfield caption="Port B7 High Side Driver enable" mask="0x80" name="PB7HS"/>
          <bitfield caption="Port B7 Low Side Driver enable" mask="0x40" name="PB7LS"/>
          <bitfield caption="Port B4 High Side Driver enable" mask="0x20" name="PB4HS"/>
          <bitfield caption="Pull-up Resistors Disable" mask="0x10" name="PUD"/>
          <bitfield caption="Enable Port Settings" mask="0x08" name="ENPS"/>
          <bitfield caption="SPI Interrupt Only" mask="0x04" name="SPIIO"/>
          <bitfield caption="Interrupt Vector Select" mask="0x02" name="IVSEL"/>
          <bitfield caption="Interrupt Vector Change Enable" mask="0x01" name="IVCE"/>
        </register>
        <register caption="MCU Status Register" name="MCUSR" offset="0x4B" size="1">
          <bitfield caption="Watchdog Reset Flag" mask="0x08" name="WDRF"/>
          <bitfield caption="External Reset Flag" mask="0x02" name="EXTRF"/>
          <bitfield caption="Power-on Reset flag" mask="0x01" name="PORF"/>
        </register>
        <register caption="Sleep mode control Register" name="SMCR" offset="0x58" size="1">
          <bitfield caption="Sleep Mode Select" mask="0x0E" name="SM" values="CPU_SLEEP_MODE_3BITS2"/>
          <bitfield caption="Sleep Enable" mask="0x01" name="SE"/>
        </register>
        <register caption="debugWire communication Register" name="DWDR" offset="0x0051" size="1" mask="0xFF" ocd-rw=""/>
      </register-group>
      <value-group caption="" name="CPU_CLT_PRESCALE_3_BITS_SMALL">
        <value caption="disabled" name="VAL_0x00" value="0x00"/>
        <value caption="1" name="VAL_0x01" value="0x01"/>
        <value caption="2" name="VAL_0x02" value="0x02"/>
        <value caption="4" name="VAL_0x03" value="0x03"/>
        <value caption="8" name="VAL_0x04" value="0x04"/>
        <value caption="16" name="VAL_0x05" value="0x05"/>
        <value caption="32" name="VAL_0x06" value="0x06"/>
        <value caption="64" name="VAL_0x07" value="0x07"/>
      </value-group>
      <value-group caption="" name="CPU_CLK_PRESCALE_3_BITS_SMALL">
        <value caption="1" name="VAL_0x00" value="0x00"/>
        <value caption="2" name="VAL_0x01" value="0x01"/>
        <value caption="4" name="VAL_0x02" value="0x02"/>
        <value caption="8" name="VAL_0x03" value="0x03"/>
        <value caption="16" name="VAL_0x04" value="0x04"/>
        <value caption="32" name="VAL_0x05" value="0x05"/>
        <value caption="64" name="VAL_0x06" value="0x06"/>
        <value caption="128" name="VAL_0x07" value="0x07"/>
      </value-group>
      <value-group caption="" name="CPU_SLEEP_MODE_3BITS2">
        <value caption="Idle" name="IDLE" value="0x00"/>
        <value caption="Extended power-save" name="EPSAVE" value="0x01"/>
        <value caption="Power Down" name="PDOWN" value="0x02"/>
        <value caption="Power Save" name="PSAVE" value="0x03"/>
        <value caption="Reserved" name="VAL_0x04" value="0x04"/>
        <value caption="Reserved" name="VAL_0x05" value="0x05"/>
        <value caption="Reserved" name="VAL_0x06" value="0x06"/>
        <value caption="Reserved" name="VAL_0x07" value="0x07"/>
      </value-group>
    <parameters><param name="CORE_VERSION" value="V2E"/></parameters></module>
    <module caption="" name="CRC">
      <register-group caption="" name="CRC">
        <register caption="CRC Control Register" name="CRCCR" offset="0x145" size="1">
          <bitfield caption="Reflect Data Output Byte" mask="0x04" name="REFLO"/>
          <bitfield caption="Reflect Data Input Byte" mask="0x02" name="REFLI"/>
          <bitfield caption="CRC Data Register Reset" mask="0x01" name="CRCRS"/>
        </register>
        <register caption="CRC Data Input Register" name="CRCDIR" offset="0x49" size="1" mask="0xFF"/>
        <register caption="CRC Data Output Register" name="CRCDOR" offset="0x146" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="DEBOUNCE">
      <register-group caption="" name="DEBOUNCE">
        <register caption="DeBounce Control Register" name="DBCR" offset="0x0152" size="1">
          <bitfield caption="Debounce Handshake Active" mask="0x08" name="DBHA"/>
          <bitfield caption="Debounce Timer Mask Select" mask="0x04" name="DBTMS"/>
          <bitfield caption="Debounce Clock Select" mask="0x02" name="DBCS"/>
          <bitfield caption="Debounce Mode" mask="0x01" name="DBMD"/>
        </register>
        <register caption="DeBounce Enable Port B" name="DBENB" offset="0x0154" size="1" mask="0xFF"/>
        <register caption="DeBounce Enable Port C" name="DBENC" offset="0x0155" size="1" mask="0x3F"/>
        <register caption="Debounce Timer Compare Register" name="DBTC" offset="0x0153" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="DEBUG">
      <register-group caption="" name="DEBUG">
        <register caption="Debugging Support Switch" name="DBGSW" offset="0x0156" size="1">
          <bitfield caption="Debugging Support Switch Enable" mask="0x80" name="DBGSE"/>
          <bitfield caption="CPU Busy Flag" mask="0x40" name="CPBF"/>
          <bitfield caption="CPU Busy Flag Output Select" mask="0x30" name="CPBFOS"/>
          <bitfield caption="Debugging Support Group Select" mask="0x0F" name="DBGGS"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="DEMOD">
      <register-group caption="" name="DEMOD">
        <register caption="Demodulator Carrier Detect for path A" name="DMCDA" offset="0x00A4" size="1">
          <bitfield caption="Demodulator Carrier Detect Time for path A" mask="0xE0" name="DMCTA"/>
          <bitfield caption="Demodulator Carrier Detect Limit for path A" mask="0x1F" name="DMCLA"/>
        </register>
        <register caption="Demodulator Carrier Detect for path B" name="DMCDB" offset="0x00A3" size="1">
          <bitfield caption="Demodulator Carrier Detect Time for path B" mask="0xE0" name="DMCTB"/>
          <bitfield caption="Demodulator Carrier Detect Limit for path B" mask="0x1F" name="DMCLB"/>
        </register>
        <register caption="Demodulator Control Register for path A" name="DMCRA" offset="0x00A6" size="1">
          <bitfield caption="Demodulator automatic restart on path A" mask="0x80" name="DMARA"/>
          <bitfield caption="Symbol check with only 1T on path A" mask="0x40" name="SY1TA"/>
          <bitfield caption="Select ASK input for path A" mask="0x20" name="SASKA"/>
          <bitfield caption="Demodulator PLL loop gain for path A" mask="0x1F" name="DMPGA"/>
        </register>
        <register caption="Demodulator Control Register for path B" name="DMCRB" offset="0x00A5" size="1">
          <bitfield caption="Demodulator automatic restart on path B" mask="0x80" name="DMARB"/>
          <bitfield caption="Symbol check with only 1T on path B" mask="0x40" name="SY1TB"/>
          <bitfield caption="Select ASK input for path B" mask="0x20" name="SASKB"/>
          <bitfield caption="Demodulator PLL loop gain for path B" mask="0x1F" name="DMPGB"/>
        </register>
        <register caption="Demodulator Data Rate on path A" name="DMDRA" offset="0x00A8" size="1">
          <bitfield caption="Demodulator Downsampling on path A" mask="0xF0" name="DMDNA"/>
          <bitfield caption="Demodulator Moving Average Data Rate factor on path A" mask="0x0F" name="DMAA"/>
        </register>
        <register caption="Demodulator Data Rate on path B" name="DMDRB" offset="0x00A7" size="1">
          <bitfield caption="Demodulator Downsampling on path B" mask="0xF0" name="DMDNB"/>
          <bitfield caption="Demodulator Moving Average Data Rate factor on path B" mask="0x0F" name="DMAB"/>
        </register>
        <register caption="Demodulator Mode for path A" name="DMMA" offset="0x00A2" size="1">
          <bitfield caption="Demodulator NRZ Enable for path A" mask="0x80" name="DMNEA"/>
          <bitfield caption="Demodulator Hold Mode for path A" mask="0x40" name="DMHA"/>
          <bitfield caption="Demodulator Data Polarity Selection for path A" mask="0x20" name="DMPA"/>
          <bitfield caption="Demodulator Amplitude Threshold for path A" mask="0x1F" name="DMATA"/>
        </register>
        <register caption="Demodulator Mode for Path B" name="DMMB" offset="0x00A1" size="1">
          <bitfield caption="Demodulator NRZ Enable for path B" mask="0x80" name="DMNEB"/>
          <bitfield caption="Demodulator Hold Mode for path B" mask="0x40" name="DMHB"/>
          <bitfield caption="Demodulator Data Polarity Selection for path B" mask="0x20" name="DMPB"/>
          <bitfield caption="Demodulator Amplitude Threshold for path B" mask="0x1F" name="DMATB"/>
        </register>
        <register caption="Received Frequency Offset vs Intermediate Frequency on path A" name="RXFOA" offset="0x00A0" size="1" mask="0xFF"/>
        <register caption="Received Frequency Offset vs Intermediate Frequency on path B" name="RXFOB" offset="0x009F" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="DFIFO">
      <register-group caption="" name="DFIFO">
        <register caption="Data FIFO Configuration Register" name="DFC" offset="0x00DA" size="1">
          <bitfield caption="Data FIFO Direct Read Access Operational Mode" mask="0x80" name="DFDRA"/>
          <bitfield caption="Data FIFO Fill-Level Configuration" mask="0x3F" name="DFFLC"/>
        </register>
        <register caption="Data FIFO Data Register" name="DFD" offset="0x00D8" size="1" mask="0xFF"/>
        <register caption="Data FIFO Interrupt Mask Register" name="DFI" offset="0x00D9" size="1">
          <bitfield caption="Data FIFO Error Interrupt Mask" mask="0x02" name="DFERIM"/>
          <bitfield caption="Data FIFO Fill-level Interrupt Mask" mask="0x01" name="DFFLIM"/>
        </register>
        <register caption="Data FIFO Fill Level Register" name="DFL" offset="0x00D5" size="1">
          <bitfield caption="Data FIFO Clear" mask="0x80" name="DFCLR"/>
          <bitfield caption="Data FIFO Fill Level Status" mask="0x3F" name="DFFLS"/>
        </register>
        <register caption="Data FIFO Read Pointer" name="DFRP" offset="0x00D7" size="1">
          <bitfield caption="Data FIFO Read Pointer" mask="0x3F" name="DFRP"/>
        </register>
        <register caption="Data FIFO Status Register" name="DFS" offset="0x00D2" size="1">
          <bitfield caption="Data FIFO Overflow Flag" mask="0x04" name="DFOFL"/>
          <bitfield caption="Data FIFO Underflow Flag" mask="0x02" name="DFUFL"/>
          <bitfield caption="Data FIFO Fill-Level Reached Status Flag" mask="0x01" name="DFFLRF"/>
        </register>
        <register caption="Data FIFO Telegram Length" name="DFTL" offset="0x00D3" size="2" mask="0x0FFF"/>
        <register caption="Data FIFO Write Pointer" name="DFWP" offset="0x00D6" size="1">
          <bitfield caption="Data FIFO Write Pointer" mask="0x3F" name="DFWP"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="EEPROM">
      <register-group caption="" name="EEPROM">
        <register caption="EEPROM Address Register" name="EEAR" offset="0x0041" size="2" mask="0x07FF"/>
        <register caption="EEPROM Control Register" name="EECR" offset="0x003F" size="1">
          <bitfield caption="Non-volatile memory busy" mask="0x80" name="NVMBSY"/>
          <bitfield caption="EEPROM page access (multiple bytes access mode)" mask="0x40" name="EEPAGE"/>
          <bitfield caption="EEPROM Programming Mode" mask="0x30" name="EEPM" values="EEP_MODE"/>
          <bitfield caption="EEPROM Ready Interrupt Enable" mask="0x08" name="EERIE"/>
          <bitfield caption="EEPROM Master Write Enable" mask="0x04" name="EEMWE"/>
          <bitfield caption="EEPROM Write Enable" mask="0x02" name="EEWE"/>
          <bitfield caption="EEPROM Read Enable" mask="0x01" name="EERE"/>
        </register>
        <register caption="EEPROM Control Register 2" name="EECR2" offset="0x0159" size="1">
          <bitfield caption="EEPROM Burst Read Enable" mask="0x01" name="EEBRE"/>
        </register>
        <register caption="EEPROM Data Register" name="EEDR" offset="0x0040" size="1" mask="0xFF"/>
        <register caption="EEPROM Protection Register" name="EEPR" offset="0x0043" size="1">
          <bitfield caption="EEPROM Access Protection" mask="0x0F" name="EEAP"/>
        </register>
      </register-group>
      <value-group caption="" name="EEP_MODE">
        <value caption="Erase and Write in one operation" name="VAL_0x00" value="0x00"/>
        <value caption="Erase Only" name="VAL_0x01" value="0x01"/>
        <value caption="Write Only" name="VAL_0x02" value="0x02"/>
      </value-group>
    </module>
    <module caption="" name="FE">
      <register-group caption="" name="FE">
        <register caption="Front-End Antenna Level Detector Range" name="FEALR" offset="0x010C" size="1">
          <bitfield caption="Range of the ANT_TUNE level detector" mask="0x03" name="RNGE" values="FE_ALR_RANGE"/>
        </register>
        <register caption="Front-End ANTenna" name="FEANT" offset="0x010D" size="1">
          <bitfield caption="antenna signal LeVeL" mask="0x0F" name="LVLC"/>
        </register>
        <register caption="Front-End IF Amplifier BIAS" name="FEBIA" offset="0x010E" size="1">
          <bitfield caption="IF Amplifier Enable" mask="0x80" name="IFAEN"/>
        </register>
        <register caption="Front-End RC Tuning Register" name="FEBT" offset="0x0107" size="1">
          <bitfield caption="Resistor Tuning" mask="0x0C" name="RTN2"/>
          <bitfield caption="Capacitor Tuning" mask="0x03" name="CTN2"/>
        </register>
        <register caption="Front-End Control Register" name="FECR" offset="0x010A" size="1">
          <bitfield caption="ASK Not DPSK Switch" mask="0x20" name="ANPS"/>
          <bitfield caption="PLL Lock Detect Gate" mask="0x10" name="PLCKG"/>
          <bitfield caption="ADC High Sample Rate" mask="0x08" name="ADHS"/>
          <bitfield caption="Antenna Damping" mask="0x04" name="ANDP"/>
          <bitfield caption="Select 433 Not 315MHz Band" mask="0x02" name="S4N3"/>
          <bitfield caption="Select Low-Band Not High-Band" mask="0x01" name="LBNHB"/>
        </register>
        <register caption="Front-End Enable Register 1" name="FEEN1" offset="0x0101" size="1">
          <bitfield caption="Antenna Tuning Enable" mask="0x80" name="ATEN"/>
          <bitfield caption="PLL Speedup 1" mask="0x40" name="PLSP1"/>
          <bitfield caption="ADC Clock enable" mask="0x20" name="ADCLK"/>
          <bitfield caption="Analog Digital Converter enable" mask="0x10" name="ADEN"/>
          <bitfield caption="Low Noise Amplifier enable" mask="0x08" name="LNAEN"/>
          <bitfield caption="Cristal Oscillator enable" mask="0x04" name="XTOEN"/>
          <bitfield caption="PLL calibration mode" mask="0x02" name="PLCAL"/>
          <bitfield caption="PLL enable" mask="0x01" name="PLEN"/>
        </register>
        <register caption="Front-End Enable Register 2" name="FEEN2" offset="0x0102" size="1">
          <bitfield caption="XTO VPump enable" mask="0x20" name="XTPEN"/>
          <bitfield caption="PLL Post En IQ divider" mask="0x10" name="PLPEN"/>
          <bitfield caption="Temperature measurement" mask="0x08" name="TMPM"/>
          <bitfield caption="Power Amplifier enable" mask="0x04" name="PAEN"/>
          <bitfield caption="Single Pole Double Throw (SPDT) Switch TX" mask="0x02" name="SDRX2"/>
          <bitfield caption="Single Pole Double Throw (SPDT) Switch RX" mask="0x01" name="SDRX"/>
        </register>
        <register caption="Front-End LNA Bias Register" name="FELNA" offset="0x0103" size="1">
          <bitfield caption="LNA Bias Low band" mask="0xF0" name="LBL"/>
          <bitfield caption="LNA Bias High band" mask="0x0F" name="LBH"/>
        </register>
        <register caption="Front-End Main and Swallow Control Register" name="FEMS" offset="0x0108" size="1">
          <bitfield caption="PLL Mode" mask="0xF0" name="PLLM"/>
          <bitfield caption="PLL Swallow" mask="0x0F" name="PLLS"/>
        </register>
        <register caption="Front-End Status Register" name="FESR" offset="0x0100" size="1">
          <bitfield caption="PLL locked" mask="0x08" name="PLCK"/>
          <bitfield caption="XTO ready" mask="0x04" name="XRDY"/>
          <bitfield caption="LNA High band saturated" mask="0x02" name="HBSAT"/>
          <bitfield caption="LNA Low band saturated" mask="0x01" name="LBSAT"/>
        </register>
        <register caption="Front-End RC Tuning 4bit Register" name="FETN4" offset="0x0109" size="1">
          <bitfield caption="4 bit Resistor Tuning" mask="0xF0" name="RTN4"/>
          <bitfield caption="4 bit Capacitor Tuning" mask="0x0F" name="CTN4"/>
        </register>
        <register caption="Front-End VCO and PLL control" name="FEVCO" offset="0x010B" size="1">
          <bitfield caption="VCO Bias" mask="0xF0" name="VCOB"/>
          <bitfield caption="Charge pump current control" mask="0x0F" name="CPCC"/>
        </register>
        <register caption="Front-End VCO Tuning Register" name="FEVCT" offset="0x0106" size="1">
          <bitfield caption="Front-End VCO Tuning Register" mask="0x0F" name="FEVCT"/>
        </register>
      </register-group>
      <value-group caption="" name="FE_ALR_RANGE">
        <value caption="0..3 dBm" name="VAL_0x00" value="0x00"/>
        <value caption="4..7 dBm" name="VAL_0x01" value="0x01"/>
        <value caption="8..14 dBm" name="VAL_0x02" value="0x02"/>
        <value caption="Secure Measurement" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="FREQS">
      <register-group caption="" name="FREQS">
        <register caption="Fractional Frequency 1 Setting, High Byte" name="FFREQ1H" offset="0x0066" size="1" mask="0x03"/>
        <register caption="Fractional Frequency 1 Setting, Low Byte" name="FFREQ1L" offset="0x0064" size="1" mask="0xFF"/>
        <register caption="Fractional Frequency 1 Setting, Middle Byte" name="FFREQ1M" offset="0x0065" size="1" mask="0xFF"/>
        <register caption="Fractional Frequency 2 Setting, High Byte" name="FFREQ2H" offset="0x0069" size="1" mask="0x03"/>
        <register caption="Fractional Frequency 2 Setting, Low Byte" name="FFREQ2L" offset="0x0067" size="1" mask="0xFF"/>
        <register caption="Fractional Frequency 2 Setting, Middle Byte" name="FFREQ2M" offset="0x0068" size="1" mask="0xFF"/>
        <register caption="Frequency Synthesizer Enable register" name="FSEN" offset="0x0060" size="1">
          <bitfield caption="Sigma-delta Modulator Enable" mask="0x02" name="SDEN"/>
          <bitfield caption="Sigma-delta Modulator Power Up" mask="0x01" name="SDPU"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="FRSYNC">
      <register-group caption="" name="FRSYNC">
        <register caption="Start-Frame ID byte 1 for data path A" name="SFID1A" offset="0x00BB" size="1" mask="0xFF"/>
        <register caption="Start-Frame ID byte 1 for data path B" name="SFID1B" offset="0x00AF" size="1" mask="0xFF"/>
        <register caption="Start-Frame ID byte 2 for data path A" name="SFID2A" offset="0x00BC" size="1" mask="0xFF"/>
        <register caption="Start-Frame ID byte 2 for data path B" name="SFID2B" offset="0x00B0" size="1" mask="0xFF"/>
        <register caption="Start-Frame ID byte 3 for data path A" name="SFID3A" offset="0x00BD" size="1" mask="0xFF"/>
        <register caption="Start-Frame ID byte 3 for data path B" name="SFID3B" offset="0x00B1" size="1" mask="0xFF"/>
        <register caption="Start-Frame ID byte 4 for data path A" name="SFID4A" offset="0x00BE" size="1" mask="0xFF"/>
        <register caption="Start-Frame ID byte 4 for data path B" name="SFID4B" offset="0x00B2" size="1" mask="0xFF"/>
        <register caption="Start-Frame ID Control for data path A" name="SFIDCA" offset="0x00B7" size="1">
          <bitfield caption="Serial mode enable for data path A" mask="0x80" name="SEMEA"/>
          <bitfield caption="Start-Frame ID threshold for data path A" mask="0x1F" name="SFIDTA"/>
        </register>
        <register caption="Start-Frame ID Control for data path B" name="SFIDCB" offset="0x00AB" size="1">
          <bitfield caption="Serial mode enable for data path B" mask="0x80" name="SEMEB"/>
          <bitfield caption="Start-Frame ID threshold for data path B" mask="0x1F" name="SFIDTB"/>
        </register>
        <register caption="Start-Frame ID Length for data path A" name="SFIDLA" offset="0x00B8" size="1">
          <bitfield caption="Start-Frame ID Length for data path A" mask="0x3F" name="SFIDLA"/>
        </register>
        <register caption="Start-Frame ID Length for data path B" name="SFIDLB" offset="0x00AC" size="1">
          <bitfield caption="Start-Frame ID Length for data path B" mask="0x3F" name="SFIDLB"/>
        </register>
        <register caption="Wake-Up Pattern byte 1 for data path A" name="WUP1A" offset="0x00BF" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern byte 1 for data path B" name="WUP1B" offset="0x00B3" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern byte 2 for data path A" name="WUP2A" offset="0x00C0" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern byte 2 for data path B" name="WUP2B" offset="0x00B4" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern byte 3 for data path A" name="WUP3A" offset="0x00C1" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern byte 3 for data path B" name="WUP3B" offset="0x00B5" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern byte 4 for data path A" name="WUP4A" offset="0x00C2" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern byte 4 for data path B" name="WUP4B" offset="0x00B6" size="1" mask="0xFF"/>
        <register caption="Wake-Up Pattern Length for data path A" name="WUPLA" offset="0x00BA" size="1">
          <bitfield caption="Wake-Up Pattern Length for data path A" mask="0x3F" name="WUPLA"/>
        </register>
        <register caption="Wake-Up Pattern Length for data path B" name="WUPLB" offset="0x00AE" size="1">
          <bitfield caption="Wake-Up Pattern Length for data path B" mask="0x3F" name="WUPLB"/>
        </register>
        <register caption="Wake-Up Pattern Threshold for data path A" name="WUPTA" offset="0x00B9" size="1">
          <bitfield caption="Wake-Up Pattern Threshold for data path A" mask="0x1F" name="WUPTA"/>
        </register>
        <register caption="Wake-Up Pattern Threshold for data path B" name="WUPTB" offset="0x00AD" size="1">
          <bitfield caption="Wake-Up Pattern Threshold for data path B" mask="0x1F" name="WUPTB"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="GPIOREGS">
      <register-group caption="" name="GPIOREGS">
        <register caption="General Purpose I/O Register 0" name="GPIOR0" offset="0x003A" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 1" name="GPIOR1" offset="0x0044" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 2" name="GPIOR2" offset="0x0045" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 3" name="GPIOR3" offset="0x003B" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 4" name="GPIOR4" offset="0x003C" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 5" name="GPIOR5" offset="0x003D" size="1" mask="0xFF"/>
        <register caption="General Purpose I/O Register 6" name="GPIOR6" offset="0x003E" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="IDSCAN">
      <register-group caption="" name="IDSCAN">
        <register caption="ID Byte 0" name="IDB0" offset="0x0147" size="1" mask="0xFF"/>
        <register caption="ID Byte 1" name="IDB1" offset="0x0148" size="1" mask="0xFF"/>
        <register caption="ID Byte 2" name="IDB2" offset="0x0149" size="1" mask="0xFF"/>
        <register caption="ID Byte 3" name="IDB3" offset="0x014A" size="1" mask="0xFF"/>
        <register caption="ID Configuration" name="IDC" offset="0x014B" size="1">
          <bitfield caption="ID Check Execute" mask="0x80" name="IDCE"/>
          <bitfield caption="ID Clear" mask="0x40" name="IDCLR"/>
          <bitfield caption="ID Full Interrupt Mask" mask="0x20" name="IDFIM"/>
          <bitfield caption="ID Byte Offset" mask="0x0C" name="IDBO"/>
          <bitfield caption="ID Length" mask="0x03" name="IDL"/>
        </register>
        <register caption="ID Status" name="IDS" offset="0x014C" size="1">
          <bitfield caption="ID Full Flag" mask="0x02" name="IDFULL"/>
          <bitfield caption="ID Scan Ok Flag" mask="0x01" name="IDOK"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="INT">
      <register-group caption="" name="INT">
        <register caption="External Interrupt control Register" name="EICRA" offset="0x006B" size="1">
          <bitfield caption="Interrupt Sense Control 1" mask="0x0C" name="ISC1" values="INTERRUPT_SENSE_CONTROL"/>
          <bitfield caption="Interrupt Sense Control 0" mask="0x03" name="ISC0" values="INTERRUPT_SENSE_CONTROL"/>
        </register>
        <register caption="External Interrupt Flag Register" name="EIFR" offset="0x0048" size="1">
          <bitfield caption="External Interrupt Flag 1" mask="0x02" name="INTF1"/>
          <bitfield caption="External Interrupt Flag 0" mask="0x01" name="INTF0"/>
        </register>
        <register caption="External Interrupt Mask Register" name="EIMSK" offset="0x0047" size="1">
          <bitfield caption="External Interrupt Request 1 Enable" mask="0x02" name="INT1"/>
          <bitfield caption="External Interrupt Request 0 Enable" mask="0x01" name="INT0"/>
        </register>
        <register caption="Pin change Interrupt control Register" name="PCICR" offset="0x0046" size="1">
          <bitfield caption="Pin Change Interrupt Enable 1" mask="0x02" name="PCIE1"/>
          <bitfield caption="Pin Change Interrupt Enable 0" mask="0x01" name="PCIE0"/>
        </register>
        <register caption="Pin change Interrupt flag Register" name="PCIFR" offset="0x002F" size="1">
          <bitfield caption="Pin Change Interrupt Flag 1" mask="0x02" name="PCIF1"/>
          <bitfield caption="Pin Change Interrupt Flag 0" mask="0x01" name="PCIF0"/>
        </register>
        <register caption="Pin change Mask Register 0" name="PCMSK0" offset="0x006C" size="1">
          <bitfield caption="Pin Change Enable Mask bit 0" mask="0x01" name="PCINT0"/>
          <bitfield caption="Pin Change Enable Mask bit 1" mask="0x02" name="PCINT1"/>
          <bitfield caption="Pin Change Enable Mask bit 2" mask="0x04" name="PCINT2"/>
          <bitfield caption="Pin Change Enable Mask bit 3" mask="0x08" name="PCINT3"/>
          <bitfield caption="Pin Change Enable Mask bit 4" mask="0x10" name="PCINT4"/>
          <bitfield caption="Pin Change Enable Mask bit 5" mask="0x20" name="PCINT5"/>
          <bitfield caption="Pin Change Enable Mask bit 6" mask="0x40" name="PCINT6"/>
          <bitfield caption="Pin Change Enable Mask bit 7" mask="0x80" name="PCINT7"/>
        </register>
        <register caption="Pin change Mask Register 1" name="PCMSK1" offset="0x006D" size="1">
          <bitfield caption="Pin Change Enable Mask bit 8" mask="0x01" name="PCINT8"/>
          <bitfield caption="Pin Change Enable Mask bit 9" mask="0x02" name="PCINT9"/>
          <bitfield caption="Pin Change Enable Mask bit 10" mask="0x04" name="PCINT10"/>
          <bitfield caption="Pin Change Enable Mask bit 11" mask="0x08" name="PCINT11"/>
          <bitfield caption="Pin Change Enable Mask bit 12" mask="0x10" name="PCINT12"/>
          <bitfield caption="Pin Change Enable Mask bit 13" mask="0x20" name="PCINT13"/>
        </register>
      </register-group>
      <value-group caption="Interrupt Sense Control" name="INTERRUPT_SENSE_CONTROL">
        <value caption="Low Level of INTX" name="VAL_0x00" value="0x00"/>
        <value caption="Logical Change of INTX" name="VAL_0x01" value="0x01"/>
        <value caption="Falling Edge of INTX" name="VAL_0x02" value="0x02"/>
        <value caption="Rising Edge of INTX" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="MEM">
      <register-group caption="" name="MEM">
        <register caption="EEPROM Status Register" name="EEST" offset="0x015B" size="1">
          <bitfield caption="EEPROM Syndrome" mask="0x0F" name="EESYN"/>
        </register>
        <register caption="Program Memory Status Register" name="PGMST" offset="0x015A" size="1">
          <bitfield caption="Program Memory Syndrome" mask="0x1F" name="PGMSYN"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="PORTB">
      <register-group caption="" name="PORTB">
        <register caption="Port B Data Register" name="PORTB" offset="0x27" size="1" mask="0xFF"/>
        <register caption="Port B Data Direction Register" name="DDRB" offset="0x26" size="1" mask="0xFF"/>
        <register caption="Port B Input Pins" name="PINB" offset="0x25" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="PORTC">
      <register-group caption="" name="PORTC">
        <register caption="Port C Data Register" name="PORTC" offset="0x2A" size="1" mask="0x3F"/>
        <register caption="Port C Data Direction Register" name="DDRC" offset="0x29" size="1" mask="0x3F"/>
        <register caption="Port C Input Pins" name="PINC" offset="0x28" size="1" mask="0x3F"/>
      </register-group>
    </module>
    <module caption="" name="RSSIB">
      <register-group caption="" name="RSSIB">
        <register caption="RSSI Compensation Register" name="RSCOM" offset="0x015F" size="1">
          <bitfield caption="RSSI IF Amplifier Compensation" mask="0x02" name="RSIFC"/>
          <bitfield caption="RSSI Damping Compensation" mask="0x01" name="RSDC"/>
        </register>
        <register caption="RSSI High Band Damping Value" name="RSHDV" offset="0x015E" size="1" mask="0xFF"/>
        <register caption="RSSI High IF Amplifier Gain" name="RSIFG" offset="0x015C" size="1" mask="0xFF"/>
        <register caption="RSSI Low Band Damping Value" name="RSLDV" offset="0x015D" size="1" mask="0xFF"/>
        <register caption="RSSI Average Value" name="RSSAV" offset="0x014D" size="1" mask="0xFF"/>
        <register caption="RSSI Configuration Register" name="RSSC" offset="0x0151" size="1">
          <bitfield caption="RSSI Peak Values to SFIFO" mask="0x40" name="RSPKF"/>
          <bitfield caption="RSSI High Band Reception" mask="0x20" name="RSHRX"/>
          <bitfield caption="RSSI within Low and High Limits" mask="0x10" name="RSWLH"/>
          <bitfield caption="RSSI Update Period" mask="0x0F" name="RSUP"/>
        </register>
        <register caption="RSSI High Threshold for Signal Check" name="RSSH" offset="0x0150" size="1" mask="0xFF"/>
        <register caption="RSSI Low Threshold for Signal Check" name="RSSL" offset="0x014F" size="1" mask="0xFF"/>
        <register caption="RSSI Peak Value" name="RSSPK" offset="0x014E" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="RXBUF">
      <register-group caption="" name="RXBUF">
        <register caption="Rx Buffer configuration register 1" name="RXBC1" offset="0x012F" size="1">
          <bitfield caption="Receive Data MSB-first for data path B" mask="0x80" name="RXMSBB"/>
          <bitfield caption="Receive CRC Bit Lengths setting for data path B" mask="0x60" name="RXCBLB" values="RXBUF_CRC_LENGTH"/>
          <bitfield caption="RX CRC Enable data path B" mask="0x10" name="RXCEB"/>
          <bitfield caption="Receive Data MSB-first for data path A" mask="0x08" name="RXMSBA"/>
          <bitfield caption="Receive CRC Bit Lengths setting for data path A" mask="0x06" name="RXCBLA" values="RXBUF_CRC_LENGTH"/>
          <bitfield caption="RX CRC Enable data path A" mask="0x01" name="RXCEA"/>
        </register>
        <register caption="Rx Buffer configuration register 2" name="RXBC2" offset="0x0130" size="1">
          <bitfield caption="RX Buffer Clear" mask="0x04" name="RXBCLR"/>
          <bitfield caption="RX Buffer Finish" mask="0x02" name="RXBF"/>
          <bitfield caption="RX Buffer Path B select signal" mask="0x01" name="RXBPB"/>
        </register>
        <register caption="Rx CRC Init value (16-bit RXCI) high byte for data path A" name="RXCIHA" offset="0x0141" size="1" mask="0xFF"/>
        <register caption="Rx CRC Init value (16-bit RXCI) high byte for data path B" name="RXCIHB" offset="0x0137" size="1" mask="0xFF"/>
        <register caption="Rx CRC Init value (16-bit RXCI) low byte for data path A" name="RXCILA" offset="0x0140" size="1" mask="0xFF"/>
        <register caption="Rx CRC Init value (16-bit RXCI) low byte for data path B" name="RXCILB" offset="0x0136" size="1" mask="0xFF"/>
        <register caption="Rx CRC polynomial (15 bit RXCPA) high byte for data path A" name="RXCPHA" offset="0x0143" size="1" mask="0xFF"/>
        <register caption="Rx CRC polynomial (15 bit RXCPB) high byte for data path B" name="RXCPHB" offset="0x0139" size="1" mask="0xFF"/>
        <register caption="Rx CRC polynomial low byte for data path A" name="RXCPLA" offset="0x0142" size="1" mask="0xFE"/>
        <register caption="Rx CRC polynomial low byte for data path B" name="RXCPLB" offset="0x0138" size="1" mask="0xFE"/>
        <register caption="Rx CRC result register high byte for data path A" name="RXCRHA" offset="0x013E" size="1" mask="0xFF"/>
        <register caption="Rx CRC result register high byte for data path B" name="RXCRHB" offset="0x0134" size="1" mask="0xFF"/>
        <register caption="Rx CRC result register low byte for data path A" name="RXCRLA" offset="0x013D" size="1" mask="0xFF"/>
        <register caption="Rx CRC result register low byte for data path B" name="RXCRLB" offset="0x0133" size="1" mask="0xFF"/>
        <register caption="Rx CRC skip bit number for data path A" name="RXCSBA" offset="0x013F" size="1" mask="0xFF"/>
        <register caption="Rx CRC skip bit number for data path B" name="RXCSBB" offset="0x0135" size="1" mask="0xFF"/>
        <register caption="Rx data shift register for data path A" name="RXDSA" offset="0x0144" size="1" mask="0xFF"/>
        <register caption="Rx data shift register for data path B" name="RXDSB" offset="0x013A" size="1" mask="0xFF"/>
        <register caption="Rx data telegram length register high byte for data path A" name="RXTLHA" offset="0x013C" size="1">
          <bitfield caption="RXTL (Receive Telegram Length) register High byte for data path A bit 3" mask="0x08" name="RXTLHA3"/>
          <bitfield caption="RXTL (Receive Telegram Length) register High byte for data path A bit 2" mask="0x04" name="RXTLHA2"/>
          <bitfield caption="RXTL (Receive Telegram Length) register High byte for data path A bit 1" mask="0x02" name="RXTLHA1"/>
          <bitfield caption="RXTL (Receive Telegram Length) register High byte for data path A bit 0" mask="0x01" name="RXTLHA0"/>
        </register>
        <register caption="Rx data telegram length register high byte for data path B" name="RXTLHB" offset="0x0132" size="1">
          <bitfield caption="RXTL (Receive Telegram Length) register High byte for data path B bit 3" mask="0x08" name="RXTLHB3"/>
          <bitfield caption="RXTL (Receive Telegram Length) register High byte for data path B bit 2" mask="0x04" name="RXTLHB2"/>
          <bitfield caption="RXTL (Receive Telegram Length) register High byte for data path B bit 1" mask="0x02" name="RXTLHB1"/>
          <bitfield caption="RXTL (Receive Telegram Length) register High byte for data path B bit 0" mask="0x01" name="RXTLHB0"/>
        </register>
        <register caption="Rx data telegram length register low byte for data path A" name="RXTLLA" offset="0x013B" size="1" mask="0xFF"/>
        <register caption="Rx data telegram length register low byte for data path B" name="RXTLLB" offset="0x0131" size="1" mask="0xFF"/>
      </register-group>
      <value-group caption="" name="RXBUF_CRC_LENGTH">
        <value caption="CRC 4-bit" name="VAL_0x00" value="0x00"/>
        <value caption="CRC 8-bit" name="VAL_0x01" value="0x01"/>
        <value caption="CRC 16-bit" name="VAL_0x02" value="0x02"/>
      </value-group>
    </module>
    <module caption="" name="RXDSP">
      <register-group caption="" name="RXDSP">
        <register caption="End Of Telegram Conditions for path A" name="EOTCA" offset="0x0055" size="1">
          <bitfield caption="End Of Telegram on path B Fail Enable" mask="0x80" name="EOTBFE"/>
          <bitfield caption="RSSI Range Fail Enable on path A" mask="0x40" name="RRFEA"/>
          <bitfield caption="Telegram Length Reached Enable on path A" mask="0x20" name="TELREA"/>
          <bitfield caption="Time-Out Fail Enable on path A" mask="0x10" name="TMOFEA"/>
          <bitfield caption="MANchester Coding Failed Enable for path A" mask="0x08" name="MANFEA"/>
          <bitfield caption="SYmbol Timing check Failed Enable for path A" mask="0x04" name="SYTFEA"/>
          <bitfield caption="AMPlitude Failed Enable for path A" mask="0x02" name="AMPFEA"/>
          <bitfield caption="CARrier check Failed Enable for path A" mask="0x01" name="CARFEA"/>
        </register>
        <register caption="End Of Telegram Conditions for path B" name="EOTCB" offset="0x0057" size="1">
          <bitfield caption="End Of Telegram on path B Fail Enable" mask="0x80" name="EOTAFE"/>
          <bitfield caption="RSSI Range Fail Enable on path B" mask="0x40" name="RRFEB"/>
          <bitfield caption="Telegram Length Reached Enable on path B" mask="0x20" name="TELREB"/>
          <bitfield caption="Time-Out Fail Enable on path B" mask="0x10" name="TMOFEB"/>
          <bitfield caption="MANchester Coding Failed Enable for path B" mask="0x08" name="MANFEB"/>
          <bitfield caption="SYmbol Timing check Failed Enable for path B" mask="0x04" name="SYTFEB"/>
          <bitfield caption="AMPlitude Failed Enable for path B" mask="0x02" name="AMPFEB"/>
          <bitfield caption="CARrier check Failed Enable for path B" mask="0x01" name="CARFEB"/>
        </register>
        <register caption="End Of Telegram Status on path A" name="EOTSA" offset="0x0054" size="1">
          <bitfield caption="End Of Telegram on path B Flag" mask="0x80" name="EOTBF"/>
          <bitfield caption="RSSI Range Fail on path A" mask="0x40" name="RRFA"/>
          <bitfield caption="Telegram Length Reached on path A" mask="0x20" name="TELRA"/>
          <bitfield caption="Time-Out Fail on path A" mask="0x10" name="TMOFA"/>
          <bitfield caption="MANchester coding Failed on path A" mask="0x08" name="MANFA"/>
          <bitfield caption="SYmbol Timing check Failed on path A" mask="0x04" name="SYTFA"/>
          <bitfield caption="AMPlitude Failed on path A" mask="0x02" name="AMPFA"/>
          <bitfield caption="CARrier check Failed on path A" mask="0x01" name="CARFA"/>
        </register>
        <register caption="End Of Telegram Status on path B" name="EOTSB" offset="0x0056" size="1">
          <bitfield caption="End Of Telegram on path A Flag" mask="0x80" name="EOTAF"/>
          <bitfield caption="RSSI Range Fail on path B" mask="0x40" name="RRFB"/>
          <bitfield caption="Telegram Length Reached on path B" mask="0x20" name="TELRB"/>
          <bitfield caption="Time-Out Fail on path B" mask="0x10" name="TMOFB"/>
          <bitfield caption="MANchester coding Failed on path B" mask="0x08" name="MANFB"/>
          <bitfield caption="SYmbol Timing check Failed on path B" mask="0x04" name="SYTFB"/>
          <bitfield caption="AMPlitude Failed on path B" mask="0x02" name="AMPFB"/>
          <bitfield caption="CARrier check Failed on path B" mask="0x01" name="CARFB"/>
        </register>
        <register caption="Rx DSP control register" name="RDCR" offset="0x0053" size="1">
          <bitfield caption="Rx DSP enable" mask="0x04" name="RDEN"/>
          <bitfield caption="Divided ADC clock enable" mask="0x02" name="ADIVEN"/>
          <bitfield caption="Rx DSP Power Up" mask="0x01" name="RDPU"/>
        </register>
        <register caption="Rx DSP output control" name="RDOCR" offset="0x0099" size="1">
          <bitfield caption="Rx DSP Start bit Is Data for path B" mask="0x40" name="RDSIDB"/>
          <bitfield caption="Rx DSP Start bit Is Data for path A" mask="0x20" name="RDSIDA"/>
          <bitfield caption="Enable Transparent Path B" mask="0x10" name="ETRPB"/>
          <bitfield caption="Enable Transparent Path A" mask="0x08" name="ETRPA"/>
          <bitfield caption="Transparent Mode Data Select" mask="0x06" name="TMDS"/>
        </register>
        <register caption="Rx DSP status interrupt flag register" name="RDSIFR" offset="0x002D" size="1">
          <bitfield caption="Wake Conditions Ok on path B" mask="0x80" name="WCOB"/>
          <bitfield caption="Wake Conditions Ok on path A" mask="0x40" name="WCOA"/>
          <bitfield caption="Start Of Telegram on path B" mask="0x20" name="SOTB"/>
          <bitfield caption="Start Of Telegram on path A" mask="0x10" name="SOTA"/>
          <bitfield caption="End Of Telegram on path B" mask="0x08" name="EOTB"/>
          <bitfield caption="End Of Telegram on path A" mask="0x04" name="EOTA"/>
          <bitfield caption="New Bit on Rx path B" mask="0x02" name="NBITB"/>
          <bitfield caption="New Bit on Rx path A" mask="0x01" name="NBITA"/>
        </register>
        <register caption="Rx DSP status interrupt mask register" name="RDSIMR" offset="0x0098" size="1">
          <bitfield caption="Wake Conditions Ok on path B interrupt mask register" mask="0x80" name="WCOBM"/>
          <bitfield caption="Wake Conditions Ok on path A interrupt mask register" mask="0x40" name="WCOAM"/>
          <bitfield caption="Start Of Telegram on Rx path B interrupt mask register" mask="0x20" name="SOTBM"/>
          <bitfield caption="Start Of Telegram on Rx path A interrupt mask register" mask="0x10" name="SOTAM"/>
          <bitfield caption="End Of Telegram on Rx path B interrupt mask register" mask="0x08" name="EOTBM"/>
          <bitfield caption="End Of Telegram on Rx path A interrupt mask register" mask="0x04" name="EOTAM"/>
          <bitfield caption="New bit on Rx path B interrupt mask register" mask="0x02" name="NBITBM"/>
          <bitfield caption="New bit on Rx path A interrupt mask register" mask="0x01" name="NBITAM"/>
        </register>
        <register caption="Start Of Telegram Conditions for path A" name="SOTCA" offset="0x0094" size="1">
          <bitfield caption="Wake Check OK from path B Ok Enable" mask="0x80" name="WCOBOE"/>
          <bitfield caption="RSSI Range OK Enable for path A" mask="0x40" name="RROEA"/>
          <bitfield caption="Start of Frame IDentifier match Enabled for path A" mask="0x20" name="SFIDEA"/>
          <bitfield caption="Wake Up Pattern match Enabled for path A" mask="0x10" name="WUPEA"/>
          <bitfield caption="Manchester Coding Ok Enabled for path A" mask="0x08" name="MANOEA"/>
          <bitfield caption="Symbol Timing Ok Enabled for path A" mask="0x04" name="SYTOEA"/>
          <bitfield caption="AMPlitude Ok Enabled for path A" mask="0x02" name="AMPOEA"/>
          <bitfield caption="CARrier check Ok Enabled for path A" mask="0x01" name="CAROEA"/>
        </register>
        <register caption="Start Of Telegram Conditions for path B" name="SOTCB" offset="0x0093" size="1">
          <bitfield caption="Wake Check OK from path A Ok Enable" mask="0x80" name="WCOAOE"/>
          <bitfield caption="RSSI Range OK Enable for path B" mask="0x40" name="RROEB"/>
          <bitfield caption="Start of Frame IDentifier match Enabled for path B" mask="0x20" name="SFIDEB"/>
          <bitfield caption="Wake Up Pattern match Enabled for path B" mask="0x10" name="WUPEB"/>
          <bitfield caption="Manchester Coding Ok Enabled for path B" mask="0x08" name="MANOEB"/>
          <bitfield caption="Symbol Timing Ok Enabled for path B" mask="0x04" name="SYTOEB"/>
          <bitfield caption="AMPlitude Ok Enabled for path B" mask="0x02" name="AMPOEB"/>
          <bitfield caption="CARrier check Ok Enabled for path B" mask="0x01" name="CAROEB"/>
        </register>
        <register caption="Start Of Telegram Status for path A" name="SOTSA" offset="0x0092" size="1">
          <bitfield caption="Wake Check Ok on path B Ok" mask="0x80" name="WCOBO"/>
          <bitfield caption="RSSI Range Ok on Path A" mask="0x40" name="RROA"/>
          <bitfield caption="Start of Frame IDentifier matched on path A" mask="0x20" name="SFIDOA"/>
          <bitfield caption="Wake Up Pattern matched on path A" mask="0x10" name="WUPOA"/>
          <bitfield caption="Manchester Coding Ok on path A" mask="0x08" name="MANOA"/>
          <bitfield caption="Symbol Timing Ok on path A" mask="0x04" name="SYTOA"/>
          <bitfield caption="AMPlitude Ok on path A" mask="0x02" name="AMPOA"/>
          <bitfield caption="CARrier check Ok on path A" mask="0x01" name="CAROA"/>
        </register>
        <register caption="Start Of Telegram Status for path B" name="SOTSB" offset="0x0091" size="1">
          <bitfield caption="Wake Check Ok on path A Ok" mask="0x80" name="WCOAO"/>
          <bitfield caption="RSSI Range Ok on Path B" mask="0x40" name="RROB"/>
          <bitfield caption="Start of Frame IDentifier matched on path B" mask="0x20" name="SFIDOB"/>
          <bitfield caption="Wake Up Pattern matched on path B" mask="0x10" name="WUPOB"/>
          <bitfield caption="Manchester Coding Ok on path B" mask="0x08" name="MANOB"/>
          <bitfield caption="Symbol Timing Ok on path B" mask="0x04" name="SYTOB"/>
          <bitfield caption="AMPlitude Ok on path B" mask="0x02" name="AMPOB"/>
          <bitfield caption="CARrier check Ok on path B" mask="0x01" name="CAROB"/>
        </register>
        <register caption="Telegram Status Register on Path A" name="TESRA" offset="0x0096" size="1">
          <bitfield caption="End of Telegram Location on path A" mask="0x06" name="EOTLA" values="SSM_EOT_LOCATION"/>
          <bitfield caption="Cyclic Redundancy Check Ok on path A" mask="0x01" name="CRCOA"/>
        </register>
        <register caption="Telegram Status Register on Path B" name="TESRB" offset="0x0095" size="1">
          <bitfield caption="End of Telegram Location on path B" mask="0x06" name="EOTLB" values="SSM_EOT_LOCATION"/>
          <bitfield caption="Cyclic Redundancy Check Ok on path B" mask="0x01" name="CRCOB"/>
        </register>
      </register-group>
      <value-group caption="" name="SSM_EOT_LOCATION">
        <value caption="No EOT" name="VAL_0x00" value="0x00"/>
        <value caption="Before WCO" name="VAL_0x01" value="0x01"/>
        <value caption="Between WCO and SOT" name="VAL_0x02" value="0x02"/>
        <value caption="After SOT" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="SFIFO">
      <register-group caption="" name="SFIFO">
        <register caption="Support FIFO Configuration Register" name="SFC" offset="0x00E1" size="1">
          <bitfield caption="Support FIFO Direct Read Access Operational Mode" mask="0x80" name="SFDRA"/>
          <bitfield caption="Support FIFO Fill-Level Configuration" mask="0x1F" name="SFFLC"/>
        </register>
        <register caption="Support FIFO Data Register" name="SFD" offset="0x00DF" size="1" mask="0xFF"/>
        <register caption="Support FIFO Interrupt Mask Register" name="SFI" offset="0x00E0" size="1">
          <bitfield caption="Support FIFO Error Interrupt Mask" mask="0x02" name="SFERIM"/>
          <bitfield caption="Support FIFO Fill-level Interrupt Mask" mask="0x01" name="SFFLIM"/>
        </register>
        <register caption="Support FIFO Fill Level Register" name="SFL" offset="0x00DC" size="1">
          <bitfield caption="Support FIFO Clear" mask="0x80" name="SFCLR"/>
          <bitfield caption="Support FIFO Fill Level Status" mask="0x1F" name="SFFLS"/>
        </register>
        <register caption="Support FIFO Read Pointer" name="SFRP" offset="0x00DE" size="1">
          <bitfield caption="Support FIFO Read Pointer" mask="0x1F" name="SFRP"/>
        </register>
        <register caption="Support FIFO Status Register" name="SFS" offset="0x00DB" size="1">
          <bitfield caption="Support FIFO Overflow Flag" mask="0x04" name="SFOFL"/>
          <bitfield caption="Support FIFO Underflow Flag" mask="0x02" name="SFUFL"/>
          <bitfield caption="Support FIFO Fill-Level Reached Status Flag" mask="0x01" name="SFFLRF"/>
        </register>
        <register caption="Support FIFO Write Pointer" name="SFWP" offset="0x00DD" size="1">
          <bitfield caption="Support FIFO Write Pointer" mask="0x1F" name="SFWP"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="SPI">
      <register-group caption="" name="SPI">
        <register caption="SPI Data Register" name="SPDR" offset="0x4E" size="1" mask="0xFF"/>
        <register caption="SPI Status Register" name="SPSR" offset="0x4D" size="1">
          <bitfield caption="SPI Interrupt Flag" mask="0x80" name="SPIF"/>
          <bitfield caption="Tx Buffer Interrupt Flag" mask="0x20" name="TXIF"/>
          <bitfield caption="Rx Buffer Interrupt Flag" mask="0x10" name="RXIF"/>
          <bitfield caption="Double SPI Speed Bit" mask="0x01" name="SPI2X"/>
        </register>
        <register caption="SPI Control Register" name="SPCR" offset="0x4C" size="1">
          <bitfield caption="SPI Interrupt Enable" mask="0x80" name="SPIE"/>
          <bitfield caption="SPI Enable" mask="0x40" name="SPE"/>
          <bitfield caption="Data Order" mask="0x20" name="DORD"/>
          <bitfield caption="Master/Slave Select" mask="0x10" name="MSTR"/>
          <bitfield caption="Clock polarity" mask="0x08" name="CPOL"/>
          <bitfield caption="Clock Phase" mask="0x04" name="CPHA"/>
          <bitfield caption="SPI Clock Rate Selects" mask="0x03" name="SPR" values="COMM_SCK_RATE_3BIT"/>
        </register>
        <register caption="SPI FIFO Fill Status Register" name="SFFR" offset="0x157" size="1">
          <bitfield caption="SPI Tx Buffer Clear" mask="0x80" name="TFC"/>
          <bitfield caption="SPI Transmit Buffer Fill Level" mask="0x70" name="TFL"/>
          <bitfield caption="SPI Rx Buffer Clear" mask="0x08" name="RFC"/>
          <bitfield caption="SPI Receive Buffer Fill Level" mask="0x07" name="RFL"/>
        </register>
        <register caption="SPI FIFO Interrupt Register" name="SFIR" offset="0x158" size="1">
          <bitfield caption="SPI Tx Buffer Interrupt Enable" mask="0x80" name="STIE"/>
          <bitfield caption="SPI Transmit Buffer Interrupt Level" mask="0x70" name="TIL"/>
          <bitfield caption="SPI Rx Buffer Interrupt Enable" mask="0x08" name="SRIE"/>
          <bitfield caption="SPI Receive Buffer Interrupt Level" mask="0x07" name="RIL"/>
        </register>
      </register-group>
      <value-group caption="" name="COMM_SCK_RATE_3BIT">
        <value caption="clkio/4" name="VAL_0x00" value="0x00"/>
        <value caption="clkio/16" name="VAL_0x01" value="0x01"/>
        <value caption="clkio/64" name="VAL_0x02" value="0x02"/>
        <value caption="clkio/128" name="VAL_0x03" value="0x03"/>
        <value caption="clkio/2" name="VAL_0x04" value="0x04"/>
        <value caption="clkio/8" name="VAL_0x05" value="0x05"/>
        <value caption="clkio/32" name="VAL_0x06" value="0x06"/>
        <value caption="clkio/64" name="VAL_0x07" value="0x07"/>
      </value-group>
    </module>
    <module caption="" name="SSM">
      <register-group caption="" name="SSM">
        <register caption="End Of Telegram Conditions 1 for Path A" name="EOTC1A" offset="0x00F5" size="1">
          <bitfield caption="End Of Telegram on Path B Fail Enable" mask="0x80" name="EOTBFE1"/>
          <bitfield caption="RSSI Range Fail Enable on Path A" mask="0x40" name="RRFEA1"/>
          <bitfield caption="Telegram Length Reached Enable on Path A" mask="0x20" name="TELREA1"/>
          <bitfield caption="Time-Out Fail Enable on Path A" mask="0x10" name="TMOFEA1"/>
          <bitfield caption="MANchester Coding Failed Enable for Path A" mask="0x08" name="MANFEA1"/>
          <bitfield caption="SYmbol Timing check Failed Enable for Path A" mask="0x04" name="SYTFEA1"/>
          <bitfield caption="AMPlitude Failed Enable for path A" mask="0x02" name="AMPFEA1"/>
          <bitfield caption="CARrier check Failed Enable for path A" mask="0x01" name="CARFEA1"/>
        </register>
        <register caption="End Of Telegram Conditions 1 for Path B" name="EOTC1B" offset="0x00F8" size="1">
          <bitfield caption="End Of Telegram on Path B Fail Enable" mask="0x80" name="EOTAFE1"/>
          <bitfield caption="RSSI Range Fail Enable on Path B" mask="0x40" name="RRFEB1"/>
          <bitfield caption="Telegram Length Reached Enable on Path B" mask="0x20" name="TELREB1"/>
          <bitfield caption="Time-Out Fail Enable on Path B" mask="0x10" name="TMOFEB1"/>
          <bitfield caption="MANchester Coding Failed Enable for Path B" mask="0x08" name="MANFEB1"/>
          <bitfield caption="SYmbol Timing check Failed Enable for Path B" mask="0x04" name="SYTFEB1"/>
          <bitfield caption="AMPlitude Failed Enable for path B" mask="0x02" name="AMPFEB1"/>
          <bitfield caption="CARrier check Failed Enable for path B" mask="0x01" name="CARFEB1"/>
        </register>
        <register caption="End Of Telegram Conditions 2 for Path A" name="EOTC2A" offset="0x00F6" size="1">
          <bitfield caption="End Of Telegram on Path B Fail Enable" mask="0x80" name="EOTBFE2"/>
          <bitfield caption="RSSI Range Fail Enable on Path A" mask="0x40" name="RRFEA2"/>
          <bitfield caption="Telegram Length Reached Enable on Path A" mask="0x20" name="TELREA2"/>
          <bitfield caption="Time-Out Fail Enable on Path A" mask="0x10" name="TMOFEA2"/>
          <bitfield caption="MANchester Coding Failed Enable for Path A" mask="0x08" name="MANFEA2"/>
          <bitfield caption="SYmbol Timing check Failed Enable for Path A" mask="0x04" name="SYTFEA2"/>
          <bitfield caption="AMPlitude Failed Enable for path A" mask="0x02" name="AMPFEA2"/>
          <bitfield caption="CARrier check Failed Enable for path A" mask="0x01" name="CARFEA2"/>
        </register>
        <register caption="End Of Telegram Conditions 2 for Path B" name="EOTC2B" offset="0x00F9" size="1">
          <bitfield caption="End Of Telegram on Path B Fail Enable" mask="0x80" name="EOTAFE2"/>
          <bitfield caption="RSSI Range Fail Enable on Path B" mask="0x40" name="RRFEB2"/>
          <bitfield caption="Telegram Length Reached Enable on Path B" mask="0x20" name="TELREB2"/>
          <bitfield caption="Time-Out Fail Enable on Path B" mask="0x10" name="TMOFEB2"/>
          <bitfield caption="MANchester Coding Failed Enable for Path B" mask="0x08" name="MANFEB2"/>
          <bitfield caption="SYmbol Timing check Failed Enable for Path B" mask="0x04" name="SYTFEB2"/>
          <bitfield caption="AMPlitude Failed Enable for path B" mask="0x02" name="AMPFEB2"/>
          <bitfield caption="CARrier check Failed Enable for path B" mask="0x01" name="CARFEB2"/>
        </register>
        <register caption="End Of Telegram Conditions 3 for Path A" name="EOTC3A" offset="0x00F7" size="1">
          <bitfield caption="End Of Telegram on Path B Fail Enable" mask="0x80" name="EOTBFE3"/>
          <bitfield caption="RSSI Range Fail Enable on Path A" mask="0x40" name="RRFEA3"/>
          <bitfield caption="Telegram Length Reached Enable on Path A" mask="0x20" name="TELREA3"/>
          <bitfield caption="Time-Out Fail Enable on Path A" mask="0x10" name="TMOFEA3"/>
          <bitfield caption="MANchester Coding Failed Enable for Path A" mask="0x08" name="MANFEA3"/>
          <bitfield caption="SYmbol Timing check Failed Enable for Path A" mask="0x04" name="SYTFEA3"/>
          <bitfield caption="AMPlitude Failed Enable for path A" mask="0x02" name="AMPFEA3"/>
          <bitfield caption="CARrier check Failed Enable for path A" mask="0x01" name="CARFEA3"/>
        </register>
        <register caption="End Of Telegram Conditions 3 for Path B" name="EOTC3B" offset="0x00FA" size="1">
          <bitfield caption="End Of Telegram on Path B Fail Enable" mask="0x80" name="EOTAFE3"/>
          <bitfield caption="RSSI Range Fail Enable on Path B" mask="0x40" name="RRFEB3"/>
          <bitfield caption="Telegram Length Reached Enable on Path B" mask="0x20" name="TELREB3"/>
          <bitfield caption="Time-Out Fail Enable on Path B" mask="0x10" name="TMOFEB3"/>
          <bitfield caption="MANchester Coding Failed Enable for Path B" mask="0x08" name="MANFEB3"/>
          <bitfield caption="SYmbol Timing check Failed Enable for Path B" mask="0x04" name="SYTFEB3"/>
          <bitfield caption="AMPlitude Failed Enable for path B" mask="0x02" name="AMPFEB3"/>
          <bitfield caption="CARrier check Failed Enable for path B" mask="0x01" name="CARFEB3"/>
        </register>
        <register caption="Get Telegram Control Register" name="GTCR" offset="0x00F0" size="1">
          <bitfield caption="Intermittent WUP Mode Path B" mask="0x80" name="IWUPB"/>
          <bitfield caption="Demodulator Automatic Restart on Path B" mask="0x40" name="DARB"/>
          <bitfield caption="Gap Mode Path B" mask="0x20" name="GAPMB"/>
          <bitfield caption="Rx Telegram End Handling Path B" mask="0x10" name="RXTEHB"/>
          <bitfield caption="Intermittent WUP Mode Path A" mask="0x08" name="IWUPA"/>
          <bitfield caption="Demodulator Automatic Restart on Path A" mask="0x04" name="DARA"/>
          <bitfield caption="Gap Mode Path A" mask="0x02" name="GAPMA"/>
          <bitfield caption="Rx Telegram End Handling Path A" mask="0x01" name="RXTEHA"/>
        </register>
        <register caption="Master State Machine Control Register 1" name="MSMCR1" offset="0x00EC" size="1">
          <bitfield caption="Master State Machine SubState Machine Select 0" mask="0x0F" name="MSMSM0" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine SubState Machine Select 1" mask="0xF0" name="MSMSM1" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 2" name="MSMCR2" offset="0x00ED" size="1">
          <bitfield caption="Master State Machine SubState Machine Select 2" mask="0x0F" name="MSMSM2" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine SubState Machine Select 3" mask="0xF0" name="MSMSM3" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 3" name="MSMCR3" offset="0x00EE" size="1">
          <bitfield caption="Master State Machine SubState Machine Select 4" mask="0x0F" name="MSMSM4" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine SubState Machine Select 5" mask="0xF0" name="MSMSM5" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine Control Register 4" name="MSMCR4" offset="0x00EF" size="1">
          <bitfield caption="Master State Machine SubState Machine Select 6" mask="0x0F" name="MSMSM6" values="SSM_SUB_STATE_MACHINE"/>
          <bitfield caption="Master State Machine SubState Machine Select 7" mask="0xF0" name="MSMSM7" values="SSM_SUB_STATE_MACHINE"/>
        </register>
        <register caption="Master State Machine state register" name="MSMSTR" offset="0x00E9" size="1">
          <bitfield caption="Sequencer State Machine Master State" mask="0x1F" name="SSMMST"/>
        </register>
        <register caption="Start Of Telegram Conditions 1 for Path A" name="SOTC1A" offset="0x00F1" size="1">
          <bitfield caption="Wake Check OK from path B Ok Enable" mask="0x80" name="WCOBOE1"/>
          <bitfield caption="RSSI Range OK Enable for path A" mask="0x40" name="RROEA1"/>
          <bitfield caption="Start of Frame IDentifier match Enabled for path A" mask="0x20" name="SFIDEA1"/>
          <bitfield caption="Wake Up Pattern match Enabled for path A" mask="0x10" name="WUPEA1"/>
          <bitfield caption="Manchester Coding Ok Enabled for path A" mask="0x08" name="MANOEA1"/>
          <bitfield caption="Symbol Timing Ok Enabled for path A" mask="0x04" name="SYTOEA1"/>
          <bitfield caption="AMPlitude Ok Enabled for path A" mask="0x02" name="AMPOEA1"/>
          <bitfield caption="CARrier check Ok Enabled for path A" mask="0x01" name="CAROEA1"/>
        </register>
        <register caption="Start Of Telegram Conditions 1 for Path B" name="SOTC1B" offset="0x00F3" size="1">
          <bitfield caption="Wake Check Ok on path B Ok" mask="0x80" name="WCOAOE1"/>
          <bitfield caption="RSSI Range Ok on Path A" mask="0x40" name="RROEB1"/>
          <bitfield caption="Start of Frame IDentifier match Enabled for path B" mask="0x20" name="SFIDEB1"/>
          <bitfield caption="Wake Up Pattern match Enabled for path B" mask="0x10" name="WUPEB1"/>
          <bitfield caption="Manchester Coding Ok Enabled for path B" mask="0x08" name="MANOEB1"/>
          <bitfield caption="Symbol Timing Ok Enabled for path B" mask="0x04" name="SYTOEB1"/>
          <bitfield caption="AMPlitude Ok Enabled for path B" mask="0x02" name="AMPOEB1"/>
          <bitfield caption="CARrier check Ok Enabled for path B" mask="0x01" name="CAROEB1"/>
        </register>
        <register caption="Start Of Telegram Conditions 2 for Path A" name="SOTC2A" offset="0x00F2" size="1">
          <bitfield caption="Wake Check OK from path B Ok Enable" mask="0x80" name="WCOBOE2"/>
          <bitfield caption="RSSI Range OK Enable for path A" mask="0x40" name="RROEA2"/>
          <bitfield caption="Start of Frame IDentifier match Enabled for path A" mask="0x20" name="SFIDEA2"/>
          <bitfield caption="Wake Up Pattern match Enabled for path A" mask="0x10" name="WUPEA2"/>
          <bitfield caption="Manchester Coding Ok Enabled for path A" mask="0x08" name="MANOEA2"/>
          <bitfield caption="Symbol Timing Ok Enabled for path A" mask="0x04" name="SYTOEA2"/>
          <bitfield caption="AMPlitude Ok Enabled for path A" mask="0x02" name="AMPOEA2"/>
          <bitfield caption="CARrier check Ok Enabled for path A" mask="0x01" name="CAROEA2"/>
        </register>
        <register caption="Start Of Telegram Conditions 2 for Path B" name="SOTC2B" offset="0x00F4" size="1">
          <bitfield caption="Wake Check Ok on path B Ok" mask="0x80" name="WCOAOE2"/>
          <bitfield caption="RSSI Range Ok on Path A" mask="0x40" name="RROEB2"/>
          <bitfield caption="Start of Frame IDentifier match Enabled for path B" mask="0x20" name="SFIDEB2"/>
          <bitfield caption="Wake Up Pattern match Enabled for path B" mask="0x10" name="WUPEB2"/>
          <bitfield caption="Manchester Coding Ok Enabled for path B" mask="0x08" name="MANOEB2"/>
          <bitfield caption="Symbol Timing Ok Enabled for path B" mask="0x04" name="SYTOEB2"/>
          <bitfield caption="AMPlitude Ok Enabled for path B" mask="0x02" name="AMPOEB2"/>
          <bitfield caption="CARrier check Ok Enabled for path B" mask="0x01" name="CAROEB2"/>
        </register>
        <register caption="Start Of Telegram Time Out for path A" name="SOTTOA" offset="0x00FD" size="1" mask="0xFF"/>
        <register caption="Start Of Telegram Time Out for path B" name="SOTTOB" offset="0x00FE" size="1" mask="0xFF"/>
        <register caption="SSM Control Register" name="SSMCR" offset="0x00E2" size="1">
          <bitfield caption="Sequencer State Machine Enable Transparent Path B" mask="0x80" name="SETRPB"/>
          <bitfield caption="Sequencer State Machine Enable Transparent Path A" mask="0x40" name="SETRPA"/>
          <bitfield caption="Sequencer State Machine Tx Ask-Shaping Enable" mask="0x20" name="SSMTAE"/>
          <bitfield caption="Sequencer State Machine PV Enable" mask="0x10" name="SSMPVE"/>
          <bitfield caption="Sequencer State Machine Tx Preemphasis Enable" mask="0x08" name="SSMTPE"/>
          <bitfield caption="Sequencer State Machine Tx Gauss Enable" mask="0x04" name="SSMTGE"/>
          <bitfield caption="Sequencer State Machine Temperature Measurement" mask="0x02" name="SSMTM"/>
          <bitfield caption="Sequencer State Machine Tx" mask="0x01" name="SSMTX"/>
        </register>
        <register caption="SSM Filter Bandwidth Register" name="SSMFBR" offset="0x00E4" size="1">
          <bitfield caption="Sequencer State Machine PLL Lock Delay Time" mask="0x20" name="SSMPLDT"/>
          <bitfield caption="Sequencer State Machine Half Antennadamping Delay Time" mask="0x10" name="SSMHADT"/>
          <bitfield caption="Sequencer State Machine Double Filter Delay Time" mask="0x08" name="SSMDFDT"/>
          <bitfield caption="Sequencer State Machine Filter Delay" mask="0x07" name="SSMFID"/>
        </register>
        <register caption="SSM Flow Control Register" name="SSMFCR" offset="0x00FF" size="1">
          <bitfield caption="Sequencer State Machine ID Scan Fail" mask="0x02" name="SSMIDSF"/>
          <bitfield caption="Sequencer State Machine ID Scan OK" mask="0x01" name="SSMIDSO"/>
        </register>
        <register caption="SSM Interrupt Flag Register" name="SSMIFR" offset="0x00E7" size="1">
          <bitfield caption="Sequencer State Machine Interrupt Flag" mask="0x01" name="SSMIF"/>
        </register>
        <register caption="SSM interrupt mask register" name="SSMIMR" offset="0x00E8" size="1">
          <bitfield caption="Sequencer State Machine Interrupt Mask" mask="0x01" name="SSMIM"/>
        </register>
        <register caption="SSM Rx Control Register" name="SSMRCR" offset="0x00E3" size="1">
          <bitfield caption="Sequencer State Machine Transparent Mode Output Enable" mask="0x80" name="SSMTMOE"/>
          <bitfield caption="Sequencer State Machine ID Scan Enable" mask="0x40" name="SSMIDSE"/>
          <bitfield caption="Sequencer State Machine IF Amplifier Enable" mask="0x20" name="SSMIFA"/>
          <bitfield caption="Sequencer State Machine Path Valid After SOT" mask="0x10" name="SSMPVS"/>
          <bitfield caption="Sequencer State Machine Antenna Damping Disable Path B" mask="0x08" name="SSMADB"/>
          <bitfield caption="Sequencer State Machine Antenna Damping Disable Path A" mask="0x04" name="SSMADA"/>
          <bitfield caption="Sequencer State Machine Path B" mask="0x02" name="SSMPB"/>
          <bitfield caption="Sequencer State Machine Path A" mask="0x01" name="SSMPA"/>
        </register>
        <register caption="SSM Run Register" name="SSMRR" offset="0x00E5" size="1">
          <bitfield caption="Sequencer State Machine Stop" mask="0x02" name="SSMST"/>
          <bitfield caption="Sequencer State Machine Run" mask="0x01" name="SSMR"/>
        </register>
        <register caption="SSM Status Register" name="SSMSR" offset="0x00E6" size="1">
          <bitfield caption="Sequencer State Machine Error" mask="0x80" name="SSMERR"/>
          <bitfield caption="Sequencer State Machine Error State Machine" mask="0x0F" name="SSMESM"/>
        </register>
        <register caption="SSM State Register" name="SSMSTR" offset="0x00EA" size="1">
          <bitfield caption="Sequencer State Machine State A" mask="0x3F" name="SSMSTA"/>
        </register>
        <register caption="SSM extended State Register" name="SSMXSR" offset="0x00EB" size="1">
          <bitfield caption="Sequencer State Machine State B" mask="0x3F" name="SSMSTB"/>
        </register>
        <register caption="Wait check ok time out for path A" name="WCOTOA" offset="0x00FB" size="1" mask="0xFF"/>
        <register caption="Wait check ok time out for path B" name="WCOTOB" offset="0x00FC" size="1" mask="0xFF"/>
      </register-group>
      <value-group caption="" name="SSM_SUB_STATE_MACHINE">
        <value caption="None/Stop" name="VAL_0x00" value="0x00"/>
        <value caption="PLL en" name="VAL_0x01" value="0x01"/>
        <value caption="PLL lock" name="VAL_0x02" value="0x02"/>
        <value caption="RX DSP enable" name="VAL_0x03" value="0x03"/>
        <value caption="RX DSP disable" name="VAL_0x04" value="0x04"/>
        <value caption="TX DSP enable" name="VAL_0x05" value="0x05"/>
        <value caption="TX DSP disable" name="VAL_0x06" value="0x06"/>
        <value caption="RX to TX" name="VAL_0x07" value="0x07"/>
        <value caption="TX to RX" name="VAL_0x08" value="0x08"/>
        <value caption="Get telegram" name="VAL_0x09" value="0x09"/>
        <value caption="Send telegram" name="VAL_0x0A" value="0x0A"/>
        <value caption="Shut down" name="VAL_0x0B" value="0x0B"/>
        <value caption="VCO Tuning" name="VAL_0x0C" value="0x0C"/>
        <value caption="Antenna Tuning" name="VAL_0x0D" value="0x0D"/>
      </value-group>
    </module>
    <module caption="" name="SUP">
      <register-group caption="" name="SUP">
        <register caption="Calibration ready signature" name="CALRDY" offset="0x00D0" size="1" mask="0xFF"/>
        <register caption="Supply calibration register 2" name="SUPCA2" offset="0x00CD" size="1">
          <bitfield caption="Band Gap Calibration" mask="0x0F" name="BGCAL"/>
        </register>
        <register caption="Supply calibration register 3" name="SUPCA3" offset="0x00CE" size="1">
          <bitfield caption="DVCC Reset Threshold Calibration bit 6" mask="0x40" name="DCAL6"/>
          <bitfield caption="DVCC Reset Threshold Calibration bit 5" mask="0x20" name="DCAL5"/>
          <bitfield caption="DVCC Reset Threshold Calibration bit 4" mask="0x10" name="DCAL4"/>
          <bitfield caption="AVCC Reset Threshold Calibration bit 7" mask="0x08" name="ACAL7"/>
          <bitfield caption="AVCC Reset Threshold Calibration bit 6" mask="0x04" name="ACAL6"/>
          <bitfield caption="AVCC Reset Threshold Calibration bit 5" mask="0x02" name="ACAL5"/>
          <bitfield caption="AVCC Reset Threshold Calibration bit 4" mask="0x01" name="ACAL4"/>
        </register>
        <register caption="Supply calibration register 4" name="SUPCA4" offset="0x00CF" size="1">
          <bitfield caption="DVCC Regulator Output Voltage Calibration bit 3" mask="0x80" name="DCAL3"/>
          <bitfield caption="DVCC Regulator Output Voltage Calibration bit 2" mask="0x40" name="DCAL2"/>
          <bitfield caption="DVCC Regulator Output Voltage Calibration bit 1" mask="0x20" name="DCAL1"/>
          <bitfield caption="DVCC Regulator Output Voltage Calibration bit 0" mask="0x10" name="DCAL0"/>
          <bitfield caption="AVCC Regulator Output Voltage Calibration bit 3" mask="0x08" name="ACAL3"/>
          <bitfield caption="AVCC Regulator Output Voltage Calibration bit 2" mask="0x04" name="ACAL2"/>
          <bitfield caption="AVCC Regulator Output Voltage Calibration bit 1" mask="0x02" name="ACAL1"/>
          <bitfield caption="AVCC Regulator Output Voltage Calibration bit 0" mask="0x01" name="ACAL0"/>
        </register>
        <register caption="Supply Control Register" name="SUPCR" offset="0x00CB" size="1">
          <bitfield caption="AVCC Double Internal Current" mask="0x40" name="AVDIC"/>
          <bitfield caption="AVCC Enable" mask="0x20" name="AVEN"/>
          <bitfield caption="DVCC Disable" mask="0x10" name="DVDIS"/>
          <bitfield caption="Power amplifier Voltage supply Enable" mask="0x04" name="PVEN"/>
          <bitfield caption="AVCC Low Interrupt Mask Bit" mask="0x02" name="AVCCLM"/>
          <bitfield caption="AVCC Reset Interrupt Mask Bit" mask="0x01" name="AVCCRM"/>
        </register>
        <register caption="Supply Interrupt Flag Register" name="SUPFR" offset="0x00CA" size="1">
          <bitfield caption="AVCC low interrupt flag" mask="0x02" name="AVCCLF"/>
          <bitfield caption="AVCC reset interrupt flag" mask="0x01" name="AVCCRF"/>
        </register>
        <register caption="Voltage Monitor Calibration register" name="VMCAL" offset="0x00D1" size="1">
          <bitfield caption="Voltage monitor calibration" mask="0x07" name="VMCAL"/>
        </register>
        <register caption="Voltage Monitor Control and Status Register" name="VMCSR" offset="0x004A" size="1">
          <bitfield caption="Voltage Monitor Flag" mask="0x20" name="VMF"/>
          <bitfield caption="Voltage Monitor Interrupt Mask" mask="0x10" name="VMIM"/>
          <bitfield caption="Voltage Monitor Level Select" mask="0x0F" name="VMLS"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="SYMCH">
      <register-group caption="" name="SYMCH">
        <register caption="Symbol check configuration for data path A" name="SYCA" offset="0x009E" size="1">
          <bitfield caption="Symbol timing limit for path A" mask="0xF0" name="SYTLA"/>
          <bitfield caption="Symbol Check check size for data path A" mask="0x0F" name="SYCSA"/>
        </register>
        <register caption="Symbol check configuration for data path B" name="SYCB" offset="0x009D" size="1">
          <bitfield caption="Symbol timing limit for path B" mask="0xF0" name="SYTLB"/>
          <bitfield caption="Symbol Check check size for data path B" mask="0x0F" name="SYCSB"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="TEMPER">
      <register-group caption="" name="TEMPER">
        <register caption="Temperature High byte" name="TEMPH" offset="0x009C" size="1" mask="0xFF"/>
        <register caption="Temperature Low byte" name="TEMPL" offset="0x009B" size="1" mask="0xFF"/>
      </register-group>
    </module>
    <module caption="" name="TIMER0_WDT">
      <register-group caption="" name="TIMER0_WDT">
        <register caption="Timer0 Control Register" name="T0CR" offset="0x0030" size="1">
          <bitfield caption="Timer 0 Prescaler Reset" mask="0x10" name="T0PR"/>
          <bitfield caption="Timer 0 Interrupt Enable" mask="0x08" name="T0IE"/>
          <bitfield caption="Timer 0 Prescaler Select" mask="0x07" name="T0PS"/>
        </register>
        <register caption="Timer0 Interrupt Flag Register" name="T0IFR" offset="0x004F" size="1">
          <bitfield caption="Timer0 Flag" mask="0x01" name="T0F"/>
        </register>
        <register caption="Watchdog Timer0 control Register" name="WDTCR" offset="0x006E" size="1">
          <bitfield caption="Watchdog Change Enable" mask="0x10" name="WDCE"/>
          <bitfield caption="Watchdog System Reset Enable" mask="0x08" name="WDE"/>
          <bitfield caption="Watchdog Prescaler Select" mask="0x07" name="WDPS"/>
        </register>
      </register-group>
    </module>
    <module caption="" name="TIMER1">
      <register-group caption="" name="TIMER1">
        <register caption="Timer1 Counter Register" name="T1CNT" offset="0x006F" size="1" mask="0xFF"/>
        <register caption="Timer1 Compare Register" name="T1COR" offset="0x0070" size="1" mask="0xFF"/>
        <register caption="Timer1 control Register" name="T1CR" offset="0x0031" size="1">
          <bitfield caption="Timer1 Enable" mask="0x80" name="T1ENA"/>
          <bitfield caption="Timer1 Toggle with Start" mask="0x40" name="T1TOS"/>
          <bitfield caption="Timer1 Reset" mask="0x20" name="T1RES"/>
          <bitfield caption="Timer1 Toggle Output Preset" mask="0x10" name="T1TOP"/>
          <bitfield caption="Timer1 Compare Reset Mask" mask="0x04" name="T1CRM"/>
          <bitfield caption="Timer1 Compare Toggle Mask" mask="0x02" name="T1CTM"/>
          <bitfield caption="Timer1 Overflow Toggle Mask" mask="0x01" name="T1OTM"/>
        </register>
        <register caption="Timer1 Interrupt Flag Register" name="T1IFR" offset="0x0035" size="1">
          <bitfield caption="Timer1 Compare Flag" mask="0x02" name="T1COF"/>
          <bitfield caption="Timer1 Overflow Flag" mask="0x01" name="T1OFF"/>
        </register>
        <register caption="Timer1 Interrupt Mask Register" name="T1IMR" offset="0x0072" size="1">
          <bitfield caption="Timer1 Compare Interrupt Mask" mask="0x02" name="T1CIM"/>
          <bitfield caption="Timer1 Overflow Interrupt Mask" mask="0x01" name="T1OIM"/>
        </register>
        <register caption="Timer1 Mode Register" name="T1MR" offset="0x0071" size="1">
          <bitfield caption="Timer1 Duty Cycle" mask="0xC0" name="T1DC"/>
          <bitfield caption="Timer1 Prescaler Select" mask="0x3C" name="T1PS"/>
          <bitfield caption="Timer1 Clock Select" mask="0x03" name="T1CS" values="TIM1_CLOCK_SELECT"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM1_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_frc" name="VAL_0x01" value="0x01"/>
        <value caption="clk_T" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto4" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER2">
      <register-group caption="" name="TIMER2">
        <register caption="Timer2 Counter Register" name="T2CNT" offset="0x0073" size="1" mask="0xFF"/>
        <register caption="Timer2 Compare Register" name="T2COR" offset="0x0074" size="1" mask="0xFF"/>
        <register caption="Timer2 Control Register" name="T2CR" offset="0x0032" size="1">
          <bitfield caption="Timer2 Enable" mask="0x80" name="T2ENA"/>
          <bitfield caption="Timer2 Toggle with Start" mask="0x40" name="T2TOS"/>
          <bitfield caption="Timer2 Reset" mask="0x20" name="T2RES"/>
          <bitfield caption="Timer2 Toggle Output Preset" mask="0x10" name="T2TOP"/>
          <bitfield caption="Timer2 Compare Reset Mask" mask="0x04" name="T2CRM"/>
          <bitfield caption="Timer2 Compare Toggle Mask" mask="0x02" name="T2CTM"/>
          <bitfield caption="Timer2 Overflow Toggle Mask" mask="0x01" name="T2OTM"/>
        </register>
        <register caption="Timer2 Interrupt Flag Register" name="T2IFR" offset="0x0036" size="1">
          <bitfield caption="Timer2 Compare Flag" mask="0x02" name="T2COF"/>
          <bitfield caption="Timer2 Overflow Flag" mask="0x01" name="T2OFF"/>
        </register>
        <register caption="Timer2 Interrupt Mask Register" name="T2IMR" offset="0x0076" size="1">
          <bitfield caption="Timer2 Compare Interrupt Mask" mask="0x02" name="T2CIM"/>
          <bitfield caption="Timer2 Overflow Interrupt Mask" mask="0x01" name="T2OIM"/>
        </register>
        <register caption="Timer2 Mode Register" name="T2MR" offset="0x0075" size="1">
          <bitfield caption="Timer2 Duty Cycle" mask="0xC0" name="T2DC"/>
          <bitfield caption="Timer2 Prescaler Select" mask="0x3C" name="T2PS"/>
          <bitfield caption="Timer2 Clock Select" mask="0x03" name="T2CS" values="TIM2_CLOCK_SELECT"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM2_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_vdiv" name="VAL_0x01" value="0x01"/>
        <value caption="clk_T" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto4" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER3">
      <register-group caption="" name="TIMER3">
        <register caption="Timer3 counter Register" name="T3CNT" offset="0x0077" size="2" mask="0xFFFF"/>
        <register caption="Timer3 compare Register" name="T3COR" offset="0x0079" size="2" mask="0xFFFF"/>
        <register caption="Timer3 control Register" name="T3CR" offset="0x0033" size="1">
          <bitfield caption="Timer3 Enable" mask="0x80" name="T3ENA"/>
          <bitfield caption="Timer3 Toggle with Start" mask="0x40" name="T3TOS"/>
          <bitfield caption="Timer3 Reset" mask="0x20" name="T3RES"/>
          <bitfield caption="Timer3 Toggle Output Preset" mask="0x10" name="T3TOP"/>
          <bitfield caption="Timer3 CaPture reset Mask" mask="0x08" name="T3CPRM"/>
          <bitfield caption="Timer3 Compare Reset Mask" mask="0x04" name="T3CRM"/>
          <bitfield caption="Timer3 Compare Toggle Mask" mask="0x02" name="T3CTM"/>
          <bitfield caption="Timer3 Overflow Toggle Mask" mask="0x01" name="T3OTM"/>
        </register>
        <register caption="Timer3 input capture Register" name="T3ICR" offset="0x007B" size="2" mask="0xFFFF"/>
        <register caption="Timer3 interrupt flag Register" name="T3IFR" offset="0x0037" size="1">
          <bitfield caption="Timer3 Input Capture Flag" mask="0x04" name="T3ICF"/>
          <bitfield caption="Timer3 Compare Flag" mask="0x02" name="T3COF"/>
          <bitfield caption="Timer3 OverFlow Flag" mask="0x01" name="T3OFF"/>
        </register>
        <register caption="Timer3 interrupt mask Register" name="T3IMR" offset="0x007F" size="1">
          <bitfield caption="Timer3 Capture Interrupt Mask" mask="0x04" name="T3CPIM"/>
          <bitfield caption="Timer3 Compare Interrupt Mask" mask="0x02" name="T3CIM"/>
          <bitfield caption="Timer3 Overflow Interrupt Mask" mask="0x01" name="T3OIM"/>
        </register>
        <register caption="Timer3 mode Register" name="T3MRA" offset="0x007D" size="1">
          <bitfield caption="Timer3 Prescaler Select" mask="0x1C" name="T3PS"/>
          <bitfield caption="Timer 3 Clock Select" mask="0x03" name="T3CS" values="TIM3_CLOCK_SELECT"/>
        </register>
        <register caption="Timer3 mode Register" name="T3MRB" offset="0x007E" size="1">
          <bitfield caption="Timer3 Input Capture Select" mask="0xE0" name="T3ICS"/>
          <bitfield caption="Timer3 Capture Edge select" mask="0x18" name="T3CE" values="TIM3_CAPTURE_EDGE_SELECT"/>
          <bitfield caption="Timer3 input Capture Noise Canceller" mask="0x04" name="T3CNC"/>
          <bitfield caption="Timer3 Software Capture Enable" mask="0x02" name="T3SCE"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM3_CLOCK_SELECT">
        <value caption="clk_frc" name="VAL_0x00" value="0x00"/>
        <value caption="clk_T" name="VAL_0x01" value="0x01"/>
        <value caption="clk_xto4" name="VAL_0x02" value="0x02"/>
        <value caption="clk_xto2" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TIM3_CAPTURE_EDGE_SELECT">
        <value caption="disable" name="VAL_0x00" value="0x00"/>
        <value caption="rising edge" name="VAL_0x01" value="0x01"/>
        <value caption="falling edge" name="VAL_0x02" value="0x02"/>
        <value caption="both edges" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER4">
      <register-group caption="" name="TIMER4">
        <register caption="Timer4 counter Register" name="T4CNT" offset="0x0080" size="2" mask="0xFFFF"/>
        <register caption="Timer4 compare Register" name="T4COR" offset="0x0082" size="2" mask="0xFFFF"/>
        <register caption="Timer4 control Register" name="T4CR" offset="0x0034" size="1">
          <bitfield caption="Timer4 Enable" mask="0x80" name="T4ENA"/>
          <bitfield caption="Timer4 Toggle with Start" mask="0x40" name="T4TOS"/>
          <bitfield caption="Timer4 Reset" mask="0x20" name="T4RES"/>
          <bitfield caption="Timer4 Toggle Output Preset" mask="0x10" name="T4TOP"/>
          <bitfield caption="Timer4 CaPture reset Mask" mask="0x08" name="T4CPRM"/>
          <bitfield caption="Timer4 Compare Reset Mask" mask="0x04" name="T4CRM"/>
          <bitfield caption="Timer4 Compare Toggle Mask" mask="0x02" name="T4CTM"/>
          <bitfield caption="Timer4 Overflow Toggle Mask" mask="0x01" name="T4OTM"/>
        </register>
        <register caption="Timer4 input capture Register" name="T4ICR" offset="0x0084" size="2" mask="0xFFFF"/>
        <register caption="Timer4 interrupt flag Register" name="T4IFR" offset="0x0038" size="1">
          <bitfield caption="Timer4 Input Capture Flag" mask="0x04" name="T4ICF"/>
          <bitfield caption="Timer4 Compare Flag" mask="0x02" name="T4COF"/>
          <bitfield caption="Timer4 OverFlow Flag" mask="0x01" name="T4OFF"/>
        </register>
        <register caption="Timer4 interrupt mask Register" name="T4IMR" offset="0x0088" size="1">
          <bitfield caption="Timer4 Capture Interrupt Mask" mask="0x04" name="T4CPIM"/>
          <bitfield caption="Timer4 Compare Interrupt Mask" mask="0x02" name="T4CIM"/>
          <bitfield caption="Timer4 Overflow Interrupt Mask" mask="0x01" name="T4OIM"/>
        </register>
        <register caption="Timer4 mode Register" name="T4MRA" offset="0x0086" size="1">
          <bitfield caption="Timer 4 Prescaler Select" mask="0x1C" name="T4PS"/>
          <bitfield caption="Timer 4 Clock Select" mask="0x03" name="T4CS" values="TIM4_CLOCK_SELECT"/>
        </register>
        <register caption="Timer4 mode Register" name="T4MRB" offset="0x0087" size="1">
          <bitfield caption="Timer4 Input Capture Select" mask="0xE0" name="T4ICS"/>
          <bitfield caption="Timer4 Capture Edge select" mask="0x18" name="T4CE"/>
          <bitfield caption="Timer4 input Capture Noise Canceller" mask="0x04" name="T4CNC"/>
          <bitfield caption="Timer4 Software Capture Enable" mask="0x02" name="T4SCE"/>
        </register>
      </register-group>
      <value-group caption="" name="TIM4_CLOCK_SELECT">
        <value caption="clk_src" name="VAL_0x00" value="0x00"/>
        <value caption="clk_T" name="VAL_0x01" value="0x01"/>
        <value caption="clk_xto6" name="VAL_0x02" value="0x02"/>
        <value caption="clk_frc" name="VAL_0x03" value="0x03"/>
      </value-group>
      <value-group caption="" name="TIM4_CAPTURE_EDGE_SELECT">
        <value caption="disable" name="VAL_0x00" value="0x00"/>
        <value caption="rising edge" name="VAL_0x01" value="0x01"/>
        <value caption="falling edge" name="VAL_0x02" value="0x02"/>
        <value caption="both edges" name="VAL_0x03" value="0x03"/>
      </value-group>
    </module>
    <module caption="" name="TIMER5">
      <register-group caption="" name="TIMER5">
        <register caption="General Timer/Counter Control Register" name="GTCCR" offset="0x0090" size="1">
          <bitfield caption="Timer/Counter Synchronization Mode" mask="0x80" name="TSM"/>
          <bitfield caption="PreScaler Reset" mask="0x01" name="PSR10"/>
        </register>
        <register caption="Timer5 Control Register" name="T5CCR" offset="0x008C" size="1">
          <bitfield caption="Clear Timer5 on Compare Match" mask="0x08" name="T5CTC"/>
          <bitfield caption="Timer5 Clock Select" mask="0x07" name="T5CS" values="CLK_SEL_3BIT"/>
        </register>
        <register caption="Timer5 Counter" name="T5CNT" offset="0x008D" size="2" mask="0xFFFF"/>
        <register caption="Timer5 Interrupt Flag Register" name="T5IFR" offset="0x0039" size="1">
          <bitfield caption="Timer5 Output Compare Output Match Flag" mask="0x02" name="T5COF"/>
          <bitfield caption="Timer5 Output Overflow Flag" mask="0x01" name="T5OFF"/>
        </register>
        <register caption="Timer5 Interrupt Mask Register" name="T5IMR" offset="0x008F" size="1">
          <bitfield caption="Timer5 Output Compare Interrupt Mask" mask="0x02" name="T5CIM"/>
          <bitfield caption="Timer5 Output Overflow Interrupt Mask" mask="0x01" name="T5OIM"/>
        </register>
        <register caption="Timer5 Output Compare Register" name="T5OCR" offset="0x008A" size="2" mask="0xFFFF"/>
      </register-group>
      <value-group caption="" name="CLK_SEL_3BIT">
        <value caption="No Clock Source (Stopped)" name="VAL_0x00" value="0x00"/>
        <value caption="Running, No Prescaling" name="VAL_0x01" value="0x01"/>
        <value caption="Running, CLK/8" name="VAL_0x02" value="0x02"/>
        <value caption="Running, CLK/32" name="VAL_0x03" value="0x03"/>
        <value caption="Running, CLK/64" name="VAL_0x04" value="0x04"/>
        <value caption="Running, CLK/128" name="VAL_0x05" value="0x05"/>
        <value caption="Running, CLK/256" name="VAL_0x06" value="0x06"/>
        <value caption="Running, CLK/1024" name="VAL_0x07" value="0x07"/>
      </value-group>
    </module>
  </modules>
</avr-tools-device-file>
