/dts-v1/;

/memreserve/	0x0000000008300000 0x000000000001c000;
/memreserve/	0x000000000a200000 0x00000000008cf15d;
/ {
	serial-number = "425ca8fc29ade692";
	compatible = "rockchip,rk3568-firefly-roc-pc-se\0rockchip,rk3568";
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "Firefly RK3568-ROC-PC-SE HDMI (Linux)";

	memory {
		reg = <0x00 0x80000000 0x00 0x60000000>;
		device_type = "memory";
	};

	ddr3-params {
		version = <0x100>;
		expanded_version = <0x00>;
		reserved = <0x00>;
		freq_0 = <0x420>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x00>;
		freq_5 = <0x00>;
		pd_idle = <0x0d>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x00>;
		srpd_lite_idle = <0x00>;
		standby_idle = <0x00>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x12c>;
		phy_dll_dis_freq = <0x00>;
		phy_dq_drv_odten = <0x21>;
		phy_ca_drv_odten = <0x21>;
		phy_clk_drv_odten = <0x21>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x21>;
		phy_ca_drv_odtoff = <0x21>;
		phy_clk_drv_odtoff = <0x21>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0x78>;
		phy_odt = <0xa7>;
		phy_odt_puup_en = <0x01>;
		phy_odt_pudn_en = <0x01>;
		dram_dq_odt_en_freq = <0x14d>;
		phy_odt_en_freq = <0x14d>;
		phy_dq_sr_odten = <0x0f>;
		phy_ca_sr_odten = <0x03>;
		phy_clk_sr_odten = <0x00>;
		phy_dq_sr_odtoff = <0x0f>;
		phy_ca_sr_odtoff = <0x03>;
		phy_clk_sr_odtoff = <0x00>;
		ssmod_downspread = <0x00>;
		ssmod_div = <0x00>;
		ssmod_spread = <0x00>;
		mode_2t = <0x00>;
		speed_bin = <0x15>;
		dram_ext_temp = <0x00>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x00>;
		dq_map_cs0_dq_h = <0x00>;
		dq_map_cs1_dq_l = <0x00>;
		dq_map_cs1_dq_h = <0x00>;
		phandle = <0xb7>;
	};

	ddr4-params {
		version = <0x100>;
		expanded_version = <0x00>;
		reserved = <0x00>;
		freq_0 = <0x420>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x00>;
		freq_5 = <0x00>;
		pd_idle = <0x0d>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x00>;
		srpd_lite_idle = <0x00>;
		standby_idle = <0x00>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x271>;
		phy_dll_dis_freq = <0x00>;
		phy_dq_drv_odten = <0x25>;
		phy_ca_drv_odten = <0x25>;
		phy_clk_drv_odten = <0x25>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x25>;
		phy_ca_drv_odtoff = <0x25>;
		phy_clk_drv_odtoff = <0x25>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0x78>;
		phy_odt = <0x8b>;
		phy_odt_puup_en = <0x01>;
		phy_odt_pudn_en = <0x01>;
		dram_dq_odt_en_freq = <0x1f4>;
		phy_odt_en_freq = <0x1f4>;
		phy_dq_sr_odten = <0x0e>;
		phy_ca_sr_odten = <0x01>;
		phy_clk_sr_odten = <0x01>;
		phy_dq_sr_odtoff = <0x0e>;
		phy_ca_sr_odtoff = <0x01>;
		phy_clk_sr_odtoff = <0x01>;
		ssmod_downspread = <0x00>;
		ssmod_div = <0x00>;
		ssmod_spread = <0x00>;
		mode_2t = <0x00>;
		speed_bin = <0x0c>;
		dram_ext_temp = <0x00>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x22777788>;
		dq_map_cs0_dq_h = <0xd7888877>;
		dq_map_cs1_dq_l = <0x22777788>;
		dq_map_cs1_dq_h = <0xd7888877>;
		phandle = <0xb8>;
	};

	lpddr3-params {
		version = <0x100>;
		expanded_version = <0x00>;
		reserved = <0x00>;
		freq_0 = <0x420>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x00>;
		freq_5 = <0x00>;
		pd_idle = <0x0d>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x00>;
		srpd_lite_idle = <0x00>;
		standby_idle = <0x00>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x00>;
		phy_dll_dis_freq = <0x00>;
		phy_dq_drv_odten = <0x25>;
		phy_ca_drv_odten = <0x25>;
		phy_clk_drv_odten = <0x27>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x25>;
		phy_ca_drv_odtoff = <0x25>;
		phy_clk_drv_odtoff = <0x27>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0x78>;
		phy_odt = <0x94>;
		phy_odt_puup_en = <0x01>;
		phy_odt_pudn_en = <0x01>;
		dram_dq_odt_en_freq = <0x14d>;
		phy_odt_en_freq = <0x14d>;
		phy_dq_sr_odten = <0x0f>;
		phy_ca_sr_odten = <0x01>;
		phy_clk_sr_odten = <0x0f>;
		phy_dq_sr_odtoff = <0x0f>;
		phy_ca_sr_odtoff = <0x01>;
		phy_clk_sr_odtoff = <0x0f>;
		ssmod_downspread = <0x00>;
		ssmod_div = <0x00>;
		ssmod_spread = <0x00>;
		mode_2t = <0x00>;
		speed_bin = <0x00>;
		dram_ext_temp = <0x00>;
		byte_map = <0x8d>;
		dq_map_cs0_dq_l = <0x00>;
		dq_map_cs0_dq_h = <0x00>;
		dq_map_cs1_dq_l = <0x00>;
		dq_map_cs1_dq_h = <0x00>;
		phandle = <0xb9>;
	};

	lpddr4-params {
		version = <0x100>;
		expanded_version = <0x00>;
		reserved = <0x00>;
		freq_0 = <0x618>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x00>;
		freq_5 = <0x00>;
		pd_idle = <0x0d>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x00>;
		srpd_lite_idle = <0x00>;
		standby_idle = <0x00>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x00>;
		phy_dll_dis_freq = <0x00>;
		phy_dq_drv_odten = <0x1e>;
		phy_ca_drv_odten = <0x26>;
		phy_clk_drv_odten = <0x26>;
		dram_dq_drv_odten = <0x28>;
		phy_dq_drv_odtoff = <0x1e>;
		phy_ca_drv_odtoff = <0x26>;
		phy_clk_drv_odtoff = <0x26>;
		dram_dq_drv_odtoff = <0x28>;
		dram_odt = <0x50>;
		phy_odt = <0x3c>;
		phy_odt_puup_en = <0x00>;
		phy_odt_pudn_en = <0x00>;
		dram_dq_odt_en_freq = <0x320>;
		phy_odt_en_freq = <0x320>;
		phy_dq_sr_odten = <0x00>;
		phy_ca_sr_odten = <0x0f>;
		phy_clk_sr_odten = <0x0f>;
		phy_dq_sr_odtoff = <0x00>;
		phy_ca_sr_odtoff = <0x0f>;
		phy_clk_sr_odtoff = <0x0f>;
		ssmod_downspread = <0x00>;
		ssmod_div = <0x00>;
		ssmod_spread = <0x00>;
		mode_2t = <0x00>;
		speed_bin = <0x00>;
		dram_ext_temp = <0x00>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x00>;
		dq_map_cs0_dq_h = <0x00>;
		dq_map_cs1_dq_l = <0x00>;
		dq_map_cs1_dq_h = <0x00>;
		lp4_ca_odt = <0x78>;
		lp4_drv_pu_cal_odten = <0x01>;
		lp4_drv_pu_cal_odtoff = <0x01>;
		phy_lp4_drv_pulldown_en_odten = <0x00>;
		phy_lp4_drv_pulldown_en_odtoff = <0x00>;
		lp4_ca_odt_en_freq = <0x320>;
		phy_lp4_cs_drv_odten = <0x00>;
		phy_lp4_cs_drv_odtoff = <0x00>;
		lp4_odte_ck_en = <0x01>;
		lp4_odte_cs_en = <0x01>;
		lp4_odtd_ca_en = <0x00>;
		phy_lp4_dq_vref_odten = <0xa6>;
		lp4_dq_vref_odten = <0x12c>;
		lp4_ca_vref_odten = <0x17c>;
		phy_lp4_dq_vref_odtoff = <0x1a4>;
		lp4_dq_vref_odtoff = <0x1a4>;
		lp4_ca_vref_odtoff = <0x1a4>;
		phandle = <0xba>;
	};

	lpddr4x-params {
		version = <0x100>;
		expanded_version = <0x00>;
		reserved = <0x00>;
		freq_0 = <0x618>;
		freq_1 = <0x144>;
		freq_2 = <0x210>;
		freq_3 = <0x30c>;
		freq_4 = <0x00>;
		freq_5 = <0x00>;
		pd_idle = <0x0d>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x00>;
		srpd_lite_idle = <0x00>;
		standby_idle = <0x00>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x00>;
		phy_dll_dis_freq = <0x00>;
		phy_dq_drv_odten = <0x1d>;
		phy_ca_drv_odten = <0x24>;
		phy_clk_drv_odten = <0x24>;
		dram_dq_drv_odten = <0x28>;
		phy_dq_drv_odtoff = <0x1d>;
		phy_ca_drv_odtoff = <0x24>;
		phy_clk_drv_odtoff = <0x24>;
		dram_dq_drv_odtoff = <0x28>;
		dram_odt = <0x50>;
		phy_odt = <0x3c>;
		phy_odt_puup_en = <0x00>;
		phy_odt_pudn_en = <0x00>;
		dram_dq_odt_en_freq = <0x320>;
		phy_odt_en_freq = <0x320>;
		phy_dq_sr_odten = <0x00>;
		phy_ca_sr_odten = <0x00>;
		phy_clk_sr_odten = <0x00>;
		phy_dq_sr_odtoff = <0x00>;
		phy_ca_sr_odtoff = <0x00>;
		phy_clk_sr_odtoff = <0x00>;
		ssmod_downspread = <0x00>;
		ssmod_div = <0x00>;
		ssmod_spread = <0x00>;
		mode_2t = <0x00>;
		speed_bin = <0x00>;
		dram_ext_temp = <0x00>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x00>;
		dq_map_cs0_dq_h = <0x00>;
		dq_map_cs1_dq_l = <0x00>;
		dq_map_cs1_dq_h = <0x00>;
		lp4_ca_odt = <0x78>;
		lp4_drv_pu_cal_odten = <0x00>;
		lp4_drv_pu_cal_odtoff = <0x00>;
		phy_lp4_drv_pulldown_en_odten = <0x00>;
		phy_lp4_drv_pulldown_en_odtoff = <0x00>;
		lp4_ca_odt_en_freq = <0x320>;
		phy_lp4_cs_drv_odten = <0x00>;
		phy_lp4_cs_drv_odtoff = <0x00>;
		lp4_odte_ck_en = <0x00>;
		lp4_odte_cs_en = <0x00>;
		lp4_odtd_ca_en = <0x00>;
		phy_lp4_dq_vref_odten = <0xa6>;
		lp4_dq_vref_odten = <0xe4>;
		lp4_ca_vref_odten = <0x157>;
		phy_lp4_dq_vref_odtoff = <0x1a4>;
		lp4_dq_vref_odtoff = <0x1a4>;
		lp4_ca_vref_odtoff = <0x157>;
		phandle = <0xbb>;
	};

	aliases {
		csi2dphy0 = "/csi2-dphy0";
		csi2dphy1 = "/csi2-dphy1";
		csi2dphy2 = "/csi2-dphy2";
		dsi0 = "/dsi@fe060000";
		dsi1 = "/dsi@fe070000";
		ethernet0 = "/ethernet@fe2a0000";
		ethernet1 = "/ethernet@fe010000";
		gpio0 = "/pinctrl/gpio0@fdd60000";
		gpio1 = "/pinctrl/gpio1@fe740000";
		gpio2 = "/pinctrl/gpio2@fe750000";
		gpio3 = "/pinctrl/gpio3@fe760000";
		gpio4 = "/pinctrl/gpio4@fe770000";
		i2c0 = "/i2c@fdd40000";
		i2c1 = "/i2c@fe5a0000";
		i2c2 = "/i2c@fe5b0000";
		i2c3 = "/i2c@fe5c0000";
		i2c4 = "/i2c@fe5d0000";
		i2c5 = "/i2c@fe5e0000";
		mmc0 = "/sdhci@fe310000";
		mmc1 = "/dwmmc@fe2b0000";
		mmc2 = "/dwmmc@fe2c0000";
		mmc3 = "/dwmmc@fe000000";
		serial0 = "/serial@fdd50000";
		serial1 = "/serial@fe650000";
		serial2 = "/serial@fe660000";
		serial3 = "/serial@fe670000";
		serial4 = "/serial@fe680000";
		serial5 = "/serial@fe690000";
		serial6 = "/serial@fe6a0000";
		serial7 = "/serial@fe6b0000";
		serial8 = "/serial@fe6c0000";
		serial9 = "/serial@fe6d0000";
		spi0 = "/spi@fe610000";
		spi1 = "/spi@fe620000";
		spi2 = "/spi@fe630000";
		spi3 = "/spi@fe640000";
		lvds0 = "/syscon@fdc60000/lvds";
		lvds1 = "/syscon@fdc60000/lvds1";
	};

	cpus {
		#address-cells = <0x02>;
		#size-cells = <0x00>;

		// cpu@0 {
		// 	device_type = "cpu";
		// 	compatible = "arm,cortex-a55";
		// 	reg = <0x00 0x00>;
		// 	enable-method = "psci";
		// 	clocks = <0x02 0x00>;
		// 	operating-points-v2 = <0x03>;
		// 	cpu-idle-states = <0x04>;
		// 	#cooling-cells = <0x02>;
		// 	dynamic-power-coefficient = <0xbb>;
		// 	cpu-supply = <0x05>;
		// 	phandle = <0x0c>;
		// };

		// cpu@100 {
		// 	device_type = "cpu";
		// 	compatible = "arm,cortex-a55";
		// 	reg = <0x00 0x100>;
		// 	enable-method = "psci";
		// 	clocks = <0x02 0x00>;
		// 	operating-points-v2 = <0x03>;
		// 	cpu-idle-states = <0x04>;
		// 	phandle = <0x0d>;
		// };

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x00 0x200>;
			enable-method = "psci";
			clocks = <0x02 0x00>;
			operating-points-v2 = <0x03>;
			cpu-idle-states = <0x04>;
			phandle = <0x0e>;
		};

		cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x00 0x300>;
			enable-method = "psci";
			clocks = <0x02 0x00>;
			operating-points-v2 = <0x03>;
			cpu-idle-states = <0x04>;
			phandle = <0x0f>;
		};

		idle-states {
			entry-method = "psci";

			cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x10000>;
				entry-latency-us = <0x64>;
				exit-latency-us = <0x78>;
				min-residency-us = <0x3e8>;
				phandle = <0x04>;
			};
		};
	};

	cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
		nvmem-cells = <0x06 0x07 0x08 0x09 0x0a 0x0b>;
		nvmem-cell-names = "leakage\0pvtm\0mbist-vmin\0opp-info\0specification_serial_number\0remark_spec_serial_number";
		rockchip,supported-hw;
		rockchip,max-volt = <0x118c30>;
		rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x153d8 0x01 0x153d9 0x16378 0x02 0x16379 0x186a0 0x03>;
		rockchip,pvtm-freq = <0x639c0>;
		rockchip,pvtm-volt = <0xdbba0>;
		rockchip,pvtm-ch = <0x00 0x05>;
		rockchip,pvtm-sample-time = <0x3e8>;
		rockchip,pvtm-number = <0x0a>;
		rockchip,pvtm-error = <0x3e8>;
		rockchip,pvtm-ref-temp = <0x28>;
		rockchip,pvtm-temp-prop = <0x1a 0x1a>;
		rockchip,thermal-zone = "soc-thermal";
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x00>;
		rockchip,low-temp-adjust-volt = <0x00 0x7c8 0x124f8>;
		phandle = <0x03>;

		opp-408000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x18519600>;
			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-600000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-816000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x30a32c00>;
			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
			opp-suspend;
		};

		opp-1104000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x41cdb400>;
			opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
			opp-microvolt-L0 = <0xdbba0 0xdbba0 0x118c30>;
			opp-microvolt-L1 = <0xcf850 0xcf850 0x118c30>;
			opp-microvolt-L2 = <0xcf850 0xcf850 0x118c30>;
			opp-microvolt-L3 = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1416000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0xfa3e8 0xfa3e8 0x118c30>;
			opp-microvolt-L0 = <0xfa3e8 0xfa3e8 0x118c30>;
			opp-microvolt-L1 = <0xee098 0xee098 0x118c30>;
			opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0x118c30>;
			opp-microvolt-L3 = <0xe1d48 0xe1d48 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1608000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x5fd82200>;
			opp-microvolt = <0x10c8e0 0x10c8e0 0x118c30>;
			opp-microvolt-L0 = <0x10c8e0 0x10c8e0 0x118c30>;
			opp-microvolt-L1 = <0x100590 0x100590 0x118c30>;
			opp-microvolt-L2 = <0xfa3e8 0xfa3e8 0x118c30>;
			opp-microvolt-L3 = <0xf4240 0xf4240 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1800000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x6b49d200>;
			opp-microvolt = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L0 = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L1 = <0x10c8e0 0x10c8e0 0x118c30>;
			opp-microvolt-L2 = <0x106738 0x106738 0x118c30>;
			opp-microvolt-L3 = <0x100590 0x100590 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1992000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x76bb8200>;
			opp-microvolt = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L0 = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L1 = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L2 = <0x112a88 0x112a88 0x118c30>;
			opp-microvolt-L3 = <0x10c8e0 0x10c8e0 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-j-1008000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = <0x00 0x3c14dc00>;
			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-j-1416000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-m-1608000000 {
			opp-supported-hw = <0x02 0xffff>;
			opp-hz = <0x00 0x5fd82200>;
			opp-microvolt = <0xf4240 0xf4240 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a55-pmu\0arm,armv8-pmuv3";
		interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>;
		interrupt-affinity = <0x0c 0x0d 0x0e 0x0f>;
	};

	cpuinfo {
		compatible = "rockchip,cpuinfo";
		nvmem-cells = <0x10 0x11 0x12>;
		nvmem-cell-names = "id\0cpu-version\0cpu-code";
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		memory-region = <0x13 0x14>;
		memory-region-names = "drm-logo\0drm-cubic-lut";
		ports = <0x15>;
		devfreq = <0x16>;

		route {

			route-dsi0 {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x17>;
			};

			route-dsi1 {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x18>;
			};

			route-edp {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x19>;
			};

			route-hdmi {
				status = "okay";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x1a>;
			};

			route-lvds {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x1b>;
			};

			route-rgb {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x1c>;
			};
		};
	};

	edac {
		compatible = "rockchip,rk3568-edac";
		interrupts = <0x00 0xad 0x04 0x00 0xaf 0x04>;
		interrupt-names = "ce\0ue";
		status = "disabled";
	};

	firmware {

		scmi {
			compatible = "arm,scmi-smc";
			shmem = <0x1d>;
			arm,smc-id = <0x82000010>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			protocol@14 {
				reg = <0x14>;
				#clock-cells = <0x01>;
				rockchip,clk-init = <0x41cdb400>;
				phandle = <0x02>;
			};
		};

		sdei {
			compatible = "arm,sdei-1.0";
			method = "smc";
		};
	};

	mipi-csi2 {
		compatible = "rockchip,rk3568-mipi-csi2";
		rockchip,hw = <0x1e>;
		status = "disabled";
	};

	mpp-srv {
		compatible = "rockchip,mpp-service";
		rockchip,taskqueue-count = <0x06>;
		rockchip,resetgroup-count = <0x06>;
		status = "okay";
		phandle = <0x7b>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		drm-logo@00000000 {
			compatible = "rockchip,drm-logo";
			reg = <0x00 0xedf00000 0x00 0x2e0000>;
			phandle = <0x13>;
		};

		drm-cubic-lut@00000000 {
			compatible = "rockchip,drm-cubic-lut";
			reg = <0x00 0xeff00000 0x00 0x8000>;
			phandle = <0x14>;
		};

		ramoops@110000 {
			compatible = "ramoops";
			reg = <0x00 0x110000 0x00 0xf0000>;
			record-size = <0x20000>;
			console-size = <0x80000>;
			ftrace-size = <0x00>;
			pmsg-size = <0x50000>;
		};
	};

	rockchip-suspend {
		compatible = "rockchip,pm-rk3568";
		status = "okay";
		rockchip,sleep-debug-en = <0x01>;
		rockchip,sleep-mode-config = <0x5ec>;
		rockchip,wakeup-config = <0x10>;
	};

	rockchip-system-monitor {
		compatible = "rockchip,system-monitor";
		rockchip,thermal-zone = "soc-thermal";
	};

	thermal-zones {

		soc-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			sustainable-power = <0x389>;
			thermal-sensors = <0x1f 0x00>;

			trips {

				trip-point-0 {
					temperature = <0x124f8>;
					hysteresis = <0x7d0>;
					type = "passive";
				};

				trip-point-1 {
					temperature = <0x14c08>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x20>;
				};

				soc-crit {
					temperature = <0x1c138>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0x20>;
					cooling-device = <0x0c 0xffffffff 0xffffffff>;
					contribution = <0x400>;
				};

				map1 {
					trip = <0x20>;
					cooling-device = <0x21 0xffffffff 0xffffffff>;
					contribution = <0x400>;
				};
			};
		};

		gpu-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x1f 0x01>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
		arm,no-tick-in-suspend;
	};

	external-gmac0-clock {
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
		clock-output-names = "gmac0_clkin";
		#clock-cells = <0x00>;
		phandle = <0xc7>;
	};

	external-gmac1-clock {
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
		clock-output-names = "gmac1_clkin";
		#clock-cells = <0x00>;
		phandle = <0x92>;
	};

	xpcs-gmac0-clock {
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
		clock-output-names = "clk_gmac0_xpcs_mii";
		#clock-cells = <0x00>;
	};

	xpcs-gmac1-clock {
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
		clock-output-names = "clk_gmac1_xpcs_mii";
		#clock-cells = <0x00>;
	};

	i2s1-mclkin-rx {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		clock-output-names = "i2s1_mclkin_rx";
	};

	i2s1-mclkin-tx {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		clock-output-names = "i2s1_mclkin_tx";
	};

	i2s2-mclkin {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		clock-output-names = "i2s2_mclkin";
	};

	i2s3-mclkin {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		clock-output-names = "i2s3_mclkin";
	};

	mpll {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0x2faf0800>;
		clock-output-names = "mpll";
	};

	xin24m {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0x16e3600>;
		clock-output-names = "xin24m";
	};

	xin32k {
		compatible = "fixed-clock";
		clock-frequency = <0x8000>;
		clock-output-names = "xin32k";
		#clock-cells = <0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x22>;
	};

	scmi-shmem@10f000 {
		compatible = "arm,scmi-shmem";
		reg = <0x00 0x10f000 0x00 0x100>;
		phandle = <0x1d>;
	};

	sata@fc000000 {
		compatible = "snps,dwc-ahci";
		reg = <0x00 0xfc000000 0x00 0x1000>;
		clocks = <0x23 0x96 0x23 0x97 0x23 0x98>;
		clock-names = "sata\0pmalive\0rxoob";
		interrupts = <0x00 0x5e 0x04>;
		interrupt-names = "hostc";
		phys = <0x24 0x01>;
		phy-names = "sata-phy";
		ports-implemented = <0x01>;
		power-domains = <0x25 0x0f>;
		status = "disabled";
	};

	sata@fc400000 {
		compatible = "snps,dwc-ahci";
		reg = <0x00 0xfc400000 0x00 0x1000>;
		clocks = <0x23 0x9b 0x23 0x9c 0x23 0x9d>;
		clock-names = "sata\0pmalive\0rxoob";
		interrupts = <0x00 0x5f 0x04>;
		interrupt-names = "hostc";
		phys = <0x26 0x01>;
		phy-names = "sata-phy";
		ports-implemented = <0x01>;
		power-domains = <0x25 0x0f>;
		status = "disabled";
	};

	sata@fc800000 {
		compatible = "snps,dwc-ahci";
		reg = <0x00 0xfc800000 0x00 0x1000>;
		clocks = <0x23 0xa0 0x23 0xa1 0x23 0xa2>;
		clock-names = "sata\0pmalive\0rxoob";
		interrupts = <0x00 0x60 0x04>;
		interrupt-names = "hostc";
		phys = <0x27 0x01>;
		phy-names = "sata-phy";
		ports-implemented = <0x01>;
		power-domains = <0x25 0x0f>;
		status = "okay";
	};

	usbdrd {
		compatible = "rockchip,rk3568-dwc3\0rockchip,rk3399-dwc3";
		clocks = <0x23 0xa6 0x23 0xa7 0x23 0xa5 0x23 0x7f>;
		clock-names = "ref_clk\0suspend_clk\0bus_clk\0pipe_clk";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		status = "okay";

		dwc3@fcc00000 {
			compatible = "snps,dwc3";
			reg = <0x00 0xfcc00000 0x00 0x400000>;
			interrupts = <0x00 0xa9 0x04>;
			dr_mode = "otg";
			phys = <0x28 0x24 0x04>;
			phy-names = "usb2-phy\0usb3-phy";
			phy_type = "utmi_wide";
			power-domains = <0x25 0x0f>;
			resets = <0x23 0x94>;
			reset-names = "usb3-otg";
			snps,dis_enblslpm_quirk;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			snps,dis_rxdet_inp3_quirk;
			snps,parkmode-disable-hs-quirk;
			snps,parkmode-disable-ss-quirk;
			quirk-skip-phy-init;
			status = "okay";
			extcon = <0x29>;
			usb-role-switch;

			port {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x2a>;
					phandle = <0x4d>;
				};
			};
		};
	};

	usbhost {
		compatible = "rockchip,rk3568-dwc3\0rockchip,rk3399-dwc3";
		clocks = <0x23 0xa9 0x23 0xaa 0x23 0xa8 0x23 0x7f>;
		clock-names = "ref_clk\0suspend_clk\0bus_clk\0pipe_clk";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		status = "okay";

		dwc3@fd000000 {
			compatible = "snps,dwc3";
			reg = <0x00 0xfd000000 0x00 0x400000>;
			interrupts = <0x00 0xaa 0x04>;
			dr_mode = "host";
			phys = <0x2b 0x26 0x04>;
			phy-names = "usb2-phy\0usb3-phy";
			phy_type = "utmi_wide";
			power-domains = <0x25 0x0f>;
			resets = <0x23 0x95>;
			reset-names = "usb3-host";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			snps,dis_rxdet_inp3_quirk;
			snps,parkmode-disable-hs-quirk;
			snps,parkmode-disable-ss-quirk;
			status = "okay";
		};
	};

	interrupt-controller@fd400000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <0x03>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		interrupt-controller;
		reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>;
		interrupts = <0x01 0x09 0x04>;
		phandle = <0x01>;

		interrupt-controller@fd440000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <0x01>;
			reg = <0x00 0xfd440000 0x00 0x20000>;
			status = "okay";
			phandle = <0xbe>;
		};
	};

	usb@fd800000 {
		compatible = "generic-ehci";
		reg = <0x00 0xfd800000 0x00 0x40000>;
		interrupts = <0x00 0x82 0x04>;
		clocks = <0x23 0xbd 0x23 0xbe 0x23 0xbc 0x2c>;
		clock-names = "usbhost\0arbiter\0pclk\0utmi";
		phys = <0x2d>;
		phy-names = "usb2-phy";
		status = "okay";
	};

	usb@fd840000 {
		compatible = "generic-ohci";
		reg = <0x00 0xfd840000 0x00 0x40000>;
		interrupts = <0x00 0x83 0x04>;
		clocks = <0x23 0xbd 0x23 0xbe 0x23 0xbc 0x2c>;
		clock-names = "usbhost\0arbiter\0pclk\0utmi";
		phys = <0x2d>;
		phy-names = "usb2-phy";
		status = "okay";
	};

	usb@fd880000 {
		compatible = "generic-ehci";
		reg = <0x00 0xfd880000 0x00 0x40000>;
		interrupts = <0x00 0x85 0x04>;
		clocks = <0x23 0xbf 0x23 0xc0 0x23 0xbc 0x2c>;
		clock-names = "usbhost\0arbiter\0pclk\0utmi";
		phys = <0x2e>;
		phy-names = "usb2-phy";
		status = "okay";
	};

	usb@fd8c0000 {
		compatible = "generic-ohci";
		reg = <0x00 0xfd8c0000 0x00 0x40000>;
		interrupts = <0x00 0x86 0x04>;
		clocks = <0x23 0xbf 0x23 0xc0 0x23 0xbc 0x2c>;
		clock-names = "usbhost\0arbiter\0pclk\0utmi";
		phys = <0x2e>;
		phy-names = "usb2-phy";
		status = "okay";
	};

	syscon@fda00000 {
		compatible = "rockchip,rk3568-xpcs\0syscon";
		reg = <0x00 0xfda00000 0x00 0x200000>;
		status = "disabled";
	};

	syscon@fdc20000 {
		compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd";
		reg = <0x00 0xfdc20000 0x00 0x10000>;
		phandle = <0x3c>;

		io-domains {
			compatible = "rockchip,rk3568-pmu-io-voltage-domain";
			status = "okay";
			pmuio1-supply = <0x2f>;
			pmuio2-supply = <0x2f>;
			vccio1-supply = <0x30>;
			vccio3-supply = <0x31>;
			vccio4-supply = <0x32>;
			vccio5-supply = <0x33>;
			vccio6-supply = <0x32>;
			vccio7-supply = <0x33>;
		};

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x200>;
			mode-bootloader = <0x5242c301>;
			mode-charge = <0x5242c30b>;
			mode-fastboot = <0x5242c309>;
			mode-loader = <0x5242c301>;
			mode-normal = <0x5242c300>;
			mode-recovery = <0x5242c303>;
			mode-ums = <0x5242c30c>;
			mode-panic = <0x5242c307>;
			mode-watchdog = <0x5242c308>;
		};
	};

	syscon@fdc50000 {
		compatible = "rockchip,rk3568-pipegrf\0syscon";
		reg = <0x00 0xfdc50000 0x00 0x1000>;
		phandle = <0x12a>;
	};

	syscon@fdc60000 {
		compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd";
		reg = <0x00 0xfdc60000 0x00 0x10000>;
		phandle = <0x3b>;

		io-domains {
			compatible = "rockchip,rk3568-io-voltage-domain";
			status = "disabled";
		};

		lvds {
			compatible = "rockchip,rk3568-lvds";
			phys = <0x34>;
			phy-names = "phy";
			status = "disabled";

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					endpoint@1 {
						reg = <0x01>;
						remote-endpoint = <0x1b>;
						status = "disabled";
						phandle = <0xa3>;
					};

					endpoint@2 {
						reg = <0x02>;
						remote-endpoint = <0x35>;
						status = "disabled";
						phandle = <0xa5>;
					};
				};
			};
		};

		lvds1 {
			compatible = "rockchip,rk3568-lvds";
			phys = <0x36>;
			phy-names = "phy";
			status = "disabled";

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					endpoint@0 {
						reg = <0x00>;
						remote-endpoint = <0x37>;
						phandle = <0xa4>;
					};

					endpoint@1 {
						reg = <0x01>;
						remote-endpoint = <0x38>;
						phandle = <0xa7>;
					};
				};
			};
		};

		rgb {
			compatible = "rockchip,rk3568-rgb";
			pinctrl-names = "default";
			pinctrl-0 = <0x39>;
			status = "disabled";

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					endpoint@2 {
						reg = <0x02>;
						remote-endpoint = <0x1c>;
						status = "disabled";
						phandle = <0xa6>;
					};
				};
			};
		};
	};

	syscon@fdc70000 {
		compatible = "rockchip,pipe-phy-grf\0syscon";
		reg = <0x00 0xfdc70000 0x00 0x1000>;
		phandle = <0x12b>;
	};

	syscon@fdc80000 {
		compatible = "rockchip,pipe-phy-grf\0syscon";
		reg = <0x00 0xfdc80000 0x00 0x1000>;
		phandle = <0x12c>;
	};

	syscon@fdc90000 {
		compatible = "rockchip,pipe-phy-grf\0syscon";
		reg = <0x00 0xfdc90000 0x00 0x1000>;
		phandle = <0x12d>;
	};

	syscon@fdca0000 {
		compatible = "rockchip,rk3568-usb2phy-grf\0syscon";
		reg = <0x00 0xfdca0000 0x00 0x8000>;
		phandle = <0x135>;
	};

	syscon@fdca8000 {
		compatible = "rockchip,rk3568-usb2phy-grf\0syscon";
		reg = <0x00 0xfdca8000 0x00 0x8000>;
		phandle = <0x137>;
	};

	syscon@fdcb0000 {
		compatible = "rockchip,rk3568-edp-phy-grf\0syscon\0simple-mfd";
		reg = <0x00 0xfdcb0000 0x00 0x100>;
		clocks = <0x23 0x192>;

		edp-phy {
			compatible = "rockchip,rk3568-edp-phy";
			clocks = <0x3a 0x29>;
			clock-names = "refclk";
			#phy-cells = <0x00>;
			status = "disabled";
			phandle = <0xae>;
		};
	};

	syscon@fdcb8000 {
		compatible = "rockchip,pcie30-phy-grf\0syscon";
		reg = <0x00 0xfdcb8000 0x00 0x10000>;
		phandle = <0x138>;
	};

	sram@fdcc0000 {
		compatible = "mmio-sram";
		reg = <0x00 0xfdcc0000 0x00 0xb000>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges = <0x00 0x00 0xfdcc0000 0xb000>;

		rkvdec-sram@0 {
			reg = <0x00 0xb000>;
			phandle = <0x84>;
		};
	};

	clock-controller@fdd00000 {
		compatible = "rockchip,rk3568-pmucru";
		reg = <0x00 0xfdd00000 0x00 0x1000>;
		rockchip,grf = <0x3b>;
		rockchip,pmugrf = <0x3c>;
		#clock-cells = <0x01>;
		#reset-cells = <0x01>;
		assigned-clocks = <0x3a 0x32>;
		assigned-clock-parents = <0x3a 0x05>;
		phandle = <0x3a>;
	};

	clock-controller@fdd20000 {
		compatible = "rockchip,rk3568-cru";
		reg = <0x00 0xfdd20000 0x00 0x1000>;
		rockchip,grf = <0x3b>;
		#clock-cells = <0x01>;
		#reset-cells = <0x01>;
		assigned-clocks = <0x3a 0x05 0x23 0x106 0x23 0x10b 0x3a 0x01 0x3a 0x2b 0x23 0x03 0x23 0x19b 0x23 0x09 0x23 0x19c 0x23 0x19d 0x23 0x1a1 0x23 0x19e 0x23 0x19f 0x23 0x1a0 0x23 0x04 0x23 0x10d 0x23 0x10e 0x23 0x173 0x23 0x174 0x23 0x175 0x23 0x176 0x23 0xc9 0x23 0xca 0x23 0x06 0x23 0x7e 0x23 0x7f 0x23 0x3d 0x23 0x41 0x23 0x45 0x23 0x49 0x23 0x4d 0x23 0x4d 0x23 0x55 0x23 0x51 0x23 0x5d 0x23 0xdd>;
		assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>;
		assigned-clock-parents = <0x3a 0x08 0x23 0x04 0x23 0x04>;
		phandle = <0x23>;
	};

	i2c@fdd40000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xfdd40000 0x00 0x1000>;
		clocks = <0x3a 0x07 0x3a 0x2d>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x2e 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x3d>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";

		tcs4525@1c {
			compatible = "tcs,tcs452x";
			reg = <0x1c>;
			vin-supply = <0x3e>;
			regulator-compatible = "fan53555-reg";
			regulator-name = "vdd_cpu";
			regulator-min-microvolt = <0xadf34>;
			regulator-max-microvolt = <0x1535b0>;
			regulator-ramp-delay = <0x8fc>;
			fcs,suspend-voltage-selector = <0x01>;
			regulator-boot-on;
			regulator-always-on;
			phandle = <0x05>;

			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};

		pmic@20 {
			compatible = "rockchip,rk809";
			reg = <0x20>;
			interrupt-parent = <0x3f>;
			interrupts = <0x03 0x08>;
			pinctrl-names = "default\0pmic-sleep\0pmic-power-off\0pmic-reset";
			pinctrl-0 = <0x40>;
			pinctrl-1 = <0x41 0x42>;
			pinctrl-2 = <0x43 0x44>;
			pinctrl-3 = <0x43 0x45>;
			rockchip,system-power-controller;
			wakeup-source;
			#clock-cells = <0x01>;
			clock-output-names = "rk808-clkout1\0rk808-clkout2";
			pmic-reset-func = <0x00>;
			not-save-power-en = <0x01>;
			vcc1-supply = <0x46>;
			vcc2-supply = <0x46>;
			vcc3-supply = <0x46>;
			vcc4-supply = <0x46>;
			vcc5-supply = <0x46>;
			vcc6-supply = <0x46>;
			vcc7-supply = <0x46>;
			vcc8-supply = <0x46>;
			vcc9-supply = <0x46>;
			phandle = <0x152>;

			pwrkey {
				status = "okay";
			};

			pinctrl_rk8xx {
				gpio-controller;
				#gpio-cells = <0x02>;

				rk817_slppin_null {
					pins = "gpio_slp";
					function = "pin_fun0";
				};

				rk817_slppin_slp {
					pins = "gpio_slp";
					function = "pin_fun1";
					phandle = <0x42>;
				};

				rk817_slppin_pwrdn {
					pins = "gpio_slp";
					function = "pin_fun2";
					phandle = <0x44>;
				};

				rk817_slppin_rst {
					pins = "gpio_slp";
					function = "pin_fun3";
					phandle = <0x45>;
				};
			};

			regulators {

				DCDC_REG1 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x7a120>;
					regulator-max-microvolt = <0x149970>;
					regulator-init-microvolt = <0xdbba0>;
					regulator-ramp-delay = <0x1771>;
					regulator-initial-mode = <0x02>;
					regulator-name = "vdd_logic";
					phandle = <0x75>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG2 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x7a120>;
					regulator-max-microvolt = <0x149970>;
					regulator-init-microvolt = <0xdbba0>;
					regulator-ramp-delay = <0x1771>;
					regulator-initial-mode = <0x02>;
					regulator-name = "vdd_gpu";
					phandle = <0x77>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG3 {
					regulator-always-on;
					regulator-boot-on;
					regulator-initial-mode = <0x02>;
					regulator-name = "vcc_ddr";

					regulator-state-mem {
						regulator-on-in-suspend;
					};
				};

				DCDC_REG4 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x7a120>;
					regulator-max-microvolt = <0x149970>;
					regulator-init-microvolt = <0xdbba0>;
					regulator-ramp-delay = <0x1771>;
					regulator-initial-mode = <0x02>;
					regulator-name = "vdd_npu";
					phandle = <0x71>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG1 {
					regulator-boot-on;
					regulator-always-on;
					regulator-min-microvolt = <0xdbba0>;
					regulator-max-microvolt = <0xdbba0>;
					regulator-name = "vdda0v9_image";

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG2 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xdbba0>;
					regulator-max-microvolt = <0xdbba0>;
					regulator-name = "vdda_0v9";

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG3 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xdbba0>;
					regulator-max-microvolt = <0xdbba0>;
					regulator-name = "vdda0v9_pmu";

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0xdbba0>;
					};
				};

				LDO_REG4 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vccio_acodec";
					phandle = <0x30>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG5 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vccio_sd";
					phandle = <0x31>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG6 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vcc3v3_pmu";
					phandle = <0x2f>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x325aa0>;
					};
				};

				LDO_REG7 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "vcca_1v8";
					phandle = <0x129>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG8 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "vcca1v8_pmu";

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				LDO_REG9 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "vcca1v8_image";

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG5 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "vcc_1v8";
					phandle = <0x32>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				SWITCH_REG1 {
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "vcc_3v3";
					phandle = <0x33>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				SWITCH_REG2 {
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "vcc3v3_sd";
					phandle = <0xcf>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};
			};

			codec {
				#sound-dai-cells = <0x00>;
				compatible = "rockchip,rk809-codec\0rockchip,rk817-codec";
				clocks = <0x23 0x1a3>;
				clock-names = "mclk";
				assigned-clocks = <0x23 0x1a3 0x23 0x1a6>;
				assigned-clock-rates = <0xbb8000>;
				assigned-clock-parents = <0x23 0x48 0x23 0x48>;
				pinctrl-names = "default\0spk_gpio";
				pinctrl-0 = <0x47>;
				pinctrl-1 = <0x48>;
				hp-volume = <0x03>;
				spk-volume = <0x03>;
				mic-in-differential;
				board-spk-from-hp;
				capture-volume = <0x00>;
				io-channels = <0x49 0x07>;
				hp-det-adc-value = <0x3e8>;
				status = "okay";
				hp-adc-drift-scope = <0x64>;
				phandle = <0x14b>;
			};

			rtc {
				status = "disabled";
			};
		};

		fusb302@22 {
			compatible = "fcs,fusb302";
			reg = <0x22>;
			interrupt-parent = <0x3f>;
			fcs,int_n = <0x3f 0x11 0x08>;
			fusb340-switch-gpios = <0x4a 0x12 0x00>;
			pinctrl-names = "default";
			pinctrl-0 = <0x4b>;
			vbus-supply = <0x4c>;
			status = "okay";

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;

					endpoint@0 {
						remote-endpoint = <0x4d>;
						phandle = <0x2a>;
					};
				};
			};

			connector {
				compatible = "usb-c-connector";
				label = "USB-C";
				data-role = "dual";
				power-role = "dual";
				try-power-role = "sink";
				op-sink-microwatt = <0xf4240>;
				sink-pdos = <0x40190fa>;
				source-pdos = <0x4019096>;
			};
		};
	};

	serial@fdd50000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfdd50000 0x00 0x100>;
		interrupts = <0x00 0x74 0x04>;
		clocks = <0x3a 0x0b 0x3a 0x2c>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x00 0x4e 0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0x4f>;
		status = "disabled";
	};

	pwm@fdd70000 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfdd70000 0x00 0x10>;
		interrupts = <0x00 0x52 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x50>;
		clocks = <0x3a 0x0d 0x3a 0x30>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fdd70010 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfdd70010 0x00 0x10>;
		interrupts = <0x00 0x52 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x51>;
		clocks = <0x3a 0x0d 0x3a 0x30>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fdd70020 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfdd70020 0x00 0x10>;
		interrupts = <0x00 0x52 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x52>;
		clocks = <0x3a 0x0d 0x3a 0x30>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fdd70030 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfdd70030 0x00 0x10>;
		interrupts = <0x00 0x52 0x04 0x00 0x56 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x53>;
		clocks = <0x3a 0x0d 0x3a 0x30>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	power-management@fdd90000 {
		compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd";
		reg = <0x00 0xfdd90000 0x00 0x1000>;

		power-controller {
			compatible = "rockchip,rk3568-power-controller";
			#power-domain-cells = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "okay";
			phandle = <0x25>;

			pd_npu@6 {
				reg = <0x06>;
				clocks = <0x23 0x27 0x23 0x25 0x23 0x26>;
				pm_qos = <0x54>;
			};

			pd_gpu@7 {
				reg = <0x07>;
				clocks = <0x23 0x19 0x23 0x1a>;
				pm_qos = <0x55>;
			};

			pd_vi@8 {
				reg = <0x08>;
				clocks = <0x23 0xcc 0x23 0xcd>;
				pm_qos = <0x56 0x57 0x58>;
			};

			pd_vo@9 {
				reg = <0x09>;
				clocks = <0x23 0xda 0x23 0xdb 0x23 0xdc>;
				pm_qos = <0x59 0x5a 0x5b>;
			};

			pd_rga@10 {
				reg = <0x0a>;
				clocks = <0x23 0xf1 0x23 0xf2>;
				pm_qos = <0x5c 0x5d 0x5e 0x5f 0x60 0x61>;
			};

			pd_vpu@11 {
				reg = <0x0b>;
				clocks = <0x23 0xed>;
				pm_qos = <0x62>;
			};

			pd_rkvdec@13 {
				clocks = <0x23 0x107>;
				reg = <0x0d>;
				pm_qos = <0x63>;
			};

			pd_rkvenc@14 {
				reg = <0x0e>;
				clocks = <0x23 0x102>;
				pm_qos = <0x64 0x65 0x66>;
			};

			pd_pipe@15 {
				reg = <0x0f>;
				clocks = <0x23 0x7f>;
				pm_qos = <0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e>;
			};
		};
	};

	pvtm@fde00000 {
		compatible = "rockchip,rk3568-core-pvtm";
		reg = <0x00 0xfde00000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		pvtm@0 {
			reg = <0x00>;
			clocks = <0x23 0x13 0x23 0x1c2>;
			clock-names = "clk\0pclk";
			resets = <0x23 0x1a 0x23 0x19>;
			reset-names = "rts\0rst-p";
			thermal-zone = "soc-thermal";
		};
	};

	npu@fde40000 {
		compatible = "rockchip,rk3568-rknpu\0rockchip,rknpu";
		reg = <0x00 0xfde40000 0x00 0x10000>;
		interrupts = <0x00 0x97 0x04>;
		clocks = <0x02 0x02 0x23 0x23 0x23 0x28 0x23 0x29>;
		clock-names = "scmi_clk\0clk\0aclk\0hclk";
		assigned-clocks = <0x23 0x23>;
		assigned-clock-rates = <0x23c34600>;
		resets = <0x23 0x2b 0x23 0x2c>;
		reset-names = "srst_a\0srst_h";
		power-domains = <0x25 0x06>;
		operating-points-v2 = <0x6f>;
		iommus = <0x70>;
		status = "okay";
		rknpu-supply = <0x71>;
	};

	npu-opp-table {
		compatible = "operating-points-v2";
		mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
		nvmem-cells = <0x72 0x07 0x08 0x73 0x0a 0x0b>;
		nvmem-cell-names = "leakage\0pvtm\0mbist-vmin\0opp-info\0specification_serial_number\0remark_spec_serial_number";
		rockchip,supported-hw;
		rockchip,max-volt = <0xf4240>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x00>;
		rockchip,low-temp-adjust-volt = <0x00 0x3e8 0xc350>;
		rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x153d8 0x01 0x153d9 0x16378 0x02 0x16379 0x186a0 0x03>;
		rockchip,pvtm-ch = <0x00 0x05>;
		phandle = <0x6f>;

		opp-200000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0xbebc200>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
		};

		opp-300000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x11b3dc40>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
		};

		opp-400000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
		};

		opp-600000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
		};

		opp-700000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x29b92700>;
			opp-microvolt = <0xd59f8 0xd59f8 0xf4240>;
			opp-microvolt-L0 = <0xd59f8 0xd59f8 0xf4240>;
			opp-microvolt-L1 = <0xcf850 0xcf850 0xf4240>;
			opp-microvolt-L2 = <0xcf850 0xcf850 0xf4240>;
			opp-microvolt-L3 = <0xcf850 0xcf850 0xf4240>;
		};

		opp-800000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x2faf0800>;
			opp-microvolt = <0xe1d48 0xe1d48 0xf4240>;
			opp-microvolt-L0 = <0xe1d48 0xe1d48 0xf4240>;
			opp-microvolt-L1 = <0xdbba0 0xdbba0 0xf4240>;
			opp-microvolt-L2 = <0xd59f8 0xd59f8 0xf4240>;
			opp-microvolt-L3 = <0xd59f8 0xd59f8 0xf4240>;
		};

		opp-900000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x35a4e900>;
			opp-microvolt = <0xee098 0xee098 0xf4240>;
			opp-microvolt-L0 = <0xee098 0xee098 0xf4240>;
			opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xf4240>;
			opp-microvolt-L2 = <0xe1d48 0xe1d48 0xf4240>;
			opp-microvolt-L3 = <0xdbba0 0xdbba0 0xf4240>;
		};

		opp-1000000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x3b9aca00>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240>;
			opp-microvolt-L0 = <0xf4240 0xf4240 0xf4240>;
			opp-microvolt-L1 = <0xee098 0xee098 0xf4240>;
			opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0xf4240>;
			opp-microvolt-L3 = <0xe1d48 0xe1d48 0xf4240>;
			status = "disabled";
		};

		opp-j-600000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xdbba0 0xdbba0 0xf4240>;
		};

		opp-m-900000000 {
			opp-supported-hw = <0x02 0xffff>;
			opp-hz = <0x00 0x35a4e900>;
			opp-microvolt = <0xe1d48 0xe1d48 0xf4240>;
		};
	};

	bus-npu {
		compatible = "rockchip,rk3568-bus";
		rockchip,busfreq-policy = "clkfreq";
		clocks = <0x02 0x02>;
		clock-names = "bus";
		operating-points-v2 = <0x74>;
		status = "okay";
		bus-supply = <0x75>;
		pvtm-supply = <0x05>;
	};

	bus-npu-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		nvmem-cells = <0x07>;
		nvmem-cell-names = "pvtm";
		rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x16378 0x01 0x16379 0x186a0 0x02>;
		rockchip,pvtm-ch = <0x00 0x05>;
		phandle = <0x74>;

		opp-700000000 {
			opp-hz = <0x00 0x29b92700>;
			opp-microvolt = <0xdbba0>;
			opp-microvolt-L0 = <0xdbba0>;
			opp-microvolt-L1 = <0xd59f8>;
			opp-microvolt-L2 = <0xd59f8>;
		};

		opp-900000000 {
			opp-hz = <0x00 0x35a4e900>;
			opp-microvolt = <0xdbba0>;
		};

		opp-1000000000 {
			opp-hz = <0x00 0x3b9aca00>;
			opp-microvolt = <0xe7ef0>;
			opp-microvolt-L0 = <0xe7ef0>;
			opp-microvolt-L1 = <0xe1d48>;
			opp-microvolt-L2 = <0xdbba0>;
		};
	};

	iommu@fde4b000 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfde4b000 0x00 0x40>;
		interrupts = <0x00 0x97 0x04>;
		interrupt-names = "rknpu_mmu";
		clocks = <0x23 0x28 0x23 0x29>;
		clock-names = "aclk\0iface";
		power-domains = <0x25 0x06>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x70>;
	};

	gpu@fde60000 {
		compatible = "arm,mali-bifrost";
		reg = <0x00 0xfde60000 0x00 0x4000>;
		interrupts = <0x00 0x27 0x04 0x00 0x29 0x04 0x00 0x28 0x04>;
		interrupt-names = "GPU\0MMU\0JOB";
		upthreshold = <0x28>;
		downdifferential = <0x0a>;
		clocks = <0x02 0x01 0x23 0x1b>;
		clock-names = "clk_mali\0clk_gpu";
		power-domains = <0x25 0x07>;
		#cooling-cells = <0x02>;
		operating-points-v2 = <0x76>;
		status = "okay";
		mali-supply = <0x77>;
		phandle = <0x21>;

		power-model {
			compatible = "simple-power-model";
			leakage-range = <0x05 0x0f>;
			ls = <0xffffa23e 0x5927 0x00>;
			static-coefficient = <0x186a0>;
			dynamic-coefficient = <0x3b9>;
			ts = <0xfffe56a6 0xf87a 0xfffffab5 0x14>;
			thermal-zone = "gpu-thermal";
		};
	};

	opp-table2 {
		compatible = "operating-points-v2";
		mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
		nvmem-cells = <0x78 0x07 0x08 0x79 0x0a 0x0b>;
		nvmem-cell-names = "leakage\0pvtm\0mbist-vmin\0opp-info\0specification_serial_number\0remark_spec_serial_number";
		rockchip,supported-hw;
		rockchip,max-volt = <0xf4240>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x00>;
		rockchip,low-temp-adjust-volt = <0x00 0x320 0xc350>;
		rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x153d8 0x01 0x153d9 0x16378 0x02 0x16379 0x186a0 0x03>;
		rockchip,pvtm-ch = <0x00 0x05>;
		phandle = <0x76>;

		opp-200000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0xbebc200>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
		};

		opp-300000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x11e1a300>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
		};

		opp-400000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
		};

		opp-600000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xdbba0 0xdbba0 0xf4240>;
			opp-microvolt-L0 = <0xdbba0 0xdbba0 0xf4240>;
			opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240>;
			opp-microvolt-L2 = <0xcf850 0xcf850 0xf4240>;
			opp-microvolt-L3 = <0xcf850 0xcf850 0xf4240>;
		};

		opp-700000000 {
			opp-supported-hw = <0xfb 0xffff>;
			opp-hz = <0x00 0x29b92700>;
			opp-microvolt = <0xe7ef0 0xe7ef0 0xf4240>;
			opp-microvolt-L0 = <0xe7ef0 0xe7ef0 0xf4240>;
			opp-microvolt-L1 = <0xe1d48 0xe1d48 0xf4240>;
			opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240>;
			opp-microvolt-L3 = <0xd59f8 0xd59f8 0xf4240>;
		};

		opp-800000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x2faf0800>;
			opp-microvolt = <0xf4240 0xf4240 0xf4240>;
			opp-microvolt-L0 = <0xf4240 0xf4240 0xf4240>;
			opp-microvolt-L1 = <0xee098 0xee098 0xf4240>;
			opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0xf4240>;
			opp-microvolt-L3 = <0xe1d48 0xe1d48 0xf4240>;
		};

		opp-j-600000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xdbba0 0xdbba0 0xf4240>;
		};

		opp-m-800000000 {
			opp-supported-hw = <0x02 0xffff>;
			opp-hz = <0x00 0x2faf0800>;
			opp-microvolt = <0xe7ef0 0xe7ef0 0xf4240>;
		};
	};

	pvtm@fde80000 {
		compatible = "rockchip,rk3568-gpu-pvtm";
		reg = <0x00 0xfde80000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		pvtm@1 {
			reg = <0x01>;
			clocks = <0x23 0x1e 0x23 0x1d>;
			clock-names = "clk\0pclk";
			resets = <0x23 0x24 0x23 0x23>;
			reset-names = "rts\0rst-p";
			thermal-zone = "gpu-thermal";
		};
	};

	pvtm@fde90000 {
		compatible = "rockchip,rk3568-npu-pvtm";
		reg = <0x00 0xfde90000 0x00 0x100>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		pvtm@2 {
			reg = <0x02>;
			clocks = <0x23 0x2b 0x23 0x2a 0x23 0x25>;
			clock-names = "clk\0pclk\0hclk";
			resets = <0x23 0x2e 0x23 0x2d>;
			reset-names = "rts\0rst-p";
			thermal-zone = "soc-thermal";
		};
	};

	vdpu@fdea0400 {
		compatible = "rockchip,vpu-decoder-v2";
		reg = <0x00 0xfdea0400 0x00 0x400>;
		interrupts = <0x00 0x8b 0x04>;
		interrupt-names = "irq_dec";
		clocks = <0x23 0xee 0x23 0xef>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		resets = <0x23 0x11a 0x23 0x11b>;
		reset-names = "video_a\0video_h";
		iommus = <0x7a>;
		power-domains = <0x25 0x0b>;
		rockchip,srv = <0x7b>;
		rockchip,taskqueue-node = <0x00>;
		rockchip,resetgroup-node = <0x00>;
		status = "okay";
	};

	iommu@fdea0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdea0800 0x00 0x40>;
		interrupts = <0x00 0x8a 0x04>;
		interrupt-names = "vdpu_mmu";
		clock-names = "aclk\0iface";
		clocks = <0x23 0xee 0x23 0xef>;
		power-domains = <0x25 0x0b>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x7a>;
	};

	rk_rga@fdeb0000 {
		compatible = "rockchip,rga2";
		reg = <0x00 0xfdeb0000 0x00 0x1000>;
		interrupts = <0x00 0x5a 0x04>;
		clocks = <0x23 0xf3 0x23 0xf4 0x23 0xf5>;
		clock-names = "aclk_rga\0hclk_rga\0clk_rga";
		power-domains = <0x25 0x0a>;
		status = "okay";
	};

	ebc@fdec0000 {
		compatible = "rockchip,rk3568-ebc-tcon";
		reg = <0x00 0xfdec0000 0x00 0x5000>;
		interrupts = <0x00 0x11 0x04>;
		clocks = <0x23 0xf9 0x23 0xfa>;
		clock-names = "hclk\0dclk";
		power-domains = <0x25 0x0a>;
		rockchip,grf = <0x3b>;
		pinctrl-names = "default";
		pinctrl-0 = <0x7c>;
		status = "disabled";
	};

	jpegd@fded0000 {
		compatible = "rockchip,rkv-jpeg-decoder-v1";
		reg = <0x00 0xfded0000 0x00 0x400>;
		interrupts = <0x00 0x3e 0x04>;
		clocks = <0x23 0xfb 0x23 0xfc>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,disable-auto-freq;
		resets = <0x23 0x12c 0x23 0x12d>;
		reset-names = "video_a\0video_h";
		iommus = <0x7d>;
		rockchip,srv = <0x7b>;
		rockchip,taskqueue-node = <0x01>;
		rockchip,resetgroup-node = <0x01>;
		power-domains = <0x25 0x0a>;
		status = "okay";
	};

	iommu@fded0480 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfded0480 0x00 0x40>;
		interrupts = <0x00 0x3d 0x04>;
		interrupt-names = "jpegd_mmu";
		clock-names = "aclk\0iface";
		clocks = <0x23 0xfb 0x23 0xfc>;
		power-domains = <0x25 0x0a>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x7d>;
	};

	vepu@fdee0000 {
		compatible = "rockchip,vpu-encoder-v2";
		reg = <0x00 0xfdee0000 0x00 0x400>;
		interrupts = <0x00 0x40 0x04>;
		clocks = <0x23 0xfd 0x23 0xfe>;
		clock-names = "aclk_vcodec\0hclk_vcodec";
		rockchip,disable-auto-freq;
		resets = <0x23 0x12e 0x23 0x12f>;
		reset-names = "video_a\0video_h";
		iommus = <0x7e>;
		rockchip,srv = <0x7b>;
		rockchip,taskqueue-node = <0x02>;
		rockchip,resetgroup-node = <0x02>;
		power-domains = <0x25 0x0a>;
		status = "okay";
	};

	iommu@fdee0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdee0800 0x00 0x40>;
		interrupts = <0x00 0x3f 0x04>;
		interrupt-names = "vepu_mmu";
		clock-names = "aclk\0iface";
		clocks = <0x23 0xfd 0x23 0xfe>;
		power-domains = <0x25 0x0a>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x7e>;
	};

	iep@fdef0000 {
		compatible = "rockchip,iep-v2";
		reg = <0x00 0xfdef0000 0x00 0x500>;
		interrupts = <0x00 0x38 0x04>;
		clocks = <0x23 0xf6 0x23 0xf7 0x23 0xf8>;
		clock-names = "aclk\0hclk\0sclk";
		resets = <0x23 0x127 0x23 0x128 0x23 0x129>;
		reset-names = "rst_a\0rst_h\0rst_s";
		power-domains = <0x25 0x0a>;
		rockchip,srv = <0x7b>;
		rockchip,taskqueue-node = <0x05>;
		rockchip,resetgroup-node = <0x05>;
		iommus = <0x7f>;
		status = "okay";
	};

	iommu@fdef0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdef0800 0x00 0x100>;
		interrupts = <0x00 0x38 0x04>;
		interrupt-names = "iep_mmu";
		clocks = <0x23 0xf6 0x23 0xf7>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x25 0x0a>;
		status = "okay";
		phandle = <0x7f>;
	};

	eink@fdf00000 {
		compatible = "rockchip,rk3568-eink-tcon";
		reg = <0x00 0xfdf00000 0x00 0x74>;
		interrupts = <0x00 0xb2 0x04>;
		clocks = <0x23 0xff 0x23 0x100>;
		clock-names = "pclk\0hclk";
		status = "disabled";
	};

	rkvenc@fdf40000 {
		compatible = "rockchip,rkv-encoder-v1";
		reg = <0x00 0xfdf40000 0x00 0x400>;
		interrupts = <0x00 0x8c 0x04>;
		interrupt-names = "irq_enc";
		clocks = <0x23 0x103 0x23 0x104 0x23 0x105>;
		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core";
		rockchip,normal-rates = <0x11b3dc40 0x00 0x11b3dc40>;
		resets = <0x23 0x133 0x23 0x134 0x23 0x135>;
		reset-names = "video_a\0video_h\0video_core";
		assigned-clocks = <0x23 0x103 0x23 0x105>;
		assigned-clock-rates = <0x11b3dc40 0x11b3dc40>;
		iommus = <0x80>;
		node-name = "rkvenc";
		rockchip,srv = <0x7b>;
		rockchip,taskqueue-node = <0x03>;
		rockchip,resetgroup-node = <0x03>;
		power-domains = <0x25 0x0e>;
		operating-points-v2 = <0x81>;
		status = "okay";
		venc-supply = <0x75>;
	};

	rkvenc-opp-table {
		compatible = "operating-points-v2";
		nvmem-cells = <0x07>;
		nvmem-cell-names = "pvtm";
		rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x16378 0x01 0x16379 0x186a0 0x02>;
		rockchip,pvtm-ch = <0x00 0x05>;
		phandle = <0x81>;

		opp-297000000 {
			opp-hz = <0x00 0x11b3dc40>;
			opp-microvolt = <0xdbba0>;
			opp-microvolt-L0 = <0xdbba0>;
			opp-microvolt-L1 = <0xd59f8>;
			opp-microvolt-L2 = <0xd59f8>;
		};

		opp-400000000 {
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xe7ef0>;
			opp-microvolt-L0 = <0xe7ef0>;
			opp-microvolt-L1 = <0xe1d48>;
			opp-microvolt-L2 = <0xdbba0>;
		};
	};

	iommu@fdf40f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdf40f00 0x00 0x40 0x00 0xfdf40f40 0x00 0x40>;
		interrupts = <0x00 0x8d 0x04 0x00 0x8e 0x04>;
		interrupt-names = "rkvenc_mmu0\0rkvenc_mmu1";
		clocks = <0x23 0x103 0x23 0x104>;
		clock-names = "aclk\0iface";
		rockchip,disable-mmu-reset;
		rockchip,enable-cmd-retry;
		#iommu-cells = <0x00>;
		power-domains = <0x25 0x0e>;
		status = "okay";
		phandle = <0x80>;
	};

	rkvdec@fdf80200 {
		compatible = "rockchip,rkv-decoder-rk3568\0rockchip,rkv-decoder-v2";
		reg = <0x00 0xfdf80200 0x00 0x400 0x00 0xfdf80100 0x00 0x100>;
		reg-names = "regs\0link";
		interrupts = <0x00 0x5b 0x04>;
		interrupt-names = "irq_dec";
		clocks = <0x23 0x108 0x23 0x109 0x23 0x10a 0x23 0x10b 0x23 0x10c>;
		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_cabac\0clk_core\0clk_hevc_cabac";
		rockchip,normal-rates = <0x11b3dc40 0x00 0x11b3dc40 0x11b3dc40 0x23c34600>;
		rockchip,advanced-rates = <0x179a7b00 0x00 0x179a7b00 0x179a7b00 0x23c34600>;
		rockchip,default-max-load = <0x1fe000>;
		resets = <0x23 0x142 0x23 0x143 0x23 0x144 0x23 0x145 0x23 0x146>;
		assigned-clocks = <0x23 0x108 0x23 0x10a 0x23 0x10b 0x23 0x10c>;
		assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>;
		reset-names = "video_a\0video_h\0video_cabac\0video_core\0video_hevc_cabac";
		power-domains = <0x25 0x0d>;
		operating-points-v2 = <0x82>;
		vdec-supply = <0x75>;
		iommus = <0x83>;
		rockchip,srv = <0x7b>;
		rockchip,taskqueue-node = <0x04>;
		rockchip,resetgroup-node = <0x04>;
		rockchip,sram = <0x84>;
		rockchip,rcb-iova = <0x10000000 0x10000>;
		rockchip,rcb-min-width = <0x200>;
		rockchip,task-capacity = <0x10>;
		status = "okay";
	};

	rkvdec-opp-table {
		compatible = "operating-points-v2";
		nvmem-cells = <0x85 0x07>;
		nvmem-cell-names = "leakage\0pvtm";
		rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>;
		rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x186a0 0x01>;
		rockchip,pvtm-ch = <0x00 0x05>;
		phandle = <0x82>;

		opp-297000000 {
			opp-hz = <0x00 0x11b3dc40>;
			opp-microvolt = <0xdbba0>;
			opp-microvolt-L0 = <0xdbba0>;
			opp-microvolt-L1 = <0xd59f8>;
		};

		opp-400000000 {
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xdbba0>;
		};
	};

	iommu@fdf80800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdf80800 0x00 0x40 0x00 0xfdf80840 0x00 0x40>;
		interrupts = <0x00 0x5c 0x04>;
		interrupt-names = "rkvdec_mmu";
		clocks = <0x23 0x108 0x23 0x109>;
		clock-names = "aclk\0iface";
		power-domains = <0x25 0x0d>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x83>;
	};

	mipi-csi2-hw@fdfb0000 {
		compatible = "rockchip,rk3568-mipi-csi2-hw";
		reg = <0x00 0xfdfb0000 0x00 0x10000>;
		reg-names = "csihost_regs";
		interrupts = <0x00 0x08 0x04 0x00 0x09 0x04>;
		interrupt-names = "csi-intr1\0csi-intr2";
		clocks = <0x23 0xd5>;
		clock-names = "pclk_csi2host";
		resets = <0x23 0xff>;
		reset-names = "srst_csihost_p";
		status = "okay";
		phandle = <0x1e>;
	};

	rkcif@fdfe0000 {
		compatible = "rockchip,rk3568-cif";
		reg = <0x00 0xfdfe0000 0x00 0x8000>;
		reg-names = "cif_regs";
		interrupts = <0x00 0x92 0x04>;
		interrupt-names = "cif-intr";
		clocks = <0x23 0xce 0x23 0xcf 0x23 0xd0 0x23 0xd1>;
		clock-names = "aclk_cif\0hclk_cif\0dclk_cif\0iclk_cif_g";
		resets = <0x23 0xf7 0x23 0xf8 0x23 0xf9 0x23 0xfb 0x23 0xfa>;
		reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d\0rst_cif_p\0rst_cif_i";
		assigned-clocks = <0x23 0xd0>;
		assigned-clock-rates = <0x11e1a300>;
		power-domains = <0x25 0x08>;
		rockchip,grf = <0x3b>;
		iommus = <0x86>;
		status = "disabled";
		phandle = <0x87>;
	};

	iommu@fdfe0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdfe0800 0x00 0x100>;
		interrupts = <0x00 0x92 0x04>;
		interrupt-names = "cif_mmu";
		clocks = <0x23 0xce 0x23 0xcf>;
		clock-names = "aclk\0iface";
		power-domains = <0x25 0x08>;
		rockchip,disable-mmu-reset;
		#iommu-cells = <0x00>;
		status = "disabled";
		phandle = <0x86>;
	};

	rkcif_dvp {
		compatible = "rockchip,rkcif-dvp";
		rockchip,hw = <0x87>;
		status = "disabled";
		phandle = <0x88>;
	};

	rkcif_dvp_sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x88>;
		status = "disabled";
	};

	rkcif_mipi_lvds {
		compatible = "rockchip,rkcif-mipi-lvds";
		rockchip,hw = <0x87>;
		status = "disabled";
		phandle = <0x89>;
	};

	rkcif_mipi_lvds_sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <0x89>;
		status = "disabled";
	};

	rkisp@fdff0000 {
		compatible = "rockchip,rk3568-rkisp";
		reg = <0x00 0xfdff0000 0x00 0x10000>;
		interrupts = <0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x3c 0x04>;
		interrupt-names = "mipi_irq\0mi_irq\0isp_irq";
		clocks = <0x23 0xd2 0x23 0xd3 0x23 0xd4>;
		clock-names = "aclk_isp\0hclk_isp\0clk_isp";
		resets = <0x23 0xfd 0x23 0xfc>;
		reset-names = "isp\0isp-h";
		rockchip,grf = <0x3b>;
		power-domains = <0x25 0x08>;
		iommus = <0x8a>;
		rockchip,iq-feature = <0x1bfb 0xfffe67ff>;
		status = "okay";
		phandle = <0x8b>;
	};

	iommu@fdff1a00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfdff1a00 0x00 0x100>;
		interrupts = <0x00 0x3b 0x04>;
		interrupt-names = "isp_mmu";
		clocks = <0x23 0xd2 0x23 0xd3>;
		clock-names = "aclk\0iface";
		power-domains = <0x25 0x08>;
		#iommu-cells = <0x00>;
		rockchip,disable-mmu-reset;
		status = "okay";
		phandle = <0x8a>;
	};

	rkisp-vir0 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x8b>;
		status = "okay";

		port {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			endpoint@0 {
				reg = <0x00>;
				remote-endpoint = <0x8c>;
				phandle = <0x134>;
			};
		};
	};

	rkisp-vir1 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <0x8b>;
		status = "disabled";
	};

	uio@fe010000 {
		compatible = "rockchip,uio-gmac";
		reg = <0x00 0xfe010000 0x00 0x10000>;
		rockchip,ethernet = <0x8d>;
		status = "disabled";
	};

	ethernet@fe010000 {
		local-mac-address = [5e 4f fd 70 05 c6];
		compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a";
		reg = <0x00 0xfe010000 0x00 0x10000>;
		interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>;
		interrupt-names = "macirq\0eth_wake_irq";
		rockchip,grf = <0x3b>;
		clocks = <0x23 0x186 0x23 0x189 0x23 0x189 0x23 0xc7 0x23 0xc3 0x23 0xc4 0x23 0x189 0x23 0xc8 0x23 0xac 0x23 0xab>;
		clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs\0clk_xpcs_eee";
		resets = <0x23 0xec>;
		reset-names = "stmmaceth";
		snps,mixed-burst;
		snps,tso;
		snps,axi-config = <0x8e>;
		snps,mtl-rx-config = <0x8f>;
		snps,mtl-tx-config = <0x90>;
		status = "okay";
		phy-mode = "rgmii";
		clock_in_out = "input";
		snps,reset-gpio = <0x91 0x19 0x01>;
		snps,reset-active-low;
		snps,reset-delays-us = <0x00 0x4e20 0x186a0>;
		assigned-clocks = <0x23 0x189 0x23 0x186>;
		assigned-clock-parents = <0x23 0x187 0x92>;
		pinctrl-names = "default";
		pinctrl-0 = <0x93 0x94 0x95 0x96 0x97 0x98>;
		tx_delay = <0x3e>;
		rx_delay = <0x32>;
		phy-handle = <0x99>;
		phandle = <0x8d>;

		mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			phy@0 {
				compatible = "ethernet-phy-ieee802.3-c22";
				reg = <0x00>;
				led_status_value = <0x6940>;
				phandle = <0x99>;
			};
		};

		stmmac-axi-config {
			snps,wr_osr_lmt = <0x04>;
			snps,rd_osr_lmt = <0x08>;
			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
			phandle = <0x8e>;
		};

		rx-queues-config {
			snps,rx-queues-to-use = <0x01>;
			phandle = <0x8f>;

			queue0 {
			};
		};

		tx-queues-config {
			snps,tx-queues-to-use = <0x01>;
			phandle = <0x90>;

			queue0 {
			};
		};
	};

	vop@fe040000 {
		compatible = "rockchip,rk3568-vop";
		reg = <0x00 0xfe040000 0x00 0x3000 0x00 0xfe044000 0x00 0x1000>;
		reg-names = "regs\0gamma_lut";
		rockchip,grf = <0x3b>;
		interrupts = <0x00 0x94 0x04>;
		clocks = <0x23 0xdd 0x23 0xde 0x23 0xdf 0x23 0xe0 0x23 0xe1>;
		clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2";
		iommus = <0x9a>;
		power-domains = <0x25 0x09>;
		status = "okay";
		assigned-clocks = <0x23 0xdf 0x23 0xe0>;
		assigned-clock-parents = <0x3a 0x02 0x23 0x05>;
		disable-win-move;

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x15>;

			port@0 {
				rockchip,primary-plane = <0x04>;
				rockchip,plane-mask = <0x15>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				reg = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x9b>;
					phandle = <0x17>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0x9c>;
					phandle = <0x18>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0x9d>;
					phandle = <0x19>;
				};

				endpoint@3 {
					reg = <0x03>;
					remote-endpoint = <0x9e>;
					phandle = <0x1a>;
				};
			};

			port@1 {
				rockchip,primary-plane = <0x05>;
				rockchip,plane-mask = <0x22>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				reg = <0x01>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x9f>;
					phandle = <0xa8>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xa0>;
					phandle = <0xa9>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0xa1>;
					phandle = <0xaf>;
				};

				endpoint@3 {
					reg = <0x03>;
					remote-endpoint = <0xa2>;
					phandle = <0xad>;
				};

				endpoint@4 {
					reg = <0x04>;
					remote-endpoint = <0xa3>;
					phandle = <0x1b>;
				};

				endpoint@5 {
					reg = <0x05>;
					remote-endpoint = <0xa4>;
					phandle = <0x37>;
				};
			};

			port@2 {
				rockchip,primary-plane = <0x03>;
				rockchip,plane-mask = <0x08>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				reg = <0x02>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xa5>;
					phandle = <0x35>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xa6>;
					phandle = <0x1c>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0xa7>;
					phandle = <0x38>;
				};
			};
		};
	};

	iommu@fe043e00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x00 0xfe043e00 0x00 0x100 0x00 0xfe043f00 0x00 0x100>;
		interrupts = <0x00 0x94 0x04>;
		interrupt-names = "vop_mmu";
		clocks = <0x23 0xdd 0x23 0xde>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		rockchip,disable-device-link-resume;
		status = "okay";
		phandle = <0x9a>;
	};

	dsi@fe060000 {
		compatible = "rockchip,rk3568-mipi-dsi";
		reg = <0x00 0xfe060000 0x00 0x10000>;
		interrupts = <0x00 0x44 0x04>;
		clocks = <0x23 0xe8 0x23 0xda>;
		clock-names = "pclk\0hclk";
		resets = <0x23 0x110>;
		reset-names = "apb";
		phys = <0x34>;
		phy-names = "dphy";
		power-domains = <0x25 0x09>;
		rockchip,grf = <0x3b>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x17>;
					status = "disabled";
					phandle = <0x9b>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xa8>;
					status = "disabled";
					phandle = <0x9f>;
				};
			};
		};
	};

	dsi@fe070000 {
		compatible = "rockchip,rk3568-mipi-dsi";
		reg = <0x00 0xfe070000 0x00 0x10000>;
		interrupts = <0x00 0x45 0x04>;
		clocks = <0x23 0xe9 0x23 0xda>;
		clock-names = "pclk\0hclk";
		resets = <0x23 0x111>;
		reset-names = "apb";
		phys = <0x36>;
		phy-names = "dphy";
		power-domains = <0x25 0x09>;
		rockchip,grf = <0x3b>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x18>;
					status = "disabled";
					phandle = <0x9c>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xa9>;
					status = "disabled";
					phandle = <0xa0>;
				};
			};
		};
	};

	hdmi@fe0a0000 {
		compatible = "rockchip,rk3568-dw-hdmi";
		reg = <0x00 0xfe0a0000 0x00 0x20000>;
		interrupts = <0x00 0x2d 0x04>;
		clocks = <0x23 0xe6 0x23 0xe7 0x23 0x193 0x3a 0x02 0x23 0xde>;
		clock-names = "iahb\0isfr\0cec\0ref\0hclk";
		power-domains = <0x25 0x09>;
		reg-io-width = <0x04>;
		rockchip,grf = <0x3b>;
		#sound-dai-cells = <0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xaa 0xab 0xac>;
		status = "okay";
		phandle = <0x147>;

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x1a>;
					status = "okay";
					phandle = <0x9e>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xad>;
					status = "disabled";
					phandle = <0xa2>;
				};
			};
		};
	};

	edp@fe0c0000 {
		compatible = "rockchip,rk3568-edp";
		reg = <0x00 0xfe0c0000 0x00 0x10000>;
		interrupts = <0x00 0x12 0x04>;
		clocks = <0x3a 0x29 0x23 0xea 0x23 0xeb 0x23 0xda>;
		clock-names = "dp\0pclk\0spdif\0hclk";
		resets = <0x23 0x113 0x23 0x112>;
		reset-names = "dp\0apb";
		phys = <0xae>;
		phy-names = "dp";
		power-domains = <0x25 0x09>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x19>;
					status = "disabled";
					phandle = <0x9d>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xaf>;
					status = "disabled";
					phandle = <0xa1>;
				};
			};
		};
	};

	nocp-cpu@fe102000 {
		compatible = "rockchip,rk3568-nocp";
		reg = <0x00 0xfe102000 0x00 0x400>;
		phandle = <0xb5>;
	};

	nocp-gpu-vpu-rga-venc@fe102400 {
		compatible = "rockchip,rk3568-nocp";
		reg = <0x00 0xfe102400 0x00 0x400>;
	};

	nocp-vdec@fe102800 {
		compatible = "rockchip,rk3568-nocp";
		reg = <0x00 0xfe102800 0x00 0x400>;
	};

	nocp-vi-usb-peri-pipe@fe102c00 {
		compatible = "rockchip,rk3568-nocp";
		reg = <0x00 0xfe102c00 0x00 0x400>;
	};

	nocp-vo@fe103000 {
		compatible = "rockchip,rk3568-nocp";
		reg = <0x00 0xfe103000 0x00 0x400>;
	};

	qos@fe128000 {
		compatible = "syscon";
		reg = <0x00 0xfe128000 0x00 0x20>;
		phandle = <0x55>;
	};

	qos@fe138080 {
		compatible = "syscon";
		reg = <0x00 0xfe138080 0x00 0x20>;
		phandle = <0x64>;
	};

	qos@fe138100 {
		compatible = "syscon";
		reg = <0x00 0xfe138100 0x00 0x20>;
		phandle = <0x65>;
	};

	qos@fe138180 {
		compatible = "syscon";
		reg = <0x00 0xfe138180 0x00 0x20>;
		phandle = <0x66>;
	};

	qos@fe148000 {
		compatible = "syscon";
		reg = <0x00 0xfe148000 0x00 0x20>;
		phandle = <0x56>;
	};

	qos@fe148080 {
		compatible = "syscon";
		reg = <0x00 0xfe148080 0x00 0x20>;
		phandle = <0x57>;
	};

	qos@fe148100 {
		compatible = "syscon";
		reg = <0x00 0xfe148100 0x00 0x20>;
		phandle = <0x58>;
	};

	qos@fe150000 {
		compatible = "syscon";
		reg = <0x00 0xfe150000 0x00 0x20>;
		phandle = <0x62>;
	};

	qos@fe158000 {
		compatible = "syscon";
		reg = <0x00 0xfe158000 0x00 0x20>;
		phandle = <0x5c>;
	};

	qos@fe158100 {
		compatible = "syscon";
		reg = <0x00 0xfe158100 0x00 0x20>;
		phandle = <0x5d>;
	};

	qos@fe158180 {
		compatible = "syscon";
		reg = <0x00 0xfe158180 0x00 0x20>;
		phandle = <0x5e>;
	};

	qos@fe158200 {
		compatible = "syscon";
		reg = <0x00 0xfe158200 0x00 0x20>;
		phandle = <0x5f>;
	};

	qos@fe158280 {
		compatible = "syscon";
		reg = <0x00 0xfe158280 0x00 0x20>;
		phandle = <0x60>;
	};

	qos@fe158300 {
		compatible = "syscon";
		reg = <0x00 0xfe158300 0x00 0x20>;
		phandle = <0x61>;
	};

	qos@fe180000 {
		compatible = "syscon";
		reg = <0x00 0xfe180000 0x00 0x20>;
		phandle = <0x54>;
	};

	qos@fe190000 {
		compatible = "syscon";
		reg = <0x00 0xfe190000 0x00 0x20>;
		phandle = <0x67>;
	};

	qos@fe190080 {
		compatible = "syscon";
		reg = <0x00 0xfe190080 0x00 0x20>;
		phandle = <0x68>;
	};

	qos@fe190100 {
		compatible = "syscon";
		reg = <0x00 0xfe190100 0x00 0x20>;
		phandle = <0x69>;
	};

	qos@fe190200 {
		compatible = "syscon";
		reg = <0x00 0xfe190200 0x00 0x20>;
		phandle = <0x6a>;
	};

	qos@fe190280 {
		compatible = "syscon";
		reg = <0x00 0xfe190280 0x00 0x20>;
		phandle = <0x6b>;
	};

	qos@fe190300 {
		compatible = "syscon";
		reg = <0x00 0xfe190300 0x00 0x20>;
		phandle = <0x6c>;
	};

	qos@fe190380 {
		compatible = "syscon";
		reg = <0x00 0xfe190380 0x00 0x20>;
		phandle = <0x6d>;
	};

	qos@fe190400 {
		compatible = "syscon";
		reg = <0x00 0xfe190400 0x00 0x20>;
		phandle = <0x6e>;
	};

	qos@fe198000 {
		compatible = "syscon";
		reg = <0x00 0xfe198000 0x00 0x20>;
		phandle = <0x63>;
	};

	qos@fe1a8000 {
		compatible = "syscon";
		reg = <0x00 0xfe1a8000 0x00 0x20>;
		phandle = <0x59>;
	};

	qos@fe1a8080 {
		compatible = "syscon";
		reg = <0x00 0xfe1a8080 0x00 0x20>;
		phandle = <0x5a>;
	};

	qos@fe1a8100 {
		compatible = "syscon";
		reg = <0x00 0xfe1a8100 0x00 0x20>;
		phandle = <0x5b>;
	};

	dwmmc@fe000000 {
		compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe000000 0x00 0x4000>;
		interrupts = <0x00 0x64 0x04>;
		max-frequency = <0x8f0d180>;
		clocks = <0x23 0xc1 0x23 0xc2 0x23 0x18e 0x23 0x18f>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		resets = <0x23 0xeb>;
		reset-names = "reset";
		status = "okay";
		no-sd;
		no-mmc;
		bus-width = <0x04>;
		disable-wp;
		cap-sd-highspeed;
		cap-sdio-irq;
		keep-power-in-suspend;
		pinctrl-names = "default";
		pinctrl-0 = <0xb0 0xb1 0xb2>;
		sd-uhs-sdr104;
		mmc-pwrseq = <0xb3>;
		non-removable;
	};

	dfi@fe230000 {
		reg = <0x00 0xfe230000 0x00 0x400>;
		compatible = "rockchip,rk3568-dfi";
		rockchip,pmugrf = <0x3c>;
		status = "okay";
		phandle = <0xb4>;
	};

	dmc {
		compatible = "rockchip,rk3568-dmc";
		interrupts = <0x00 0x0a 0x04>;
		interrupt-names = "complete";
		devfreq-events = <0xb4 0xb5>;
		clocks = <0x02 0x03>;
		clock-names = "dmc_clk";
		operating-points-v2 = <0xb6>;
		vop-bw-dmc-freq = <0x00 0x11e 0x4f1a0 0x11f 0x1869f 0x80e80>;
		vop-frame-bw-dmc-freq = <0x00 0x26c 0x4f1a0 0x26d 0x1869f 0xbe6e0>;
		cpu-bw-dmc-freq = <0x00 0x15e 0x4f1a0 0x15f 0x190 0x80e80 0x191 0x1869f 0xbe6e0>;
		upthreshold = <0x28>;
		downdifferential = <0x14>;
		system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08>;
		auto-min-freq = <0x4f1a0>;
		auto-freq-en = <0x01>;
		#cooling-cells = <0x02>;
		status = "okay";
		center-supply = <0x75>;
		phandle = <0x16>;
	};

	dmc-fsp {
		compatible = "rockchip,rk3568-dmc-fsp";
		debug_print_level = <0x00>;
		ddr3_params = <0xb7>;
		ddr4_params = <0xb8>;
		lpddr3_params = <0xb9>;
		lpddr4_params = <0xba>;
		lpddr4x_params = <0xbb>;
		status = "okay";
	};

	dmc-opp-table {
		compatible = "operating-points-v2";
		mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
		nvmem-cells = <0x85 0x07 0x08 0xbc 0x0a 0x0b>;
		nvmem-cell-names = "leakage\0pvtm\0mbist-vmin\0opp-info\0specification_serial_number\0remark_spec_serial_number";
		rockchip,supported-hw;
		rockchip,max-volt = <0xf4240>;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x00>;
		rockchip,low-temp-adjust-volt = <0x00 0x618 0x124f8>;
		rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>;
		rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x186a0 0x01>;
		rockchip,pvtm-ch = <0x00 0x05>;
		phandle = <0xb6>;

		opp-1560000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = <0x00 0x5cfbb600>;
			opp-microvolt = <0xdbba0 0xdbba0 0xf4240>;
			opp-microvolt-L0 = <0xdbba0 0xdbba0 0xf4240>;
			opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240>;
		};

		opp-j-m-1560000000 {
			opp-supported-hw = <0x06 0xffff>;
			opp-hz = <0x00 0x5cfbb600>;
			opp-microvolt = <0xd59f8 0xd59f8 0xf4240>;
		};
	};

	pcie@fe260000 {
		compatible = "rockchip,rk3568-pcie\0snps,dw-pcie";
		#address-cells = <0x03>;
		#size-cells = <0x02>;
		bus-range = <0x00 0x0f>;
		clocks = <0x23 0x81 0x23 0x82 0x23 0x83 0x23 0x84 0x23 0x85>;
		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux";
		device_type = "pci";
		interrupts = <0x00 0x4b 0x04 0x00 0x4a 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x47 0x04>;
		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
		#interrupt-cells = <0x01>;
		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
		interrupt-map = <0x00 0x00 0x00 0x01 0xbd 0x00 0x00 0x00 0x00 0x02 0xbd 0x01 0x00 0x00 0x00 0x03 0xbd 0x02 0x00 0x00 0x00 0x04 0xbd 0x03>;
		linux,pci-domain = <0x00>;
		num-ib-windows = <0x06>;
		num-viewport = <0x08>;
		num-ob-windows = <0x02>;
		max-link-speed = <0x02>;
		msi-map = <0x00 0xbe 0x00 0x1000>;
		num-lanes = <0x01>;
		phys = <0x27 0x02>;
		phy-names = "pcie-phy";
		power-domains = <0x25 0x0f>;
		ranges = <0x800 0x00 0xf4000000 0x00 0xf4000000 0x00 0x100000 0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0x1e00000 0xc3000000 0x03 0x00 0x03 0x00 0x00 0x40000000>;
		reg = <0x03 0xc0000000 0x00 0x400000 0x00 0xfe260000 0x00 0x10000>;
		reg-names = "pcie-dbi\0pcie-apb";
		resets = <0x23 0xa1>;
		reset-names = "pipe";
		status = "disabled";

		legacy-interrupt-controller {
			interrupt-controller;
			#address-cells = <0x00>;
			#interrupt-cells = <0x01>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x48 0x01>;
			phandle = <0xbd>;
		};
	};

	pcie@fe270000 {
		compatible = "rockchip,rk3568-pcie\0snps,dw-pcie";
		#address-cells = <0x03>;
		#size-cells = <0x02>;
		bus-range = <0x10 0x1f>;
		clocks = <0x23 0x88 0x23 0x89 0x23 0x8a 0x23 0x8b 0x23 0x8c>;
		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux";
		device_type = "pci";
		interrupts = <0x00 0xa0 0x04 0x00 0x9f 0x04 0x00 0x9e 0x04 0x00 0x9d 0x04 0x00 0x9c 0x04>;
		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
		#interrupt-cells = <0x01>;
		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
		interrupt-map = <0x00 0x00 0x00 0x01 0xbf 0x00 0x00 0x00 0x00 0x02 0xbf 0x01 0x00 0x00 0x00 0x03 0xbf 0x02 0x00 0x00 0x00 0x04 0xbf 0x03>;
		linux,pci-domain = <0x01>;
		num-ib-windows = <0x06>;
		num-ob-windows = <0x02>;
		num-viewport = <0x08>;
		max-link-speed = <0x03>;
		msi-map = <0x1000 0xbe 0x1000 0x1000>;
		num-lanes = <0x01>;
		phys = <0xc0>;
		phy-names = "pcie-phy";
		power-domains = <0x25 0x0f>;
		ranges = <0x800 0x00 0xf2000000 0x00 0xf2000000 0x00 0x100000 0x81000000 0x00 0xf2100000 0x00 0xf2100000 0x00 0x100000 0x82000000 0x00 0xf2200000 0x00 0xf2200000 0x00 0x1e00000 0xc3000000 0x03 0x40000000 0x03 0x40000000 0x00 0x40000000>;
		reg = <0x03 0xc0400000 0x00 0x400000 0x00 0xfe270000 0x00 0x10000>;
		reg-names = "pcie-dbi\0pcie-apb";
		resets = <0x23 0xb1>;
		reset-names = "pipe";
		status = "disabled";

		legacy-interrupt-controller {
			interrupt-controller;
			#address-cells = <0x00>;
			#interrupt-cells = <0x01>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0x9d 0x01>;
			phandle = <0xbf>;
		};
	};

	pcie@fe280000 {
		compatible = "rockchip,rk3568-pcie\0snps,dw-pcie";
		#address-cells = <0x03>;
		#size-cells = <0x02>;
		bus-range = <0x20 0x2f>;
		clocks = <0x23 0x8f 0x23 0x90 0x23 0x91 0x23 0x92 0x23 0x93>;
		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux";
		device_type = "pci";
		interrupts = <0x00 0xa5 0x04 0x00 0xa4 0x04 0x00 0xa3 0x04 0x00 0xa2 0x04 0x00 0xa1 0x04>;
		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
		#interrupt-cells = <0x01>;
		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
		interrupt-map = <0x00 0x00 0x00 0x01 0xc1 0x00 0x00 0x00 0x00 0x02 0xc1 0x01 0x00 0x00 0x00 0x03 0xc1 0x02 0x00 0x00 0x00 0x04 0xc1 0x03>;
		linux,pci-domain = <0x02>;
		num-ib-windows = <0x06>;
		num-viewport = <0x08>;
		num-ob-windows = <0x02>;
		max-link-speed = <0x03>;
		msi-map = <0x2000 0xbe 0x2000 0x1000>;
		num-lanes = <0x02>;
		phys = <0xc0>;
		phy-names = "pcie-phy";
		power-domains = <0x25 0x0f>;
		ranges = <0x800 0x00 0xf0000000 0x00 0xf0000000 0x00 0x100000 0x81000000 0x00 0xf0100000 0x00 0xf0100000 0x00 0x100000 0x82000000 0x00 0xf0200000 0x00 0xf0200000 0x00 0x1e00000 0xc3000000 0x03 0x80000000 0x03 0x80000000 0x00 0x40000000>;
		reg = <0x03 0xc0800000 0x00 0x400000 0x00 0xfe280000 0x00 0x10000>;
		reg-names = "pcie-dbi\0pcie-apb";
		resets = <0x23 0xc1>;
		reset-names = "pipe";
		status = "okay";
		reset-gpios = <0x91 0x1e 0x00>;
		vpcie3v3-supply = <0xc2>;

		legacy-interrupt-controller {
			interrupt-controller;
			#address-cells = <0x00>;
			#interrupt-cells = <0x01>;
			interrupt-parent = <0x01>;
			interrupts = <0x00 0xa2 0x01>;
			phandle = <0xc1>;
		};
	};

	uio@fe2a0000 {
		compatible = "rockchip,uio-gmac";
		reg = <0x00 0xfe2a0000 0x00 0x10000>;
		rockchip,ethernet = <0xc3>;
		status = "disabled";
	};

	ethernet@fe2a0000 {
		local-mac-address = [5a 4f fd 70 05 c6];
		compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a";
		reg = <0x00 0xfe2a0000 0x00 0x10000>;
		interrupts = <0x00 0x1b 0x04 0x00 0x18 0x04>;
		interrupt-names = "macirq\0eth_wake_irq";
		rockchip,grf = <0x3b>;
		clocks = <0x23 0x182 0x23 0x185 0x23 0x185 0x23 0xb8 0x23 0xb4 0x23 0xb5 0x23 0x185 0x23 0xb9 0x23 0xac 0x23 0xab>;
		clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs\0clk_xpcs_eee";
		resets = <0x23 0xd7>;
		reset-names = "stmmaceth";
		snps,mixed-burst;
		snps,tso;
		snps,axi-config = <0xc4>;
		snps,mtl-rx-config = <0xc5>;
		snps,mtl-tx-config = <0xc6>;
		status = "okay";
		phy-mode = "rgmii";
		clock_in_out = "input";
		snps,reset-gpio = <0x91 0x1b 0x01>;
		snps,reset-active-low;
		snps,reset-delays-us = <0x00 0x4e20 0x186a0>;
		assigned-clocks = <0x23 0x185 0x23 0x182>;
		assigned-clock-parents = <0x23 0x183 0xc7>;
		pinctrl-names = "default";
		pinctrl-0 = <0xc8 0xc9 0xca 0xcb 0xcc 0xcd>;
		tx_delay = <0x4a>;
		rx_delay = <0x2e>;
		phy-handle = <0xce>;
		phandle = <0xc3>;

		mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			phy@0 {
				compatible = "ethernet-phy-ieee802.3-c22";
				reg = <0x00>;
				led_status_value = <0x6940>;
				phandle = <0xce>;
			};
		};

		stmmac-axi-config {
			snps,wr_osr_lmt = <0x04>;
			snps,rd_osr_lmt = <0x08>;
			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
			phandle = <0xc4>;
		};

		rx-queues-config {
			snps,rx-queues-to-use = <0x01>;
			phandle = <0xc5>;

			queue0 {
			};
		};

		tx-queues-config {
			snps,tx-queues-to-use = <0x01>;
			phandle = <0xc6>;

			queue0 {
			};
		};
	};

	dwmmc@fe2b0000 {
		compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe2b0000 0x00 0x4000>;
		interrupts = <0x00 0x62 0x04>;
		max-frequency = <0x8f0d180>;
		clocks = <0x23 0xb0 0x23 0xb1 0x23 0x18a 0x23 0x18b>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		resets = <0x23 0xd4>;
		reset-names = "reset";
		status = "okay";
		no-sdio;
		no-mmc;
		bus-width = <0x04>;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		disable-wp;
		sd-uhs-sdr104;
		vmmc-supply = <0xcf>;
		vqmmc-supply = <0x31>;
		pinctrl-names = "default";
		pinctrl-0 = <0xd0 0xd1 0xd2 0xd3>;
	};

	dwmmc@fe2c0000 {
		compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe2c0000 0x00 0x4000>;
		interrupts = <0x00 0x63 0x04>;
		max-frequency = <0x8f0d180>;
		clocks = <0x23 0xb2 0x23 0xb3 0x23 0x18c 0x23 0x18d>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		resets = <0x23 0xd6>;
		reset-names = "reset";
		status = "disabled";
	};

	spi@fe300000 {
		compatible = "rockchip,sfc";
		reg = <0x00 0xfe300000 0x00 0x4000>;
		interrupts = <0x00 0x65 0x04>;
		clocks = <0x23 0x78 0x23 0x76>;
		clock-names = "clk_sfc\0hclk_sfc";
		assigned-clocks = <0x23 0x78>;
		assigned-clock-rates = <0x2faf080>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <0xd4>;

		flash@0 {
			compatible = "jedec,spi-nor";
			reg = <0x00>;
			spi-max-frequency = <0x2faf080>;
			spi-rx-bus-width = <0x01>;
			spi-tx-bus-width = <0x01>;
		};
	};

	sdhci@fe310000 {
		compatible = "rockchip,rk3568-dwcmshc\0rockchip,dwcmshc-sdhci";
		reg = <0x00 0xfe310000 0x00 0x10000>;
		interrupts = <0x00 0x13 0x04>;
		assigned-clocks = <0x23 0x7b 0x23 0x7d 0x23 0x7c>;
		assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>;
		clocks = <0x23 0x7c 0x23 0x7a 0x23 0x79 0x23 0x7b 0x23 0x7d>;
		clock-names = "core\0bus\0axi\0block\0timer";
		resets = <0x23 0x78 0x23 0x76 0x23 0x75 0x23 0x77 0x23 0x79>;
		reset-names = "core\0bus\0axi\0block\0timer";
		status = "okay";
		bus-width = <0x08>;
		no-sdio;
		no-sd;
		non-removable;
		max-frequency = <0xbebc200>;
		full-pwr-cycle-in-suspend;
	};

	nandc@fe330000 {
		compatible = "rockchip,rk-nandc-v9";
		reg = <0x00 0xfe330000 0x00 0x4000>;
		interrupts = <0x00 0x46 0x04>;
		nandc_id = <0x00>;
		clocks = <0x23 0x75 0x23 0x74>;
		clock-names = "clk_nandc\0hclk_nandc";
		status = "okay";
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		nand@0 {
			reg = <0x00>;
			nand-bus-width = <0x08>;
			nand-ecc-mode = "hw";
			nand-ecc-strength = <0x10>;
			nand-ecc-step-size = <0x400>;
		};
	};

	crypto@fe380000 {
		compatible = "rockchip,rk3568-crypto";
		reg = <0x00 0xfe380000 0x00 0x4000>;
		interrupts = <0x00 0x04 0x04>;
		clocks = <0x23 0x6a 0x23 0x6b 0x23 0x6c 0x23 0x6d>;
		clock-names = "aclk\0hclk\0sclk\0apb_pclk";
		assigned-clocks = <0x23 0x6c>;
		assigned-clock-rates = <0xbebc200>;
		resets = <0x23 0x69>;
		reset-names = "crypto-rst";
		status = "disabled";
	};

	rng@fe388000 {
		compatible = "rockchip,cryptov2-rng";
		reg = <0x00 0xfe388000 0x00 0x2000>;
		clocks = <0x23 0x70 0x23 0x6f>;
		clock-names = "clk_trng\0hclk_trng";
		resets = <0x23 0x6d>;
		reset-names = "reset";
		status = "okay";
	};

	otp@fe38c000 {
		compatible = "rockchip,rk3568-otp";
		reg = <0x00 0xfe38c000 0x00 0x4000>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		clocks = <0x23 0x73 0x23 0x72 0x23 0x71 0x23 0x181>;
		clock-names = "usr\0sbpi\0apb\0phy";
		resets = <0x23 0x1cf>;
		reset-names = "otp_phy";

		cpu-code@2 {
			reg = <0x02 0x02>;
			phandle = <0x12>;
		};

		specification-serial-number@7 {
			reg = <0x07 0x01>;
			bits = <0x00 0x05>;
			phandle = <0x0a>;
		};

		cpu-version@8 {
			reg = <0x08 0x01>;
			bits = <0x03 0x03>;
			phandle = <0x11>;
		};

		mbist-vmin@9 {
			reg = <0x09 0x01>;
			bits = <0x00 0x04>;
			phandle = <0x08>;
		};

		id@a {
			reg = <0x0a 0x10>;
			phandle = <0x10>;
		};

		cpu-leakage@1a {
			reg = <0x1a 0x01>;
			phandle = <0x06>;
		};

		log-leakage@1b {
			reg = <0x1b 0x01>;
			phandle = <0x85>;
		};

		npu-leakage@1c {
			reg = <0x1c 0x01>;
			phandle = <0x72>;
		};

		gpu-leakage@1d {
			reg = <0x1d 0x01>;
			phandle = <0x78>;
		};

		core-pvtm@2a {
			reg = <0x2a 0x02>;
			phandle = <0x07>;
		};

		cpu-tsadc-trim-l@2e {
			reg = <0x2e 0x01>;
			phandle = <0x125>;
		};

		cpu-tsadc-trim-h@2f {
			reg = <0x2f 0x01>;
			bits = <0x00 0x04>;
			phandle = <0x126>;
		};

		npu-tsadc-trim-l@30 {
			reg = <0x30 0x01>;
			phandle = <0x127>;
		};

		npu-tsadc-trim-h@31 {
			reg = <0x31 0x01>;
			bits = <0x00 0x04>;
			phandle = <0x128>;
		};

		tsadc-trim-base-frac@31 {
			reg = <0x31 0x01>;
			bits = <0x04 0x04>;
			phandle = <0x122>;
		};

		tsadc-trim-base@32 {
			reg = <0x32 0x01>;
			phandle = <0x121>;
		};

		cpu-opp-info@36 {
			reg = <0x36 0x06>;
			phandle = <0x09>;
		};

		gpu-opp-info@3c {
			reg = <0x3c 0x06>;
			phandle = <0x79>;
		};

		npu-opp-info@42 {
			reg = <0x42 0x06>;
			phandle = <0x73>;
		};

		dmc-opp-info@48 {
			reg = <0x48 0x06>;
			phandle = <0xbc>;
		};

		remark-spec-serial-number@56 {
			reg = <0x56 0x01>;
			bits = <0x00 0x05>;
			phandle = <0x0b>;
		};
	};

	i2s@fe400000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x00 0xfe400000 0x00 0x1000>;
		interrupts = <0x00 0x34 0x04>;
		clocks = <0x23 0x3f 0x23 0x43 0x23 0x39>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		dmas = <0xd5 0x00>;
		dma-names = "tx";
		resets = <0x23 0x50 0x23 0x51>;
		reset-names = "tx-m\0rx-m";
		rockchip,cru = <0x23>;
		rockchip,grf = <0x3b>;
		rockchip,playback-only;
		#sound-dai-cells = <0x00>;
		status = "okay";
		phandle = <0x146>;
	};

	i2s@fe410000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x00 0xfe410000 0x00 0x1000>;
		interrupts = <0x00 0x35 0x04>;
		clocks = <0x23 0x47 0x23 0x4b 0x23 0x3a>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		dmas = <0xd5 0x02 0xd5 0x03>;
		dma-names = "tx\0rx";
		resets = <0x23 0x52 0x23 0x53>;
		reset-names = "tx-m\0rx-m";
		rockchip,cru = <0x23>;
		rockchip,grf = <0x3b>;
		#sound-dai-cells = <0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xd6 0xd7 0xd8 0xd9>;
		status = "okay";
		rockchip,clk-trcm = <0x01>;
		phandle = <0xe8>;
	};

	i2s@fe420000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x00 0xfe420000 0x00 0x1000>;
		interrupts = <0x00 0x36 0x04>;
		clocks = <0x23 0x4f 0x23 0x4f 0x23 0x3b>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		dmas = <0xd5 0x04 0xd5 0x05>;
		dma-names = "tx\0rx";
		rockchip,cru = <0x23>;
		rockchip,grf = <0x3b>;
		rockchip,clk-trcm = <0x01>;
		#sound-dai-cells = <0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xda 0xdb 0xdc 0xdd>;
		status = "disabled";
	};

	i2s@fe430000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x00 0xfe430000 0x00 0x1000>;
		interrupts = <0x00 0x37 0x04>;
		clocks = <0x23 0x53 0x23 0x57 0x23 0x3c>;
		clock-names = "mclk_tx\0mclk_rx\0hclk";
		dmas = <0xd5 0x06 0xd5 0x07>;
		dma-names = "tx\0rx";
		resets = <0x23 0x55 0x23 0x56>;
		reset-names = "tx-m\0rx-m";
		rockchip,cru = <0x23>;
		rockchip,grf = <0x3b>;
		rockchip,clk-trcm = <0x01>;
		#sound-dai-cells = <0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xde 0xdf 0xe0 0xe1>;
		status = "disabled";
		phandle = <0x144>;
	};

	pdm@fe440000 {
		compatible = "rockchip,rk3568-pdm\0rockchip,pdm";
		reg = <0x00 0xfe440000 0x00 0x1000>;
		clocks = <0x23 0x5a 0x23 0x59>;
		clock-names = "pdm_clk\0pdm_hclk";
		dmas = <0xd5 0x09>;
		dma-names = "rx";
		pinctrl-names = "default";
		pinctrl-0 = <0xe2 0xe3 0xe4 0xe5 0xe6 0xe7>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
		phandle = <0x149>;
	};

	vad@fe450000 {
		compatible = "rockchip,rk3568-vad";
		reg = <0x00 0xfe450000 0x00 0x10000>;
		reg-names = "vad";
		clocks = <0x23 0x5b>;
		clock-names = "hclk";
		interrupts = <0x00 0x89 0x04>;
		rockchip,audio-src = <0xe8>;
		rockchip,det-channel = <0x00>;
		rockchip,mode = <0x00>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
		rockchip,buffer-time-ms = <0x80>;
		phandle = <0x14e>;
	};

	spdif@fe460000 {
		compatible = "rockchip,rk3568-spdif";
		reg = <0x00 0xfe460000 0x00 0x1000>;
		interrupts = <0x00 0x66 0x04>;
		dmas = <0xd5 0x01>;
		dma-names = "tx";
		clock-names = "mclk\0hclk";
		clocks = <0x23 0x5f 0x23 0x5c>;
		#sound-dai-cells = <0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xe9>;
		status = "disabled";
		phandle = <0x14c>;
	};

	audpwm@fe470000 {
		compatible = "rockchip,rk3568-audio-pwm\0rockchip,audio-pwm-v1";
		reg = <0x00 0xfe470000 0x00 0x1000>;
		clocks = <0x23 0x63 0x23 0x60>;
		clock-names = "clk\0hclk";
		dmas = <0xd5 0x08>;
		dma-names = "tx";
		#sound-dai-cells = <0x00>;
		rockchip,sample-width-bits = <0x0b>;
		rockchip,interpolat-points = <0x01>;
		status = "disabled";
	};

	codec-digital@fe478000 {
		compatible = "rockchip,rk3568-codec-digital\0rockchip,codec-digital-v1";
		reg = <0x00 0xfe478000 0x00 0x1000>;
		clocks = <0x23 0x67 0x23 0x66 0x23 0x65 0x23 0x64>;
		clock-names = "adc\0dac\0i2c\0pclk";
		pinctrl-names = "default";
		pinctrl-0 = <0xea>;
		resets = <0x23 0x5f>;
		reset-names = "reset";
		rockchip,grf = <0x3b>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
		phandle = <0x145>;
	};

	dmac@fe530000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xfe530000 0x00 0x4000>;
		interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04>;
		clocks = <0x23 0x10d>;
		clock-names = "apb_pclk";
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		phandle = <0x4e>;
	};

	dmac@fe550000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xfe550000 0x00 0x4000>;
		interrupts = <0x00 0x10 0x04 0x00 0x0f 0x04>;
		clocks = <0x23 0x10d>;
		clock-names = "apb_pclk";
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		phandle = <0xd5>;
	};

	rkscr@fe560000 {
		compatible = "rockchip-scr";
		reg = <0x00 0xfe560000 0x00 0x10000>;
		interrupts = <0x00 0x61 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0xeb>;
		clocks = <0x23 0x114>;
		clock-names = "g_pclk_sim_card";
		status = "disabled";
	};

	can@fe570000 {
		compatible = "rockchip,rk3568-can-2.0";
		reg = <0x00 0xfe570000 0x00 0x1000>;
		interrupts = <0x00 0x01 0x04>;
		clocks = <0x23 0x141 0x23 0x140>;
		clock-names = "baudclk\0apb_pclk";
		resets = <0x23 0x155 0x23 0x154>;
		reset-names = "can\0can-apb";
		tx-fifo-depth = <0x01>;
		rx-fifo-depth = <0x06>;
		status = "disabled";
	};

	can@fe580000 {
		compatible = "rockchip,rk3568-can-2.0";
		reg = <0x00 0xfe580000 0x00 0x1000>;
		interrupts = <0x00 0x02 0x04>;
		clocks = <0x23 0x143 0x23 0x142>;
		clock-names = "baudclk\0apb_pclk";
		resets = <0x23 0x157 0x23 0x156>;
		reset-names = "can\0can-apb";
		tx-fifo-depth = <0x01>;
		rx-fifo-depth = <0x06>;
		status = "okay";
		assigned-clocks = <0x23 0x143>;
		assigned-clock-rates = <0xbebc200>;
		pinctrl-names = "default";
		pinctrl-0 = <0xec>;
	};

	can@fe590000 {
		compatible = "rockchip,rk3568-can-2.0";
		reg = <0x00 0xfe590000 0x00 0x1000>;
		interrupts = <0x00 0x03 0x04>;
		clocks = <0x23 0x145 0x23 0x144>;
		clock-names = "baudclk\0apb_pclk";
		resets = <0x23 0x159 0x23 0x158>;
		reset-names = "can\0can-apb";
		tx-fifo-depth = <0x01>;
		rx-fifo-depth = <0x06>;
		status = "disabled";
		assigned-clocks = <0x23 0x145>;
		assigned-clock-rates = <0xbebc200>;
		pinctrl-names = "default";
		pinctrl-0 = <0xed>;
	};

	i2c@fe5a0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xfe5a0000 0x00 0x1000>;
		clocks = <0x23 0x148 0x23 0x147>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x2f 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0xee>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		clock-frequency = <0x186a0>;

		gpio@21 {
			status = "disabled";
			compatible = "nxp,pca9555";
			reg = <0x21>;
			gpio-controller;
			#gpio-cells = <0x02>;
			gpio-group-num = <0xc8>;
			phandle = <0x102>;
		};

		gt1x@14 {
			status = "disabled";
			compatible = "goodix,gt1x";
			reg = <0x14>;
			pinctrl-names = "default";
			pinctrl-0 = <0xef>;
			goodix,rst-gpio = <0x3f 0x0e 0x00>;
			goodix,irq-gpio = <0x3f 0x0d 0x08>;
		};
	};

	i2c@fe5b0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xfe5b0000 0x00 0x1000>;
		clocks = <0x23 0x14a 0x23 0x149>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x30 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0xf0>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@fe5c0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xfe5c0000 0x00 0x1000>;
		clocks = <0x23 0x14c 0x23 0x14b>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x31 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0xf1>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@fe5d0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xfe5d0000 0x00 0x1000>;
		clocks = <0x23 0x14e 0x23 0x14d>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x32 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0xf2>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		clock-frequency = <0x61a80>;

		gc8034@37 {
			compatible = "galaxycore,gc8034";
			status = "disabled";
			reg = <0x37>;
			clocks = <0x23 0xd6>;
			clock-names = "xvclk";
			pinctrl-names = "default";
			pinctrl-0 = <0xf3>;
			reset-gpios = <0x4a 0x0e 0x01>;
			pwdn-gpios = <0xf4 0x0c 0x01>;
			rockchip,grf = <0x3b>;
			rockchip,camera-module-index = <0x00>;
			rockchip,camera-module-facing = "back";
			rockchip,camera-module-name = "RK-CMK-8M-2-v1";
			rockchip,camera-module-lens-name = "CK8401";

			port {

				endpoint {
					remote-endpoint = <0xf5>;
					data-lanes = <0x01 0x02 0x03 0x04>;
					phandle = <0x130>;
				};
			};
		};

		os04a10@36 {
			status = "disabled";
			compatible = "ovti,os04a10";
			reg = <0x36>;
			clocks = <0x23 0xd6>;
			clock-names = "xvclk";
			power-domains = <0x25 0x08>;
			pinctrl-names = "default";
			pinctrl-0 = <0xf3>;
			reset-gpios = <0x4a 0x0e 0x01>;
			pwdn-gpios = <0xf4 0x0c 0x00>;
			rockchip,camera-module-index = <0x00>;
			rockchip,camera-module-facing = "back";
			rockchip,camera-module-name = "CMK-OT1607-FV1";
			rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16";

			port {

				endpoint {
					remote-endpoint = <0xf6>;
					data-lanes = <0x01 0x02 0x03 0x04>;
					phandle = <0x12f>;
				};
			};
		};

		ov5695@36 {
			status = "disabled";
			compatible = "ovti,ov5695";
			reg = <0x36>;
			clocks = <0x23 0xd6>;
			clock-names = "xvclk";
			power-domains = <0x25 0x08>;
			pinctrl-names = "default";
			pinctrl-0 = <0xf3>;
			reset-gpios = <0x4a 0x0e 0x00>;
			pwdn-gpios = <0xf4 0x0c 0x00>;
			rockchip,camera-module-index = <0x00>;
			rockchip,camera-module-facing = "back";
			rockchip,camera-module-name = "TongJu";
			rockchip,camera-module-lens-name = "CHT842-MD";

			port {

				endpoint {
					remote-endpoint = <0xf7>;
					data-lanes = <0x01 0x02>;
					phandle = <0x131>;
				};
			};
		};

		XC7160b@1b {
			status = "okay";
			compatible = "firefly,xc7160";
			reg = <0x1b>;
			clocks = <0x23 0xd6>;
			clock-names = "xvclk";
			power-domains = <0x25 0x08>;
			pinctrl-names = "default";
			pinctrl-0 = <0xf3>;
			reset-gpios = <0x3f 0x1d 0x00>;
			pwdn-gpios = <0xf4 0x0c 0x00>;
			firefly,clkout-enabled-index = <0x00>;
			rockchip,camera-module-index = <0x00>;
			rockchip,camera-module-facing = "back";
			rockchip,camera-module-name = "NC";
			rockchip,camera-module-lens-name = "NC";

			port {

				endpoint {
					remote-endpoint = <0xf8>;
					data-lanes = <0x01 0x02 0x03 0x04>;
					phandle = <0x132>;
				};
			};
		};

		imx415@37 {
			status = "okay";
			compatible = "sony,imx415";
			reg = <0x37>;
			clocks = <0x23 0xd6>;
			clock-names = "xvclk";
			power-domains = <0x25 0x08>;
			pinctrl-names = "default";
			pinctrl-0 = <0xf3>;
			reset-gpios = <0x3f 0x1d 0x01>;
			pwdn-gpios = <0xf4 0x0c 0x00>;
			firefly,clkout-enabled-index = <0x00>;
			rockchip,camera-module-index = <0x00>;
			rockchip,camera-module-facing = "back";
			rockchip,camera-module-name = "CMK-OT2022-PX1";
			rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";

			port {

				endpoint {
					remote-endpoint = <0xf9>;
					data-lanes = <0x01 0x02 0x03 0x04>;
					phandle = <0x133>;
				};
			};
		};
	};

	i2c@fe5e0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xfe5e0000 0x00 0x1000>;
		clocks = <0x23 0x150 0x23 0x14f>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x33 0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0xfa>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";

		hym8563@51 {
			status = "okay";
			compatible = "haoyu,hym8563";
			reg = <0x51>;
			#clock-cells = <0x00>;
			rtc-irq-gpio = <0x3f 0x1b 0x02>;
			clock-frequency = <0x8000>;
		};

		mc3230sensor@4c {
			compatible = "gs_mc3230";
			reg = <0x4c>;
			type = <0x02>;
			irq_enable = <0x00>;
			poll_delay_ms = <0x1e>;
			layout = <0x04>;
			status = "okay";
		};

		mxc6655xa@15 {
			status = "disabled";
			compatible = "gs_mxc6655xa";
			pinctrl-names = "default";
			pinctrl-0 = <0xfb>;
			reg = <0x15>;
			irq-gpio = <0x4a 0x11 0x08>;
			irq_enable = <0x00>;
			poll_delay_ms = <0x1e>;
			type = <0x02>;
			power-off-in-suspend = <0x01>;
			layout = <0x01>;
		};
	};

	timer@fe5f0000 {
		compatible = "rockchip,rk3568-timer\0rockchip,rk3288-timer";
		reg = <0x00 0xfe5f0000 0x00 0x1000>;
		interrupts = <0x00 0x6d 0x04>;
		clocks = <0x23 0x16c 0x23 0x16d>;
		clock-names = "pclk\0timer";
	};

	watchdog@fe600000 {
		compatible = "snps,dw-wdt";
		reg = <0x00 0xfe600000 0x00 0x100>;
		clocks = <0x23 0x116 0x23 0x115>;
		clock-names = "tclk\0pclk";
		interrupts = <0x00 0x95 0x04>;
		status = "okay";
	};

	spi@fe610000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfe610000 0x00 0x1000>;
		interrupts = <0x00 0x67 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x23 0x152 0x23 0x151>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0x4e 0x14 0x4e 0x15>;
		dma-names = "tx\0rx";
		pinctrl-names = "default\0high_speed";
		pinctrl-0 = <0xfc 0xfd 0xfe>;
		pinctrl-1 = <0xfc 0xfd 0xff>;
		num-cs = <0x02>;
		status = "disabled";
	};

	spi@fe620000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfe620000 0x00 0x1000>;
		interrupts = <0x00 0x68 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x23 0x154 0x23 0x153>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0x4e 0x16 0x4e 0x17>;
		dma-names = "tx\0rx";
		pinctrl-names = "default\0high_speed";
		pinctrl-0 = <0x100>;
		pinctrl-1 = <0x101>;
		num-cs = <0x02>;
		status = "disabled";
		max-freq = <0x2dc6c00>;
		dev-port = <0x00>;

		spi_wk2xxx@0 {
			status = "disabled";
			compatible = "firefly,spi-wk2xxx";
			reg = <0x00>;
			spi-max-frequency = <0x989680>;
			power-gpio = <0x102 0x0f 0x00>;
			reset-gpio = <0x102 0x09 0x00>;
			irq-gpio = <0x3f 0x06 0x02>;
			cs-gpio = <0x4a 0x01 0x00>;
		};
	};

	spi@fe630000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfe630000 0x00 0x1000>;
		interrupts = <0x00 0x69 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x23 0x156 0x23 0x155>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0x4e 0x18 0x4e 0x19>;
		dma-names = "tx\0rx";
		pinctrl-names = "default\0high_speed";
		pinctrl-0 = <0x103 0x104 0x105>;
		pinctrl-1 = <0x103 0x104 0x106>;
		num-cs = <0x02>;
		status = "disabled";
	};

	spi@fe640000 {
		compatible = "rockchip,rk3066-spi";
		reg = <0x00 0xfe640000 0x00 0x1000>;
		interrupts = <0x00 0x6a 0x04>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		clocks = <0x23 0x158 0x23 0x157>;
		clock-names = "spiclk\0apb_pclk";
		dmas = <0x4e 0x1a 0x4e 0x1b>;
		dma-names = "tx\0rx";
		pinctrl-names = "default\0high_speed";
		pinctrl-0 = <0x107 0x108 0x109>;
		pinctrl-1 = <0x107 0x108 0x10a>;
		num-cs = <0x02>;
		status = "disabled";
	};

	serial@fe650000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe650000 0x00 0x100>;
		interrupts = <0x00 0x75 0x04>;
		clocks = <0x23 0x11f 0x23 0x11c>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x02 0x4e 0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x10b>;
		status = "disabled";
	};

	serial@fe660000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe660000 0x00 0x100>;
		interrupts = <0x00 0x76 0x04>;
		clocks = <0x23 0x123 0x23 0x120>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x04 0x4e 0x05>;
		pinctrl-names = "default";
		pinctrl-0 = <0x10c>;
		status = "disabled";
	};

	serial@fe670000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe670000 0x00 0x100>;
		interrupts = <0x00 0x77 0x04>;
		clocks = <0x23 0x127 0x23 0x124>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x06 0x4e 0x07>;
		pinctrl-names = "default";
		pinctrl-0 = <0x10d>;
		status = "okay";
	};

	serial@fe680000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe680000 0x00 0x100>;
		interrupts = <0x00 0x78 0x04>;
		clocks = <0x23 0x12b 0x23 0x128>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x08 0x4e 0x09>;
		pinctrl-names = "default";
		pinctrl-0 = <0x10e>;
		status = "okay";
	};

	serial@fe690000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe690000 0x00 0x100>;
		interrupts = <0x00 0x79 0x04>;
		clocks = <0x23 0x12f 0x23 0x12c>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x0a 0x4e 0x0b>;
		pinctrl-names = "default";
		pinctrl-0 = <0x10f>;
		status = "disabled";
	};

	serial@fe6a0000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe6a0000 0x00 0x100>;
		interrupts = <0x00 0x7a 0x04>;
		clocks = <0x23 0x133 0x23 0x130>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x0c 0x4e 0x0d>;
		pinctrl-names = "default";
		pinctrl-0 = <0x110>;
		status = "disabled";
	};

	serial@fe6b0000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe6b0000 0x00 0x100>;
		interrupts = <0x00 0x7b 0x04>;
		clocks = <0x23 0x137 0x23 0x134>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x0e 0x4e 0x0f>;
		pinctrl-names = "default";
		pinctrl-0 = <0x111>;
		status = "okay";
	};

	serial@fe6c0000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe6c0000 0x00 0x100>;
		interrupts = <0x00 0x7c 0x04>;
		clocks = <0x23 0x13b 0x23 0x138>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x10 0x4e 0x11>;
		pinctrl-names = "default";
		pinctrl-0 = <0x112 0x113>;
		status = "okay";
	};

	serial@fe6d0000 {
		compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
		reg = <0x00 0xfe6d0000 0x00 0x100>;
		interrupts = <0x00 0x7d 0x04>;
		clocks = <0x23 0x13f 0x23 0x13c>;
		clock-names = "baudclk\0apb_pclk";
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		dmas = <0x4e 0x12 0x4e 0x13>;
		pinctrl-names = "default";
		pinctrl-0 = <0x114>;
		status = "okay";
	};

	pwm@fe6e0000 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe6e0000 0x00 0x10>;
		interrupts = <0x00 0x53 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x115>;
		clocks = <0x23 0x15a 0x23 0x159>;
		clock-names = "pwm\0pclk";
		status = "okay";
	};

	pwm@fe6e0010 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe6e0010 0x00 0x10>;
		interrupts = <0x00 0x53 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x116>;
		clocks = <0x23 0x15a 0x23 0x159>;
		clock-names = "pwm\0pclk";
		status = "okay";
	};

	pwm@fe6e0020 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe6e0020 0x00 0x10>;
		interrupts = <0x00 0x53 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x117>;
		clocks = <0x23 0x15a 0x23 0x159>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fe6e0030 {
		compatible = "rockchip,remotectl-pwm";
		reg = <0x00 0xfe6e0030 0x00 0x10>;
		interrupts = <0x00 0x53 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x118>;
		clocks = <0x23 0x15a 0x23 0x159>;
		clock-names = "pwm\0pclk";
		status = "okay";
		remote_pwm_id = <0x03>;
		handle_cpu_id = <0x01>;
		remote_support_psci = <0x00>;

		ir_key_firefly {
			rockchip,usercode = <0xff00>;
			rockchip,key_table = <0xeb 0x74 0xec 0x8b 0xfe 0x9e 0xb7 0x66 0xa3 0x96 0xf4 0x73 0xa7 0x72 0xf8 0xe8 0xfc 0x67 0xfd 0x6c 0xf1 0x69 0xe5 0x6a>;
		};
	};

	pwm@fe6f0000 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe6f0000 0x00 0x10>;
		interrupts = <0x00 0x54 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x119>;
		clocks = <0x23 0x15d 0x23 0x15c>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fe6f0010 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe6f0010 0x00 0x10>;
		interrupts = <0x00 0x54 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x11a>;
		clocks = <0x23 0x15d 0x23 0x15c>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fe6f0020 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe6f0020 0x00 0x10>;
		interrupts = <0x00 0x54 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x11b>;
		clocks = <0x23 0x15d 0x23 0x15c>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fe6f0030 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe6f0030 0x00 0x10>;
		interrupts = <0x00 0x54 0x04 0x00 0x58 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x11c>;
		clocks = <0x23 0x15d 0x23 0x15c>;
		clock-names = "pwm\0pclk";
		status = "disabled";
		phandle = <0x157>;
	};

	pwm@fe700000 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe700000 0x00 0x10>;
		interrupts = <0x00 0x55 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x11d>;
		clocks = <0x23 0x160 0x23 0x15f>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fe700010 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe700010 0x00 0x10>;
		interrupts = <0x00 0x55 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x11e>;
		clocks = <0x23 0x160 0x23 0x15f>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fe700020 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe700020 0x00 0x10>;
		interrupts = <0x00 0x55 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x11f>;
		clocks = <0x23 0x160 0x23 0x15f>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	pwm@fe700030 {
		compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
		reg = <0x00 0xfe700030 0x00 0x10>;
		interrupts = <0x00 0x55 0x04 0x00 0x59 0x04>;
		#pwm-cells = <0x03>;
		pinctrl-names = "active";
		pinctrl-0 = <0x120>;
		clocks = <0x23 0x160 0x23 0x15f>;
		clock-names = "pwm\0pclk";
		status = "disabled";
	};

	tsadc@fe710000 {
		compatible = "rockchip,rk3568-tsadc";
		reg = <0x00 0xfe710000 0x00 0x100>;
		interrupts = <0x00 0x73 0x04>;
		rockchip,grf = <0x3b>;
		clocks = <0x23 0x111 0x23 0x10f>;
		clock-names = "tsadc\0apb_pclk";
		assigned-clocks = <0x23 0x110 0x23 0x111>;
		assigned-clock-rates = <0x1036640 0xaae60>;
		resets = <0x23 0x182 0x23 0x181 0x23 0x1d7>;
		reset-names = "tsadc\0tsadc-apb\0tsadc-phy";
		#thermal-sensor-cells = <0x01>;
		nvmem-cells = <0x121 0x122>;
		nvmem-cell-names = "trim_base\0trim_base_frac";
		rockchip,hw-tshut-temp = <0x1d4c0>;
		rockchip,hw-tshut-mode = <0x00>;
		rockchip,hw-tshut-polarity = <0x00>;
		pinctrl-names = "gpio\0otpout";
		pinctrl-0 = <0x123>;
		pinctrl-1 = <0x124>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		phandle = <0x1f>;

		tsadc@0 {
			reg = <0x00>;
			nvmem-cells = <0x125 0x126>;
			nvmem-cell-names = "trim_l\0trim_h";
		};

		tsadc@1 {
			reg = <0x01>;
			nvmem-cells = <0x127 0x128>;
			nvmem-cell-names = "trim_l\0trim_h";
		};
	};

	saradc@fe720000 {
		compatible = "rockchip,rk3568-saradc\0rockchip,rk3399-saradc";
		reg = <0x00 0xfe720000 0x00 0x100>;
		interrupts = <0x00 0x5d 0x04>;
		#io-channel-cells = <0x01>;
		clocks = <0x23 0x113 0x23 0x112>;
		clock-names = "saradc\0apb_pclk";
		resets = <0x23 0x180>;
		reset-names = "saradc-apb";
		status = "okay";
		vref-supply = <0x129>;
		phandle = <0x49>;
	};

	mailbox@fe780000 {
		compatible = "rockchip,rk3568-mailbox\0rockchip,rk3368-mailbox";
		reg = <0x00 0xfe780000 0x00 0x1000>;
		interrupts = <0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04>;
		clocks = <0x23 0x11b>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <0x01>;
		status = "disabled";
	};

	phy@fe820000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x00 0xfe820000 0x00 0x100>;
		#phy-cells = <0x01>;
		clocks = <0x3a 0x1f 0x23 0x17c 0x23 0x7f>;
		clock-names = "refclk\0apbclk\0pipe_clk";
		assigned-clocks = <0x3a 0x1f>;
		assigned-clock-rates = <0x5f5e100>;
		resets = <0x23 0x1c4 0x23 0x1c5>;
		reset-names = "combphy-apb\0combphy";
		rockchip,pipe-grf = <0x12a>;
		rockchip,pipe-phy-grf = <0x12b>;
		status = "okay";
		phandle = <0x24>;
	};

	phy@fe830000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x00 0xfe830000 0x00 0x100>;
		#phy-cells = <0x01>;
		clocks = <0x3a 0x22 0x23 0x17d 0x23 0x7f>;
		clock-names = "refclk\0apbclk\0pipe_clk";
		assigned-clocks = <0x3a 0x22>;
		assigned-clock-rates = <0x5f5e100>;
		resets = <0x23 0x1c6 0x23 0x1c7>;
		reset-names = "combphy-apb\0combphy";
		rockchip,pipe-grf = <0x12a>;
		rockchip,pipe-phy-grf = <0x12c>;
		status = "okay";
		phandle = <0x26>;
	};

	phy@fe840000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x00 0xfe840000 0x00 0x100>;
		#phy-cells = <0x01>;
		clocks = <0x3a 0x25 0x23 0x17e 0x23 0x7f>;
		clock-names = "refclk\0apbclk\0pipe_clk";
		assigned-clocks = <0x3a 0x25>;
		assigned-clock-rates = <0x5f5e100>;
		resets = <0x23 0x1c8 0x23 0x1c9>;
		reset-names = "combphy-apb\0combphy";
		rockchip,pipe-grf = <0x12a>;
		rockchip,pipe-phy-grf = <0x12d>;
		status = "okay";
		phandle = <0x27>;
	};

	phy@fe850000 {
		compatible = "rockchip,rk3568-dsi-dphy\0rockchip,rk3568-video-phy";
		reg = <0x00 0xfe850000 0x00 0x10000 0x00 0xfe060000 0x00 0x10000>;
		reg-names = "phy\0host";
		clocks = <0x3a 0x17 0x23 0x17a 0x23 0xe8>;
		clock-names = "ref\0pclk\0pclk_host";
		#clock-cells = <0x00>;
		resets = <0x23 0x1bb>;
		reset-names = "apb";
		power-domains = <0x25 0x09>;
		#phy-cells = <0x00>;
		status = "disabled";
		phandle = <0x34>;
	};

	phy@fe860000 {
		compatible = "rockchip,rk3568-dsi-dphy\0rockchip,rk3568-video-phy";
		reg = <0x00 0xfe860000 0x00 0x10000 0x00 0xfe070000 0x00 0x10000>;
		reg-names = "phy\0host";
		clocks = <0x3a 0x19 0x23 0x17b 0x23 0xe9>;
		clock-names = "ref\0pclk\0pclk_host";
		#clock-cells = <0x00>;
		resets = <0x23 0x1bc>;
		reset-names = "apb";
		power-domains = <0x25 0x09>;
		#phy-cells = <0x00>;
		status = "disabled";
		phandle = <0x36>;
	};

	csi2-dphy-hw@fe870000 {
		compatible = "rockchip,rk3568-csi2-dphy-hw";
		reg = <0x00 0xfe870000 0x00 0x1000>;
		clocks = <0x23 0x179>;
		clock-names = "pclk";
		rockchip,grf = <0x3b>;
		status = "okay";
		phandle = <0x12e>;
	};

	csi2-dphy0 {
		compatible = "rockchip,rk3568-csi2-dphy";
		rockchip,hw = <0x12e>;
		status = "okay";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0x12f>;
					data-lanes = <0x01 0x02 0x03 0x04>;
					phandle = <0xf6>;
				};

				endpoint@2 {
					reg = <0x02>;
					remote-endpoint = <0x130>;
					data-lanes = <0x01 0x02 0x03 0x04>;
					phandle = <0xf5>;
				};

				endpoint@3 {
					reg = <0x03>;
					remote-endpoint = <0x131>;
					data-lanes = <0x01 0x02>;
					phandle = <0xf7>;
				};

				endpoint@4 {
					reg = <0x04>;
					remote-endpoint = <0x132>;
					data-lanes = <0x01 0x02 0x03 0x04>;
					phandle = <0xf8>;
				};

				endpoint@5 {
					reg = <0x05>;
					remote-endpoint = <0x133>;
					data-lanes = <0x01 0x02 0x03 0x04>;
					phandle = <0xf9>;
				};
			};

			port@1 {
				reg = <0x01>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x134>;
					phandle = <0x8c>;
				};
			};
		};
	};

	csi2-dphy1 {
		compatible = "rockchip,rk3568-csi2-dphy";
		rockchip,hw = <0x12e>;
		status = "disabled";
	};

	csi2-dphy2 {
		compatible = "rockchip,rk3568-csi2-dphy";
		rockchip,hw = <0x12e>;
		status = "disabled";
	};

	usb2-phy@fe8a0000 {
		compatible = "rockchip,rk3568-usb2phy";
		reg = <0x00 0xfe8a0000 0x00 0x10000>;
		interrupts = <0x00 0x87 0x04>;
		clocks = <0x3a 0x13>;
		clock-names = "phyclk";
		#clock-cells = <0x00>;
		assigned-clocks = <0x23 0x0b>;
		assigned-clock-parents = <0x29>;
		clock-output-names = "usb480m_phy";
		rockchip,usbgrf = <0x135>;
		status = "okay";
		phandle = <0x29>;

		host-port {
			#phy-cells = <0x00>;
			status = "okay";
			phy-supply = <0x136>;
			phandle = <0x2b>;
		};

		otg-port {
			#phy-cells = <0x00>;
			status = "okay";
			phandle = <0x28>;
		};
	};

	usb2-phy@fe8b0000 {
		compatible = "rockchip,rk3568-usb2phy";
		reg = <0x00 0xfe8b0000 0x00 0x10000>;
		interrupts = <0x00 0x88 0x04>;
		clocks = <0x3a 0x15>;
		clock-names = "phyclk";
		#clock-cells = <0x00>;
		rockchip,usbgrf = <0x137>;
		status = "okay";
		phandle = <0x2c>;

		host-port {
			#phy-cells = <0x00>;
			status = "okay";
			phy-supply = <0x136>;
			phandle = <0x2e>;
		};

		otg-port {
			#phy-cells = <0x00>;
			status = "okay";
			phy-supply = <0x136>;
			phandle = <0x2d>;
		};
	};

	phy@fe8c0000 {
		compatible = "rockchip,rk3568-pcie3-phy";
		reg = <0x00 0xfe8c0000 0x00 0x20000>;
		#phy-cells = <0x00>;
		clocks = <0x3a 0x26 0x3a 0x27 0x23 0x177>;
		clock-names = "refclk_m\0refclk_n\0pclk";
		resets = <0x23 0x1be>;
		reset-names = "phy";
		rockchip,phy-grf = <0x138>;
		status = "okay";
		phandle = <0xc0>;
	};

	pinctrl {
		compatible = "rockchip,rk3568-pinctrl";
		rockchip,grf = <0x3b>;
		rockchip,pmu = <0x3c>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		gpio0@fdd60000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfdd60000 0x00 0x100>;
			interrupts = <0x00 0x21 0x04>;
			clocks = <0x3a 0x2e 0x3a 0x0c>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x3f>;
		};

		gpio1@fe740000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfe740000 0x00 0x100>;
			interrupts = <0x00 0x22 0x04>;
			clocks = <0x23 0x163 0x23 0x164>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x159>;
		};

		gpio2@fe750000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfe750000 0x00 0x100>;
			interrupts = <0x00 0x23 0x04>;
			clocks = <0x23 0x165 0x23 0x166>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x91>;
		};

		gpio3@fe760000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfe760000 0x00 0x100>;
			interrupts = <0x00 0x24 0x04>;
			clocks = <0x23 0x167 0x23 0x168>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x4a>;
		};

		gpio4@fe770000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xfe770000 0x00 0x100>;
			interrupts = <0x00 0x25 0x04>;
			clocks = <0x23 0x169 0x23 0x16a>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0xf4>;
		};

		pcfg-pull-up {
			bias-pull-up;
			phandle = <0x13b>;
		};

		pcfg-pull-down {
			bias-pull-down;
			phandle = <0x142>;
		};

		pcfg-pull-none {
			bias-disable;
			phandle = <0x139>;
		};

		pcfg-pull-none-drv-level-1 {
			bias-disable;
			drive-strength = <0x01>;
			phandle = <0x13d>;
		};

		pcfg-pull-none-drv-level-2 {
			bias-disable;
			drive-strength = <0x02>;
			phandle = <0x13c>;
		};

		pcfg-pull-none-drv-level-3 {
			bias-disable;
			drive-strength = <0x03>;
			phandle = <0x141>;
		};

		pcfg-pull-up-drv-level-1 {
			bias-pull-up;
			drive-strength = <0x01>;
			phandle = <0x140>;
		};

		pcfg-pull-up-drv-level-2 {
			bias-pull-up;
			drive-strength = <0x02>;
			phandle = <0x13a>;
		};

		pcfg-pull-none-smt {
			bias-disable;
			input-schmitt-enable;
			phandle = <0x13e>;
		};

		pcfg-output-low-pull-down {
			output-low;
			bias-pull-down;
			phandle = <0x13f>;
		};

		acodec {

			acodec-pins {
				rockchip,pins = <0x01 0x09 0x05 0x139 0x01 0x01 0x05 0x139 0x01 0x00 0x05 0x139 0x01 0x07 0x05 0x139 0x01 0x08 0x05 0x139 0x01 0x03 0x05 0x139 0x01 0x05 0x05 0x139>;
				phandle = <0xea>;
			};
		};

		cam {

			vcc-cam {
				rockchip,pins = <0x00 0x11 0x00 0x139>;
				phandle = <0x158>;
			};
		};

		can1 {

			can1m1-pins {
				rockchip,pins = <0x04 0x12 0x03 0x139 0x04 0x13 0x03 0x139>;
				phandle = <0xec>;
			};
		};

		can2 {

			can2m0-pins {
				rockchip,pins = <0x04 0x0c 0x03 0x139 0x04 0x0d 0x03 0x139>;
				phandle = <0xed>;
			};
		};

		cif {

			cif-clk {
				rockchip,pins = <0x04 0x10 0x01 0x139>;
				phandle = <0xf3>;
			};
		};

		clk32k {

			clk32k-out0 {
				rockchip,pins = <0x00 0x08 0x02 0x139>;
				phandle = <0x22>;
			};
		};

		ebc {

			ebc-pins {
				rockchip,pins = <0x04 0x10 0x02 0x139 0x04 0x0b 0x02 0x139 0x04 0x0c 0x02 0x139 0x04 0x06 0x02 0x139 0x04 0x11 0x02 0x139 0x03 0x16 0x02 0x139 0x03 0x17 0x02 0x139 0x03 0x18 0x02 0x139 0x03 0x19 0x02 0x139 0x03 0x1a 0x02 0x139 0x03 0x1b 0x02 0x139 0x03 0x1c 0x02 0x139 0x03 0x1d 0x02 0x139 0x03 0x1e 0x02 0x139 0x03 0x1f 0x02 0x139 0x04 0x00 0x02 0x139 0x04 0x01 0x02 0x139 0x04 0x02 0x02 0x139 0x04 0x03 0x02 0x139 0x04 0x04 0x02 0x139 0x04 0x05 0x02 0x139 0x04 0x0e 0x02 0x139 0x04 0x0f 0x02 0x139>;
				phandle = <0x7c>;
			};
		};

		fspi {

			fspi-pins {
				rockchip,pins = <0x01 0x18 0x01 0x139 0x01 0x1b 0x01 0x139 0x01 0x19 0x01 0x139 0x01 0x1a 0x01 0x139 0x01 0x17 0x02 0x139 0x01 0x1c 0x01 0x139>;
				phandle = <0xd4>;
			};
		};

		gmac0 {

			gmac0-miim {
				rockchip,pins = <0x02 0x13 0x02 0x139 0x02 0x14 0x02 0x139>;
				phandle = <0xc8>;
			};

			gmac0-clkinout {
				rockchip,pins = <0x02 0x12 0x02 0x139>;
				phandle = <0xcd>;
			};

			gmac0-rx-bus2 {
				rockchip,pins = <0x02 0x0e 0x01 0x139 0x02 0x0f 0x02 0x139 0x02 0x10 0x02 0x139>;
				phandle = <0xca>;
			};

			gmac0-tx-bus2 {
				rockchip,pins = <0x02 0x0b 0x01 0x13c 0x02 0x0c 0x01 0x13c 0x02 0x0d 0x01 0x139>;
				phandle = <0xc9>;
			};

			gmac0-rgmii-clk {
				rockchip,pins = <0x02 0x05 0x02 0x139 0x02 0x08 0x02 0x13d>;
				phandle = <0xcb>;
			};

			gmac0-rgmii-bus {
				rockchip,pins = <0x02 0x03 0x02 0x139 0x02 0x04 0x02 0x139 0x02 0x06 0x02 0x13c 0x02 0x07 0x02 0x13c>;
				phandle = <0xcc>;
			};
		};

		gmac1 {

			gmac1m1-miim {
				rockchip,pins = <0x04 0x0e 0x03 0x139 0x04 0x0f 0x03 0x139>;
				phandle = <0x93>;
			};

			gmac1m1-clkinout {
				rockchip,pins = <0x04 0x11 0x03 0x139>;
				phandle = <0x98>;
			};

			gmac1m1-rx-bus2 {
				rockchip,pins = <0x04 0x07 0x03 0x139 0x04 0x08 0x03 0x139 0x04 0x09 0x03 0x139>;
				phandle = <0x95>;
			};

			gmac1m1-tx-bus2 {
				rockchip,pins = <0x04 0x04 0x03 0x13c 0x04 0x05 0x03 0x13c 0x04 0x06 0x03 0x139>;
				phandle = <0x94>;
			};

			gmac1m1-rgmii-clk {
				rockchip,pins = <0x04 0x03 0x03 0x139 0x04 0x00 0x03 0x13d>;
				phandle = <0x96>;
			};

			gmac1m1-rgmii-bus {
				rockchip,pins = <0x04 0x01 0x03 0x139 0x04 0x02 0x03 0x139 0x03 0x1e 0x03 0x13c 0x03 0x1f 0x03 0x13c>;
				phandle = <0x97>;
			};
		};

		hdmitx {

			hdmitxm0-cec {
				rockchip,pins = <0x04 0x19 0x01 0x139>;
				phandle = <0xac>;
			};

			hdmitx-scl {
				rockchip,pins = <0x04 0x17 0x01 0x139>;
				phandle = <0xaa>;
			};

			hdmitx-sda {
				rockchip,pins = <0x04 0x18 0x01 0x139>;
				phandle = <0xab>;
			};
		};

		i2c0 {

			i2c0-xfer {
				rockchip,pins = <0x00 0x09 0x01 0x13e 0x00 0x0a 0x01 0x13e>;
				phandle = <0x3d>;
			};
		};

		i2c1 {

			i2c1-xfer {
				rockchip,pins = <0x00 0x0b 0x01 0x13e 0x00 0x0c 0x01 0x13e>;
				phandle = <0xee>;
			};
		};

		i2c2 {

			i2c2m0-xfer {
				rockchip,pins = <0x00 0x0d 0x01 0x13e 0x00 0x0e 0x01 0x13e>;
				phandle = <0xf0>;
			};
		};

		i2c3 {

			i2c3m0-xfer {
				rockchip,pins = <0x01 0x01 0x01 0x13e 0x01 0x00 0x01 0x13e>;
				phandle = <0xf1>;
			};
		};

		i2c4 {

			i2c4m0-xfer {
				rockchip,pins = <0x04 0x0b 0x01 0x13e 0x04 0x0a 0x01 0x13e>;
				phandle = <0xf2>;
			};
		};

		i2c5 {

			i2c5m0-xfer {
				rockchip,pins = <0x03 0x0b 0x04 0x13e 0x03 0x0c 0x04 0x13e>;
				phandle = <0xfa>;
			};
		};

		i2s1 {

			i2s1m0-lrcktx {
				rockchip,pins = <0x01 0x05 0x01 0x13e>;
				phandle = <0xd7>;
			};

			i2s1m0-mclk {
				rockchip,pins = <0x01 0x02 0x01 0x13e>;
				phandle = <0x47>;
			};

			i2s1m0-sclktx {
				rockchip,pins = <0x01 0x03 0x01 0x13e>;
				phandle = <0xd6>;
			};

			i2s1m0-sdi0 {
				rockchip,pins = <0x01 0x0b 0x01 0x139>;
				phandle = <0xd8>;
			};

			i2s1m0-sdo0 {
				rockchip,pins = <0x01 0x07 0x01 0x139>;
				phandle = <0xd9>;
			};
		};

		i2s2 {

			i2s2m0-lrcktx {
				rockchip,pins = <0x02 0x13 0x01 0x13e>;
				phandle = <0xdb>;
			};

			i2s2m0-sclktx {
				rockchip,pins = <0x02 0x12 0x01 0x13e>;
				phandle = <0xda>;
			};

			i2s2m0-sdi {
				rockchip,pins = <0x02 0x15 0x01 0x139>;
				phandle = <0xdc>;
			};

			i2s2m0-sdo {
				rockchip,pins = <0x02 0x14 0x01 0x139>;
				phandle = <0xdd>;
			};
		};

		i2s3 {

			i2s3m0-lrck {
				rockchip,pins = <0x03 0x04 0x04 0x13e>;
				phandle = <0xdf>;
			};

			i2s3m0-sclk {
				rockchip,pins = <0x03 0x03 0x04 0x13e>;
				phandle = <0xde>;
			};

			i2s3m0-sdi {
				rockchip,pins = <0x03 0x06 0x04 0x139>;
				phandle = <0xe0>;
			};

			i2s3m0-sdo {
				rockchip,pins = <0x03 0x05 0x04 0x139>;
				phandle = <0xe1>;
			};
		};

		lcdc {

			lcdc-ctl {
				rockchip,pins = <0x03 0x00 0x01 0x139 0x02 0x18 0x01 0x139 0x02 0x19 0x01 0x139 0x02 0x1a 0x01 0x139 0x02 0x1b 0x01 0x139 0x02 0x1c 0x01 0x139 0x02 0x1d 0x01 0x139 0x02 0x1e 0x01 0x139 0x02 0x1f 0x01 0x139 0x03 0x01 0x01 0x139 0x03 0x02 0x01 0x139 0x03 0x03 0x01 0x139 0x03 0x04 0x01 0x139 0x03 0x05 0x01 0x139 0x03 0x06 0x01 0x139 0x03 0x07 0x01 0x139 0x03 0x08 0x01 0x139 0x03 0x09 0x01 0x139 0x03 0x0a 0x01 0x139 0x03 0x0b 0x01 0x139 0x03 0x0c 0x01 0x139 0x03 0x0d 0x01 0x139 0x03 0x0e 0x01 0x139 0x03 0x0f 0x01 0x139 0x03 0x10 0x01 0x139 0x03 0x13 0x01 0x139 0x03 0x11 0x01 0x139 0x03 0x12 0x01 0x139>;
				phandle = <0x39>;
			};
		};

		pdm {

			pdmm0-clk {
				rockchip,pins = <0x01 0x06 0x03 0x139>;
				phandle = <0xe2>;
			};

			pdmm0-clk1 {
				rockchip,pins = <0x01 0x04 0x03 0x139>;
				phandle = <0xe3>;
			};

			pdmm0-sdi0 {
				rockchip,pins = <0x01 0x0b 0x02 0x139>;
				phandle = <0xe4>;
			};

			pdmm0-sdi1 {
				rockchip,pins = <0x01 0x0a 0x03 0x139>;
				phandle = <0xe5>;
			};

			pdmm0-sdi2 {
				rockchip,pins = <0x01 0x09 0x03 0x139>;
				phandle = <0xe6>;
			};

			pdmm0-sdi3 {
				rockchip,pins = <0x01 0x08 0x03 0x139>;
				phandle = <0xe7>;
			};
		};

		pmic {

			pmic_int {
				rockchip,pins = <0x00 0x03 0x00 0x13b>;
				phandle = <0x40>;
			};

			soc_slppin_gpio {
				rockchip,pins = <0x00 0x02 0x00 0x13f>;
				phandle = <0x43>;
			};

			soc_slppin_slp {
				rockchip,pins = <0x00 0x02 0x01 0x13b>;
				phandle = <0x41>;
			};

			soc_slppin_rst {
				rockchip,pins = <0x00 0x02 0x02 0x139>;
			};

			spk_ctl_gpio {
				rockchip,pins = <0x03 0x15 0x00 0x13b>;
				phandle = <0x48>;
			};
		};

		pwm0 {

			pwm0m0-pins {
				rockchip,pins = <0x00 0x0f 0x01 0x139>;
				phandle = <0x50>;
			};
		};

		pwm1 {

			pwm1m0-pins {
				rockchip,pins = <0x00 0x10 0x01 0x139>;
				phandle = <0x51>;
			};
		};

		pwm2 {

			pwm2m0-pins {
				rockchip,pins = <0x00 0x11 0x01 0x139>;
				phandle = <0x52>;
			};
		};

		pwm3 {

			pwm3-pins {
				rockchip,pins = <0x00 0x12 0x01 0x139>;
				phandle = <0x53>;
			};
		};

		pwm4 {

			pwm4-pins {
				rockchip,pins = <0x00 0x13 0x01 0x139>;
				phandle = <0x115>;
			};
		};

		pwm5 {

			pwm5-pins {
				rockchip,pins = <0x00 0x14 0x01 0x139>;
				phandle = <0x116>;
			};
		};

		pwm6 {

			pwm6-pins {
				rockchip,pins = <0x00 0x15 0x01 0x139>;
				phandle = <0x117>;
			};
		};

		pwm7 {

			pwm7-pins {
				rockchip,pins = <0x00 0x16 0x01 0x139>;
				phandle = <0x118>;
			};
		};

		pwm8 {

			pwm8m0-pins {
				rockchip,pins = <0x03 0x09 0x05 0x139>;
				phandle = <0x119>;
			};
		};

		pwm9 {

			pwm9m0-pins {
				rockchip,pins = <0x03 0x0a 0x05 0x139>;
				phandle = <0x11a>;
			};
		};

		pwm10 {

			pwm10m0-pins {
				rockchip,pins = <0x03 0x0d 0x05 0x139>;
				phandle = <0x11b>;
			};
		};

		pwm11 {

			pwm11m0-pins {
				rockchip,pins = <0x03 0x0e 0x05 0x139>;
				phandle = <0x11c>;
			};
		};

		pwm12 {

			pwm12m0-pins {
				rockchip,pins = <0x03 0x0f 0x02 0x139>;
				phandle = <0x11d>;
			};
		};

		pwm13 {

			pwm13m0-pins {
				rockchip,pins = <0x03 0x10 0x02 0x139>;
				phandle = <0x11e>;
			};
		};

		pwm14 {

			pwm14m0-pins {
				rockchip,pins = <0x03 0x14 0x01 0x139>;
				phandle = <0x11f>;
			};
		};

		pwm15 {

			pwm15m0-pins {
				rockchip,pins = <0x03 0x15 0x01 0x139>;
				phandle = <0x120>;
			};
		};

		scr {

			scr-pins {
				rockchip,pins = <0x01 0x02 0x03 0x139 0x01 0x07 0x03 0x13b 0x01 0x03 0x03 0x13b 0x01 0x05 0x03 0x139>;
				phandle = <0xeb>;
			};
		};

		sdmmc0 {

			sdmmc0-bus4 {
				rockchip,pins = <0x01 0x1d 0x01 0x13a 0x01 0x1e 0x01 0x13a 0x01 0x1f 0x01 0x13a 0x02 0x00 0x01 0x13a>;
				phandle = <0xd0>;
			};

			sdmmc0-clk {
				rockchip,pins = <0x02 0x02 0x01 0x13a>;
				phandle = <0xd1>;
			};

			sdmmc0-cmd {
				rockchip,pins = <0x02 0x01 0x01 0x13a>;
				phandle = <0xd2>;
			};

			sdmmc0-det {
				rockchip,pins = <0x00 0x04 0x01 0x13b>;
				phandle = <0xd3>;
			};
		};

		sdmmc2 {

			sdmmc2m0-bus4 {
				rockchip,pins = <0x03 0x16 0x03 0x13a 0x03 0x17 0x03 0x13a 0x03 0x18 0x03 0x13a 0x03 0x19 0x03 0x13a>;
				phandle = <0xb0>;
			};

			sdmmc2m0-clk {
				rockchip,pins = <0x03 0x1b 0x03 0x13a>;
				phandle = <0xb2>;
			};

			sdmmc2m0-cmd {
				rockchip,pins = <0x03 0x1a 0x03 0x13a>;
				phandle = <0xb1>;
			};
		};

		spdif {

			spdifm1-tx {
				rockchip,pins = <0x03 0x15 0x02 0x139>;
				phandle = <0xe9>;
			};
		};

		spi0 {

			spi0m0-pins {
				rockchip,pins = <0x00 0x0d 0x02 0x139 0x00 0x15 0x02 0x139 0x00 0x0e 0x02 0x139>;
				phandle = <0xfe>;
			};

			spi0m0-cs0 {
				rockchip,pins = <0x00 0x16 0x02 0x139>;
				phandle = <0xfc>;
			};

			spi0m0-cs1 {
				rockchip,pins = <0x00 0x14 0x02 0x139>;
				phandle = <0xfd>;
			};
		};

		spi1 {

			spi1m1-pins {
				rockchip,pins = <0x03 0x13 0x03 0x139 0x03 0x12 0x03 0x139 0x03 0x11 0x03 0x139>;
				phandle = <0x100>;
			};
		};

		spi2 {

			spi2m0-pins {
				rockchip,pins = <0x02 0x11 0x04 0x139 0x02 0x12 0x04 0x139 0x02 0x13 0x04 0x139>;
				phandle = <0x105>;
			};

			spi2m0-cs0 {
				rockchip,pins = <0x02 0x14 0x04 0x139>;
				phandle = <0x103>;
			};

			spi2m0-cs1 {
				rockchip,pins = <0x02 0x15 0x04 0x139>;
				phandle = <0x104>;
			};
		};

		spi3 {

			spi3m0-pins {
				rockchip,pins = <0x04 0x0b 0x04 0x139 0x04 0x08 0x04 0x139 0x04 0x0a 0x04 0x139>;
				phandle = <0x109>;
			};

			spi3m0-cs0 {
				rockchip,pins = <0x04 0x06 0x04 0x139>;
				phandle = <0x107>;
			};

			spi3m0-cs1 {
				rockchip,pins = <0x04 0x07 0x04 0x139>;
				phandle = <0x108>;
			};
		};

		tsadc {

			tsadc-shutorg {
				rockchip,pins = <0x00 0x01 0x02 0x139>;
				phandle = <0x124>;
			};
		};

		uart0 {

			uart0-xfer {
				rockchip,pins = <0x00 0x10 0x03 0x13b 0x00 0x11 0x03 0x13b>;
				phandle = <0x4f>;
			};
		};

		uart1 {

			uart1m0-xfer {
				rockchip,pins = <0x02 0x0b 0x02 0x13b 0x02 0x0c 0x02 0x13b>;
				phandle = <0x10b>;
			};
		};

		uart2 {

			uart2m0-xfer {
				rockchip,pins = <0x00 0x18 0x01 0x13b 0x00 0x19 0x01 0x13b>;
				phandle = <0x10c>;
			};
		};

		uart3 {

			uart3m1-xfer {
				rockchip,pins = <0x03 0x10 0x04 0x13b 0x03 0x0f 0x04 0x13b>;
				phandle = <0x10d>;
			};
		};

		uart4 {

			uart4m1-xfer {
				rockchip,pins = <0x03 0x09 0x04 0x13b 0x03 0x0a 0x04 0x13b>;
				phandle = <0x10e>;
			};
		};

		uart5 {

			uart5m0-xfer {
				rockchip,pins = <0x02 0x01 0x03 0x13b 0x02 0x02 0x03 0x13b>;
				phandle = <0x10f>;
			};
		};

		uart6 {

			uart6m0-xfer {
				rockchip,pins = <0x02 0x03 0x03 0x13b 0x02 0x04 0x03 0x13b>;
				phandle = <0x110>;
			};
		};

		uart7 {

			uart7m1-xfer {
				rockchip,pins = <0x03 0x15 0x04 0x13b 0x03 0x14 0x04 0x13b>;
				phandle = <0x111>;
			};
		};

		uart8 {

			uart8m0-xfer {
				rockchip,pins = <0x02 0x16 0x02 0x13b 0x02 0x15 0x03 0x13b>;
				phandle = <0x112>;
			};

			uart8m0-ctsn {
				rockchip,pins = <0x02 0x0a 0x03 0x139>;
				phandle = <0x113>;
			};

			uart8m0-rtsn {
				rockchip,pins = <0x02 0x09 0x03 0x139>;
				phandle = <0x155>;
			};
		};

		uart9 {

			uart9m1-xfer {
				rockchip,pins = <0x04 0x16 0x04 0x13b 0x04 0x15 0x04 0x13b>;
				phandle = <0x114>;
			};
		};

		spi0-hs {

			spi0m0-pins {
				rockchip,pins = <0x00 0x0d 0x02 0x140 0x00 0x15 0x02 0x140 0x00 0x0e 0x02 0x140>;
				phandle = <0xff>;
			};
		};

		spi1-hs {

			spi1m1-pins {
				rockchip,pins = <0x03 0x13 0x03 0x140 0x03 0x12 0x03 0x140 0x03 0x11 0x03 0x140>;
				phandle = <0x101>;
			};
		};

		spi2-hs {

			spi2m0-pins {
				rockchip,pins = <0x02 0x11 0x04 0x140 0x02 0x12 0x04 0x140 0x02 0x13 0x04 0x140>;
				phandle = <0x106>;
			};
		};

		spi3-hs {

			spi3m0-pins {
				rockchip,pins = <0x04 0x0b 0x04 0x140 0x04 0x08 0x04 0x140 0x04 0x0a 0x04 0x140>;
				phandle = <0x10a>;
			};
		};

		gpio-func {

			tsadc-gpio-func {
				rockchip,pins = <0x00 0x01 0x00 0x139>;
				phandle = <0x123>;
			};
		};

		usb {

			vcc5v0-host-en {
				rockchip,pins = <0x00 0x06 0x00 0x139>;
				phandle = <0x150>;
			};

			vcc5v0-otg-en {
				rockchip,pins = <0x00 0x05 0x00 0x139>;
				phandle = <0x151>;
			};

			vcc-hub-reset-en {
				rockchip,pins = <0x01 0x04 0x00 0x139>;
				phandle = <0x15a>;
			};
		};

		headphone {

			hp-det {
				rockchip,pins = <0x03 0x12 0x00 0x142>;
				phandle = <0x148>;
			};
		};

		sdio-pwrseq {

			wifi-enable-h {
				rockchip,pins = <0x03 0x1d 0x00 0x139>;
				phandle = <0x153>;
			};
		};

		wireless-wlan {

			wifi-host-wake-irq {
				rockchip,pins = <0x03 0x1c 0x00 0x142>;
				phandle = <0x154>;
			};
		};

		wireless-bluetooth {

			uart8-gpios {
				rockchip,pins = <0x02 0x09 0x00 0x139>;
				phandle = <0x156>;
			};
		};

		touch {

			touch-gpio {
				rockchip,pins = <0x00 0x0d 0x00 0x13b 0x00 0x0e 0x00 0x139>;
				phandle = <0xef>;
			};
		};

		mxc6655xa {

			mxc6655xa_irq_gpio {
				rockchip,pins = <0x03 0x11 0x00 0x139>;
				phandle = <0xfb>;
			};
		};

		pcie {

			pcie-pi6c-oe-en {
				rockchip,pins = <0x03 0x07 0x00 0x139>;
				phandle = <0x15b>;
			};
		};

		leds {

			leds-gpio {
				rockchip,pins = <0x01 0x0a 0x00 0x139 0x01 0x09 0x00 0x139 0x01 0x08 0x00 0x139 0x02 0x11 0x00 0x139>;
				phandle = <0x15d>;
			};
		};

		4g {

			vcc-4g-power-en {
				rockchip,pins = <0x03 0x03 0x00 0x139>;
				phandle = <0x15c>;
			};
		};

		usb-typec {

			usbc0-int {
				rockchip,pins = <0x00 0x11 0x00 0x13b>;
				phandle = <0x4b>;
			};

			vcc5v0-typec0-en {
				rockchip,pins = <0x00 0x05 0x00 0x139>;
			};
		};
	};

	audiopwmout-diff {
		status = "disabled";
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,name = "rockchip,audiopwmout-diff";
		simple-audio-card,mclk-fs = <0x100>;
		simple-audio-card,bitclock-master = <0x143>;
		simple-audio-card,frame-master = <0x143>;

		simple-audio-card,cpu {
			sound-dai = <0x144>;
		};

		simple-audio-card,codec {
			sound-dai = <0x145>;
			phandle = <0x143>;
		};
	};

	dc-12v {
		compatible = "regulator-fixed";
		regulator-name = "dc_12v";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0xb71b00>;
		regulator-max-microvolt = <0xb71b00>;
		phandle = <0x14f>;
	};

	hdmi-sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <0x80>;
		simple-audio-card,name = "rockchip,hdmi";
		status = "okay";

		simple-audio-card,cpu {
			sound-dai = <0x146>;
		};

		simple-audio-card,codec {
			sound-dai = <0x147>;
		};
	};

	rk-headset {
		status = "disabled";
		compatible = "rockchip_headset";
		headset_gpio = <0x4a 0x12 0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0x148>;
	};

	dummy-codec {
		status = "disabled";
		compatible = "rockchip,dummy-codec";
		#sound-dai-cells = <0x00>;
		phandle = <0x14a>;
	};

	pdm-mic-array {
		status = "disabled";
		compatible = "simple-audio-card";
		simple-audio-card,name = "rockchip,pdm-mic-array";

		simple-audio-card,cpu {
			sound-dai = <0x149>;
		};

		simple-audio-card,codec {
			sound-dai = <0x14a>;
		};
	};

	rk809-sound {
		status = "okay";
		compatible = "rockchip,multicodecs-card";
		rockchip,card-name = "rockchip-rk809";
		rockchip,format = "i2s";
		rockchip,mclk-fs = <0x100>;
		rockchip,cpu = <0xe8>;
		rockchip,codec = <0x14b>;
	};

	spdif-sound {
		status = "okay";
		compatible = "simple-audio-card";
		simple-audio-card,name = "ROCKCHIP,SPDIF";

		simple-audio-card,cpu {
			sound-dai = <0x14c>;
		};

		simple-audio-card,codec {
			sound-dai = <0x14d>;
		};
	};

	spdif-out {
		status = "okay";
		compatible = "linux,spdif-dit";
		#sound-dai-cells = <0x00>;
		phandle = <0x14d>;
	};

	vad-sound {
		status = "disabled";
		compatible = "rockchip,multicodecs-card";
		rockchip,card-name = "rockchip,rk3568-vad";
		rockchip,cpu = <0xe8>;
		rockchip,codec = <0x14b 0x14e>;
	};

	vcc3v3-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0x14f>;
		phandle = <0x46>;
	};

	vcc5v0-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x14f>;
		phandle = <0x3e>;
	};

	vcc5v0-host-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x3f 0x06 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x150>;
		regulator-name = "vcc5v0_host";
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x136>;
	};

	vcc5v0-otg-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x3f 0x05 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x151>;
		regulator-name = "vcc5v0_otg";
		phandle = <0x4c>;
	};

	vcc3v3-lcd0-n {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_lcd0_n";
		regulator-boot-on;

		regulator-state-mem {
			regulator-off-in-suspend;
		};
	};

	vcc3v3-lcd1-n {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_lcd1_n";
		regulator-boot-on;
		status = "disabled";

		regulator-state-mem {
			regulator-off-in-suspend;
		};
	};

	test-power {
		status = "okay";
	};

	chosen {
		// linux,initrd-end = <0x00 0xaacf15d>;
		// linux,initrd-start = <0x00 0xa200000>;
		bootargs = "storagemedia=emmc androidboot.storagemedia=emmc androidboot.mode=normal  androidboot.verifiedbootstate=orange rw rootwait earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTLABEL=rootfs rootfstype=ext4 overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 coherent_pool=1m systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1 swiotlb=0x10000 net.ifnames=0 comm-05/20/2025 androidboot.fwver=ddr-v1.21-2d653b3476,spl-v1.14,bl31-v1.44,bl32-v2.12,uboot--boot";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <0x02>;
		rockchip,wake-irq = <0x00>;
		rockchip,irq-mode-enable = <0x01>;
		rockchip,baudrate = <0x16e360>;
		interrupts = <0x00 0xfc 0x08>;
		pinctrl-names = "default";
		pinctrl-0 = <0x10c>;
		status = "okay";
	};

	debug@fd904000 {
		compatible = "rockchip,debug";
		reg = <0x00 0xfd904000 0x00 0x1000 0x00 0xfd905000 0x00 0x1000 0x00 0xfd906000 0x00 0x1000 0x00 0xfd907000 0x00 0x1000>;
	};

	cspmu@fd90c000 {
		compatible = "rockchip,cspmu";
		reg = <0x00 0xfd90c000 0x00 0x1000 0x00 0xfd90d000 0x00 0x1000 0x00 0xfd90e000 0x00 0x1000 0x00 0xfd90f000 0x00 0x1000>;
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <0x49 0x00>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <0x1b7740>;
		poll-interval = <0x64>;

		recovery-key {
			label = "F12";
			linux,code = <0x58>;
			press-threshold-microvolt = <0x6d6>;
		};

		vol-down-key {
			label = "volume down";
			linux,code = <0x72>;
			press-threshold-microvolt = <0x48a1c>;
		};

		menu-key {
			label = "menu";
			linux,code = <0x8b>;
			press-threshold-microvolt = <0xef420>;
		};

		back-key {
			label = "back";
			linux,code = <0x9e>;
			press-threshold-microvolt = <0x13eb9c>;
		};
	};

	vcc2v5-ddr {
		compatible = "regulator-fixed";
		regulator-name = "vcc2v5-sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x2625a0>;
		regulator-max-microvolt = <0x2625a0>;
		vin-supply = <0x46>;
	};

	pcie30-avdd0v9 {
		compatible = "regulator-fixed";
		regulator-name = "pcie30_avdd0v9";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0xdbba0>;
		regulator-max-microvolt = <0xdbba0>;
		vin-supply = <0x46>;
	};

	pcie30-avdd1v8 {
		compatible = "regulator-fixed";
		regulator-name = "pcie30_avdd1v8";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x1b7740>;
		vin-supply = <0x46>;
	};

	gpio-regulator {
		compatible = "regulator-gpio";
		regulator-name = "pcie30_3v3";
		regulator-min-microvolt = <0x186a0>;
		regulator-max-microvolt = <0x325aa0>;
		gpios = <0x3f 0x1c 0x00>;
		gpios-states = <0x01>;
		states = <0x186a0 0x00 0x325aa0 0x01>;
		phandle = <0xc2>;
	};

	vcc3v3-bu {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_bu";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0x3e>;
	};

	sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <0x152 0x01>;
		clock-names = "ext_clock";
		pinctrl-names = "default";
		pinctrl-0 = <0x153>;
		post-power-on-delay-ms = <0x64>;
		reset-gpios = <0x4a 0x1d 0x01>;
		status = "okay";
		phandle = <0xb3>;
	};

	wireless-wlan {
		compatible = "wlan-platdata";
		rockchip,grf = <0x3b>;
		wifi_chip_type = "ap6256";
		pinctrl-names = "default";
		pinctrl-0 = <0x154>;
		WIFI,host_wake_irq = <0x4a 0x1c 0x00>;
		status = "okay";
	};

	wireless-bluetooth {
		compatible = "bluetooth-platdata";
		clocks = <0x152 0x01>;
		clock-names = "ext_clock";
		uart_rts_gpios = <0x91 0x09 0x01>;
		pinctrl-names = "default\0rts_gpio";
		pinctrl-0 = <0x155>;
		pinctrl-1 = <0x156>;
		BT,reset_gpio = <0x4a 0x00 0x00>;
		BT,wake_gpio = <0x4a 0x02 0x00>;
		BT,wake_host_irq = <0x4a 0x01 0x00>;
		status = "okay";
	};

	flash-led {
		compatible = "led,rgb13h";
		label = "pwm-flash-led";
		led-max-microamp = <0x4e20>;
		flash-max-microamp = <0x4e20>;
		flash-max-timeout-us = <0xf4240>;
		pwms = <0x157 0x00 0x61a8 0x00>;
		rockchip,camera-module-index = <0x01>;
		rockchip,camera-module-facing = "front";
		status = "disabled";
	};

	vcc-camera-regulator {
		compatible = "regulator-fixed";
		gpio = <0x102 0x03 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x158>;
		regulator-name = "vcc_camera";
		enable-active-high;
		status = "disabled";
	};

	vcc-hub-reset-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x159 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x15a>;
		regulator-name = "vcc_hub_reset_en";
		regulator-always-on;
	};

	pcie-pi6c-oe-regulator {
		compatible = "regulator-fixed";
		gpio = <0x4a 0x07 0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0x15b>;
		regulator-name = "pcie_pi6c_oe_en";
		regulator-always-on;
	};

	vcc-4g-power-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x4a 0x03 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x15c>;
		regulator-name = "vcc_4g_power_en";
		regulator-always-on;
	};

	leds {
		status = "okay";
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <0x15d>;

		power {
			label = "firefly:blue:power";
			linux,default-trigger = "ir-power-click";
			default-state = "on";
			gpios = <0x159 0x0a 0x00>;
		};

		user {
			label = "firefly:yellow:user";
			linux,default-trigger = "ir-user-click";
			default-state = "off";
			gpios = <0x159 0x09 0x00>;
		};

		diy1 {
			label = "firefly:green:diy";
			linux,default-trigger = "ir-user-click";
			default-state = "off";
			gpios = <0x159 0x08 0x00>;
		};

		diy2 {
			label = "firefly:yellow:diy";
			linux,default-trigger = "ir-user-click";
			default-state = "off";
			gpios = <0x91 0x11 0x00>;
		};
	};
};