#[doc = "CSIC_TOP_EN_REG register accessor: an alias for `Reg<CSIC_TOP_EN_REG_SPEC>`"]
pub type CSIC_TOP_EN_REG = crate::Reg<csic_top_en_reg::CSIC_TOP_EN_REG_SPEC>;
#[doc = "CSIC TOP Enable Register"]
pub mod csic_top_en_reg;
#[doc = "CSIC_PTN_GEN_EN_REG register accessor: an alias for `Reg<CSIC_PTN_GEN_EN_REG_SPEC>`"]
pub type CSIC_PTN_GEN_EN_REG = crate::Reg<csic_ptn_gen_en_reg::CSIC_PTN_GEN_EN_REG_SPEC>;
#[doc = "CSIC Pattern Generation Enable Register"]
pub mod csic_ptn_gen_en_reg;
#[doc = "CSIC_PTN_CTRL_REG register accessor: an alias for `Reg<CSIC_PTN_CTRL_REG_SPEC>`"]
pub type CSIC_PTN_CTRL_REG = crate::Reg<csic_ptn_ctrl_reg::CSIC_PTN_CTRL_REG_SPEC>;
#[doc = "CSIC Pattern Control Register"]
pub mod csic_ptn_ctrl_reg;
#[doc = "CSIC_PTN_LEN_REG register accessor: an alias for `Reg<CSIC_PTN_LEN_REG_SPEC>`"]
pub type CSIC_PTN_LEN_REG = crate::Reg<csic_ptn_len_reg::CSIC_PTN_LEN_REG_SPEC>;
#[doc = "CSIC Pattern Generation Length Register"]
pub mod csic_ptn_len_reg;
#[doc = "CSIC_PTN_ADDR_REG register accessor: an alias for `Reg<CSIC_PTN_ADDR_REG_SPEC>`"]
pub type CSIC_PTN_ADDR_REG = crate::Reg<csic_ptn_addr_reg::CSIC_PTN_ADDR_REG_SPEC>;
#[doc = "CSIC Pattern Generation Address Register"]
pub mod csic_ptn_addr_reg;
#[doc = "CSIC_PTN_ISP_SIZE_REG register accessor: an alias for `Reg<CSIC_PTN_ISP_SIZE_REG_SPEC>`"]
pub type CSIC_PTN_ISP_SIZE_REG = crate::Reg<csic_ptn_isp_size_reg::CSIC_PTN_ISP_SIZE_REG_SPEC>;
#[doc = "CSIC Pattern ISP Size Register"]
pub mod csic_ptn_isp_size_reg;
#[doc = "CSIC_DMA0_INPUT_SEL_REG register accessor: an alias for `Reg<CSIC_DMA0_INPUT_SEL_REG_SPEC>`"]
pub type CSIC_DMA0_INPUT_SEL_REG =
    crate::Reg<csic_dma0_input_sel_reg::CSIC_DMA0_INPUT_SEL_REG_SPEC>;
#[doc = "CSIC DMA0 Input Select Register"]
pub mod csic_dma0_input_sel_reg;
#[doc = "CSIC_DMA1_INPUT_SEL_REG register accessor: an alias for `Reg<CSIC_DMA1_INPUT_SEL_REG_SPEC>`"]
pub type CSIC_DMA1_INPUT_SEL_REG =
    crate::Reg<csic_dma1_input_sel_reg::CSIC_DMA1_INPUT_SEL_REG_SPEC>;
#[doc = "CSIC DMA1 Input Select Register"]
pub mod csic_dma1_input_sel_reg;
#[doc = "CSIC_BIST_CS_REG register accessor: an alias for `Reg<CSIC_BIST_CS_REG_SPEC>`"]
pub type CSIC_BIST_CS_REG = crate::Reg<csic_bist_cs_reg::CSIC_BIST_CS_REG_SPEC>;
#[doc = "CSIC BIST CS Register"]
pub mod csic_bist_cs_reg;
#[doc = "CSIC_BIST_CONTROL_REG register accessor: an alias for `Reg<CSIC_BIST_CONTROL_REG_SPEC>`"]
pub type CSIC_BIST_CONTROL_REG = crate::Reg<csic_bist_control_reg::CSIC_BIST_CONTROL_REG_SPEC>;
#[doc = "CSIC BIST Control Register"]
pub mod csic_bist_control_reg;
#[doc = "CSIC_BIST_START_REG register accessor: an alias for `Reg<CSIC_BIST_START_REG_SPEC>`"]
pub type CSIC_BIST_START_REG = crate::Reg<csic_bist_start_reg::CSIC_BIST_START_REG_SPEC>;
#[doc = "CSIC BIST Start Register"]
pub mod csic_bist_start_reg;
#[doc = "CSIC_BIST_END_REG register accessor: an alias for `Reg<CSIC_BIST_END_REG_SPEC>`"]
pub type CSIC_BIST_END_REG = crate::Reg<csic_bist_end_reg::CSIC_BIST_END_REG_SPEC>;
#[doc = "CSIC BIST End Register"]
pub mod csic_bist_end_reg;
#[doc = "CSIC_BIST_DATA_MASK_REG register accessor: an alias for `Reg<CSIC_BIST_DATA_MASK_REG_SPEC>`"]
pub type CSIC_BIST_DATA_MASK_REG =
    crate::Reg<csic_bist_data_mask_reg::CSIC_BIST_DATA_MASK_REG_SPEC>;
#[doc = "CSIC BIST Data Mask Register"]
pub mod csic_bist_data_mask_reg;
#[doc = "CSIC_MBUS_REQ_MAX_REG register accessor: an alias for `Reg<CSIC_MBUS_REQ_MAX_REG_SPEC>`"]
pub type CSIC_MBUS_REQ_MAX_REG = crate::Reg<csic_mbus_req_max_reg::CSIC_MBUS_REQ_MAX_REG_SPEC>;
#[doc = "CSIC MBUS REQ MAX Register"]
pub mod csic_mbus_req_max_reg;
#[doc = "CSIC_MULF_MOD_REG register accessor: an alias for `Reg<CSIC_MULF_MOD_REG_SPEC>`"]
pub type CSIC_MULF_MOD_REG = crate::Reg<csic_mulf_mod_reg::CSIC_MULF_MOD_REG_SPEC>;
#[doc = "CSIC Multi-Frame Mode Register"]
pub mod csic_mulf_mod_reg;
#[doc = "CSIC_MULF_INT_REG register accessor: an alias for `Reg<CSIC_MULF_INT_REG_SPEC>`"]
pub type CSIC_MULF_INT_REG = crate::Reg<csic_mulf_int_reg::CSIC_MULF_INT_REG_SPEC>;
#[doc = "CSIC Multi-Frame Interrupt Register"]
pub mod csic_mulf_int_reg;
