#[doc = "PRS_EN_REG register accessor: an alias for `Reg<PRS_EN_REG_SPEC>`"]
pub type PRS_EN_REG = crate::Reg<prs_en_reg::PRS_EN_REG_SPEC>;
#[doc = "Parser Enable Register"]
pub mod prs_en_reg;
#[doc = "PRS_NCSIC_IF_CFG_REG register accessor: an alias for `Reg<PRS_NCSIC_IF_CFG_REG_SPEC>`"]
pub type PRS_NCSIC_IF_CFG_REG = crate::Reg<prs_ncsic_if_cfg_reg::PRS_NCSIC_IF_CFG_REG_SPEC>;
#[doc = "Parser NCSIC Interface Configuration Register"]
pub mod prs_ncsic_if_cfg_reg;
#[doc = "PRS_CAP_REG register accessor: an alias for `Reg<PRS_CAP_REG_SPEC>`"]
pub type PRS_CAP_REG = crate::Reg<prs_cap_reg::PRS_CAP_REG_SPEC>;
#[doc = "Parser Capture Register"]
pub mod prs_cap_reg;
#[doc = "CSIC_PRS_SIGNAL_STA_REG register accessor: an alias for `Reg<CSIC_PRS_SIGNAL_STA_REG_SPEC>`"]
pub type CSIC_PRS_SIGNAL_STA_REG =
    crate::Reg<csic_prs_signal_sta_reg::CSIC_PRS_SIGNAL_STA_REG_SPEC>;
#[doc = "CSIC Parser Signal Status Register"]
pub mod csic_prs_signal_sta_reg;
#[doc = "CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG register accessor: an alias for `Reg<CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG_SPEC>`"]
pub type CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG =
    crate::Reg<csic_prs_ncsic_bt656_head_cfg_reg::CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG_SPEC>;
#[doc = "CSIC Parser NCSIC BT656 Header Configuration Register"]
pub mod csic_prs_ncsic_bt656_head_cfg_reg;
#[doc = "PRS_C0_INFMT_REG register accessor: an alias for `Reg<PRS_C0_INFMT_REG_SPEC>`"]
pub type PRS_C0_INFMT_REG = crate::Reg<prs_c0_infmt_reg::PRS_C0_INFMT_REG_SPEC>;
#[doc = "Parser Channel_0 Input Format Register"]
pub mod prs_c0_infmt_reg;
#[doc = "PRS_C0_OUTPUT_HSIZE_REG register accessor: an alias for `Reg<PRS_C0_OUTPUT_HSIZE_REG_SPEC>`"]
pub type PRS_C0_OUTPUT_HSIZE_REG =
    crate::Reg<prs_c0_output_hsize_reg::PRS_C0_OUTPUT_HSIZE_REG_SPEC>;
#[doc = "Parser Channel_0 Output Horizontal Size Register"]
pub mod prs_c0_output_hsize_reg;
#[doc = "PRS_C0_OUTPUT_VSIZE_REG register accessor: an alias for `Reg<PRS_C0_OUTPUT_VSIZE_REG_SPEC>`"]
pub type PRS_C0_OUTPUT_VSIZE_REG =
    crate::Reg<prs_c0_output_vsize_reg::PRS_C0_OUTPUT_VSIZE_REG_SPEC>;
#[doc = "Parser Channel_0 Output Vertical Size Register"]
pub mod prs_c0_output_vsize_reg;
#[doc = "PRS_C0_INPUT_PARA0_REG register accessor: an alias for `Reg<PRS_C0_INPUT_PARA0_REG_SPEC>`"]
pub type PRS_C0_INPUT_PARA0_REG = crate::Reg<prs_c0_input_para0_reg::PRS_C0_INPUT_PARA0_REG_SPEC>;
#[doc = "Parser Channel_0 Input Parameter0 Register"]
pub mod prs_c0_input_para0_reg;
#[doc = "PRS_C0_INPUT_PARA1_REG register accessor: an alias for `Reg<PRS_C0_INPUT_PARA1_REG_SPEC>`"]
pub type PRS_C0_INPUT_PARA1_REG = crate::Reg<prs_c0_input_para1_reg::PRS_C0_INPUT_PARA1_REG_SPEC>;
#[doc = "Parser Channel_0 Input Parameter1 Register"]
pub mod prs_c0_input_para1_reg;
#[doc = "PRS_C0_INPUT_PARA2_REG register accessor: an alias for `Reg<PRS_C0_INPUT_PARA2_REG_SPEC>`"]
pub type PRS_C0_INPUT_PARA2_REG = crate::Reg<prs_c0_input_para2_reg::PRS_C0_INPUT_PARA2_REG_SPEC>;
#[doc = "Parser Channel_0 Input Parameter2 Register"]
pub mod prs_c0_input_para2_reg;
#[doc = "PRS_C0_INPUT_PARA3_REG register accessor: an alias for `Reg<PRS_C0_INPUT_PARA3_REG_SPEC>`"]
pub type PRS_C0_INPUT_PARA3_REG = crate::Reg<prs_c0_input_para3_reg::PRS_C0_INPUT_PARA3_REG_SPEC>;
#[doc = "Parser Channel_0 Input Parameter3 Register"]
pub mod prs_c0_input_para3_reg;
#[doc = "PRS_C0_INT_EN_REG register accessor: an alias for `Reg<PRS_C0_INT_EN_REG_SPEC>`"]
pub type PRS_C0_INT_EN_REG = crate::Reg<prs_c0_int_en_reg::PRS_C0_INT_EN_REG_SPEC>;
#[doc = "Parser Channel_0 Interrupt Enable Register"]
pub mod prs_c0_int_en_reg;
#[doc = "PRS_C0_INT_STA_REG register accessor: an alias for `Reg<PRS_C0_INT_STA_REG_SPEC>`"]
pub type PRS_C0_INT_STA_REG = crate::Reg<prs_c0_int_sta_reg::PRS_C0_INT_STA_REG_SPEC>;
#[doc = "Parser Channel_0 Interrupt Status Register"]
pub mod prs_c0_int_sta_reg;
#[doc = "PRS_CH0_LINE_TIME_REG register accessor: an alias for `Reg<PRS_CH0_LINE_TIME_REG_SPEC>`"]
pub type PRS_CH0_LINE_TIME_REG = crate::Reg<prs_ch0_line_time_reg::PRS_CH0_LINE_TIME_REG_SPEC>;
#[doc = "Parser Channel_0 Line Time Register"]
pub mod prs_ch0_line_time_reg;
#[doc = "PRS_C1_INFMT_REG register accessor: an alias for `Reg<PRS_C1_INFMT_REG_SPEC>`"]
pub type PRS_C1_INFMT_REG = crate::Reg<prs_c1_infmt_reg::PRS_C1_INFMT_REG_SPEC>;
#[doc = "Parser Channel_1 Input Format Register"]
pub mod prs_c1_infmt_reg;
#[doc = "PRS_C1_OUTPUT_HSIZE_REG register accessor: an alias for `Reg<PRS_C1_OUTPUT_HSIZE_REG_SPEC>`"]
pub type PRS_C1_OUTPUT_HSIZE_REG =
    crate::Reg<prs_c1_output_hsize_reg::PRS_C1_OUTPUT_HSIZE_REG_SPEC>;
#[doc = "Parser Channel_1 Output Horizontal Size"]
pub mod prs_c1_output_hsize_reg;
#[doc = "PRS_C1_OUTPUT_VSIZE_REG register accessor: an alias for `Reg<PRS_C1_OUTPUT_VSIZE_REG_SPEC>`"]
pub type PRS_C1_OUTPUT_VSIZE_REG =
    crate::Reg<prs_c1_output_vsize_reg::PRS_C1_OUTPUT_VSIZE_REG_SPEC>;
#[doc = "Parser Channel_1 Output Vertical Size Register"]
pub mod prs_c1_output_vsize_reg;
#[doc = "PRS_C1_INPUT_PARA0_REG register accessor: an alias for `Reg<PRS_C1_INPUT_PARA0_REG_SPEC>`"]
pub type PRS_C1_INPUT_PARA0_REG = crate::Reg<prs_c1_input_para0_reg::PRS_C1_INPUT_PARA0_REG_SPEC>;
#[doc = "Parser Channel_1 Input Parameter0 Register"]
pub mod prs_c1_input_para0_reg;
#[doc = "PRS_C1_INPUT_PARA1_REG register accessor: an alias for `Reg<PRS_C1_INPUT_PARA1_REG_SPEC>`"]
pub type PRS_C1_INPUT_PARA1_REG = crate::Reg<prs_c1_input_para1_reg::PRS_C1_INPUT_PARA1_REG_SPEC>;
#[doc = "Parser Channel_1 Input Parameter1 Register"]
pub mod prs_c1_input_para1_reg;
#[doc = "PRS_C1_INPUT_PARA2_REG register accessor: an alias for `Reg<PRS_C1_INPUT_PARA2_REG_SPEC>`"]
pub type PRS_C1_INPUT_PARA2_REG = crate::Reg<prs_c1_input_para2_reg::PRS_C1_INPUT_PARA2_REG_SPEC>;
#[doc = "Parser Channel_1 Input Parameter2 Register"]
pub mod prs_c1_input_para2_reg;
#[doc = "PRS_C1_INPUT_PARA3_REG register accessor: an alias for `Reg<PRS_C1_INPUT_PARA3_REG_SPEC>`"]
pub type PRS_C1_INPUT_PARA3_REG = crate::Reg<prs_c1_input_para3_reg::PRS_C1_INPUT_PARA3_REG_SPEC>;
#[doc = "Parser Channel_1 Input Parameter3 Register"]
pub mod prs_c1_input_para3_reg;
#[doc = "PRS_C1_INT_EN_REG register accessor: an alias for `Reg<PRS_C1_INT_EN_REG_SPEC>`"]
pub type PRS_C1_INT_EN_REG = crate::Reg<prs_c1_int_en_reg::PRS_C1_INT_EN_REG_SPEC>;
#[doc = "Parser Channel_1 Interrupt Enable Register"]
pub mod prs_c1_int_en_reg;
#[doc = "PRS_C1_INT_STA_REG register accessor: an alias for `Reg<PRS_C1_INT_STA_REG_SPEC>`"]
pub type PRS_C1_INT_STA_REG = crate::Reg<prs_c1_int_sta_reg::PRS_C1_INT_STA_REG_SPEC>;
#[doc = "Parser Channel_1 Interrupt Status Register"]
pub mod prs_c1_int_sta_reg;
#[doc = "PRS_CH1_LINE_TIME_REG register accessor: an alias for `Reg<PRS_CH1_LINE_TIME_REG_SPEC>`"]
pub type PRS_CH1_LINE_TIME_REG = crate::Reg<prs_ch1_line_time_reg::PRS_CH1_LINE_TIME_REG_SPEC>;
#[doc = "Parser Channel_1 Line Time Register"]
pub mod prs_ch1_line_time_reg;
#[doc = "PRS_C2_INFMT_REG register accessor: an alias for `Reg<PRS_C2_INFMT_REG_SPEC>`"]
pub type PRS_C2_INFMT_REG = crate::Reg<prs_c2_infmt_reg::PRS_C2_INFMT_REG_SPEC>;
#[doc = "Parser Channel_2 Input Format Register"]
pub mod prs_c2_infmt_reg;
#[doc = "PRS_C2_OUTPUT_HSIZE_REG register accessor: an alias for `Reg<PRS_C2_OUTPUT_HSIZE_REG_SPEC>`"]
pub type PRS_C2_OUTPUT_HSIZE_REG =
    crate::Reg<prs_c2_output_hsize_reg::PRS_C2_OUTPUT_HSIZE_REG_SPEC>;
#[doc = "Parser Channel_2 Output Horizontal Size Register"]
pub mod prs_c2_output_hsize_reg;
#[doc = "PRS_C2_OUTPUT_VSIZE_REG register accessor: an alias for `Reg<PRS_C2_OUTPUT_VSIZE_REG_SPEC>`"]
pub type PRS_C2_OUTPUT_VSIZE_REG =
    crate::Reg<prs_c2_output_vsize_reg::PRS_C2_OUTPUT_VSIZE_REG_SPEC>;
#[doc = "Parser Channel_2 Output Vertical Size Register"]
pub mod prs_c2_output_vsize_reg;
#[doc = "PRS_C2_INPUT_PARA0_REG register accessor: an alias for `Reg<PRS_C2_INPUT_PARA0_REG_SPEC>`"]
pub type PRS_C2_INPUT_PARA0_REG = crate::Reg<prs_c2_input_para0_reg::PRS_C2_INPUT_PARA0_REG_SPEC>;
#[doc = "Parser Channel_2 Input Parameter0 Register"]
pub mod prs_c2_input_para0_reg;
#[doc = "PRS_C2_INPUT_PARA1_REG register accessor: an alias for `Reg<PRS_C2_INPUT_PARA1_REG_SPEC>`"]
pub type PRS_C2_INPUT_PARA1_REG = crate::Reg<prs_c2_input_para1_reg::PRS_C2_INPUT_PARA1_REG_SPEC>;
#[doc = "Parser Channel_2 Input Parameter1 Register"]
pub mod prs_c2_input_para1_reg;
#[doc = "PRS_C2_INPUT_PARA2_REG register accessor: an alias for `Reg<PRS_C2_INPUT_PARA2_REG_SPEC>`"]
pub type PRS_C2_INPUT_PARA2_REG = crate::Reg<prs_c2_input_para2_reg::PRS_C2_INPUT_PARA2_REG_SPEC>;
#[doc = "Parser Channel_2 Input Parameter2 Register"]
pub mod prs_c2_input_para2_reg;
#[doc = "PRS_C2_INPUT_PARA3_REG register accessor: an alias for `Reg<PRS_C2_INPUT_PARA3_REG_SPEC>`"]
pub type PRS_C2_INPUT_PARA3_REG = crate::Reg<prs_c2_input_para3_reg::PRS_C2_INPUT_PARA3_REG_SPEC>;
#[doc = "Parser Channel_2 Input Parameter3 Register"]
pub mod prs_c2_input_para3_reg;
#[doc = "PRS_C2_INT_EN_REG register accessor: an alias for `Reg<PRS_C2_INT_EN_REG_SPEC>`"]
pub type PRS_C2_INT_EN_REG = crate::Reg<prs_c2_int_en_reg::PRS_C2_INT_EN_REG_SPEC>;
#[doc = "Parser Channel_2 Interrupt Enable Register"]
pub mod prs_c2_int_en_reg;
#[doc = "PRS_C2_INT_STA_REG register accessor: an alias for `Reg<PRS_C2_INT_STA_REG_SPEC>`"]
pub type PRS_C2_INT_STA_REG = crate::Reg<prs_c2_int_sta_reg::PRS_C2_INT_STA_REG_SPEC>;
#[doc = "Parser Channel_2 Interrupt Status Register"]
pub mod prs_c2_int_sta_reg;
#[doc = "PRS_CH2_LINE_TIME_REG register accessor: an alias for `Reg<PRS_CH2_LINE_TIME_REG_SPEC>`"]
pub type PRS_CH2_LINE_TIME_REG = crate::Reg<prs_ch2_line_time_reg::PRS_CH2_LINE_TIME_REG_SPEC>;
#[doc = "Parser Channel_2 Line Time Register"]
pub mod prs_ch2_line_time_reg;
#[doc = "PRS_C3_INFMT_REG register accessor: an alias for `Reg<PRS_C3_INFMT_REG_SPEC>`"]
pub type PRS_C3_INFMT_REG = crate::Reg<prs_c3_infmt_reg::PRS_C3_INFMT_REG_SPEC>;
#[doc = "Parser Channel_3 Input Format Register"]
pub mod prs_c3_infmt_reg;
#[doc = "PRS_C3_OUTPUT_HSIZE_REG register accessor: an alias for `Reg<PRS_C3_OUTPUT_HSIZE_REG_SPEC>`"]
pub type PRS_C3_OUTPUT_HSIZE_REG =
    crate::Reg<prs_c3_output_hsize_reg::PRS_C3_OUTPUT_HSIZE_REG_SPEC>;
#[doc = "Parser Channel_3 Output Horizontal Size Register"]
pub mod prs_c3_output_hsize_reg;
#[doc = "PRS_C3_OUTPUT_VSIZE_REG register accessor: an alias for `Reg<PRS_C3_OUTPUT_VSIZE_REG_SPEC>`"]
pub type PRS_C3_OUTPUT_VSIZE_REG =
    crate::Reg<prs_c3_output_vsize_reg::PRS_C3_OUTPUT_VSIZE_REG_SPEC>;
#[doc = "Parser Channel_3 Output Vertical Size Register"]
pub mod prs_c3_output_vsize_reg;
#[doc = "PRS_C3_INPUT_PARA0_REG register accessor: an alias for `Reg<PRS_C3_INPUT_PARA0_REG_SPEC>`"]
pub type PRS_C3_INPUT_PARA0_REG = crate::Reg<prs_c3_input_para0_reg::PRS_C3_INPUT_PARA0_REG_SPEC>;
#[doc = "Parser Channel_3 Input Parameter0 Register"]
pub mod prs_c3_input_para0_reg;
#[doc = "PRS_C3_INPUT_PARA1_REG register accessor: an alias for `Reg<PRS_C3_INPUT_PARA1_REG_SPEC>`"]
pub type PRS_C3_INPUT_PARA1_REG = crate::Reg<prs_c3_input_para1_reg::PRS_C3_INPUT_PARA1_REG_SPEC>;
#[doc = "Parser Channel_3 Input Parameter1 Register"]
pub mod prs_c3_input_para1_reg;
#[doc = "PRS_C3_INPUT_PARA2_REG register accessor: an alias for `Reg<PRS_C3_INPUT_PARA2_REG_SPEC>`"]
pub type PRS_C3_INPUT_PARA2_REG = crate::Reg<prs_c3_input_para2_reg::PRS_C3_INPUT_PARA2_REG_SPEC>;
#[doc = "Parser Channel_3 Input Parameter2 Register"]
pub mod prs_c3_input_para2_reg;
#[doc = "PRS_C3_INPUT_PARA3_REG register accessor: an alias for `Reg<PRS_C3_INPUT_PARA3_REG_SPEC>`"]
pub type PRS_C3_INPUT_PARA3_REG = crate::Reg<prs_c3_input_para3_reg::PRS_C3_INPUT_PARA3_REG_SPEC>;
#[doc = "Parser Channel_3 Input Parameter3 Register"]
pub mod prs_c3_input_para3_reg;
#[doc = "PRS_C3_INT_EN_REG register accessor: an alias for `Reg<PRS_C3_INT_EN_REG_SPEC>`"]
pub type PRS_C3_INT_EN_REG = crate::Reg<prs_c3_int_en_reg::PRS_C3_INT_EN_REG_SPEC>;
#[doc = "Parser Channel_3 Interrupt Enable Register"]
pub mod prs_c3_int_en_reg;
#[doc = "PRS_C3_INT_STA_REG register accessor: an alias for `Reg<PRS_C3_INT_STA_REG_SPEC>`"]
pub type PRS_C3_INT_STA_REG = crate::Reg<prs_c3_int_sta_reg::PRS_C3_INT_STA_REG_SPEC>;
#[doc = "Parser Channel_3 Interrupt Status Register"]
pub mod prs_c3_int_sta_reg;
#[doc = "PRS_CH3_LINE_TIME_REG register accessor: an alias for `Reg<PRS_CH3_LINE_TIME_REG_SPEC>`"]
pub type PRS_CH3_LINE_TIME_REG = crate::Reg<prs_ch3_line_time_reg::PRS_CH3_LINE_TIME_REG_SPEC>;
#[doc = "Parser Channel_3 Line Time Register"]
pub mod prs_ch3_line_time_reg;
#[doc = "CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG register accessor: an alias for `Reg<CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG_SPEC>`"]
pub type CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG =
    crate::Reg<csic_prs_ncsic_rx_signal0_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG_SPEC>;
#[doc = "CSIC Parser NCSIC RX Signal0 Delay Adjust Register"]
pub mod csic_prs_ncsic_rx_signal0_dly_adj_reg;
#[doc = "CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG register accessor: an alias for `Reg<CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG_SPEC>`"]
pub type CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG =
    crate::Reg<csic_prs_ncsic_rx_signal5_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG_SPEC>;
#[doc = "CSIC Parser NCSIC RX Signal5 Delay Adjust Register"]
pub mod csic_prs_ncsic_rx_signal5_dly_adj_reg;
#[doc = "CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG register accessor: an alias for `Reg<CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG_SPEC>`"]
pub type CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG =
    crate::Reg<csic_prs_ncsic_rx_signal6_dly_adj_reg::CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG_SPEC>;
#[doc = "CSIC Parser NCSIC RX Signal6 Delay Adjust Register"]
pub mod csic_prs_ncsic_rx_signal6_dly_adj_reg;
