#[doc = "CSIC_DMA_EN_REG register accessor: an alias for `Reg<CSIC_DMA_EN_REG_SPEC>`"]
pub type CSIC_DMA_EN_REG = crate::Reg<csic_dma_en_reg::CSIC_DMA_EN_REG_SPEC>;
#[doc = "CSIC DMA Enable Register"]
pub mod csic_dma_en_reg;
#[doc = "CSIC_DMA_CFG_REG register accessor: an alias for `Reg<CSIC_DMA_CFG_REG_SPEC>`"]
pub type CSIC_DMA_CFG_REG = crate::Reg<csic_dma_cfg_reg::CSIC_DMA_CFG_REG_SPEC>;
#[doc = "CSIC DMA Configuration Register"]
pub mod csic_dma_cfg_reg;
#[doc = "CSIC_DMA_HSIZE_REG register accessor: an alias for `Reg<CSIC_DMA_HSIZE_REG_SPEC>`"]
pub type CSIC_DMA_HSIZE_REG = crate::Reg<csic_dma_hsize_reg::CSIC_DMA_HSIZE_REG_SPEC>;
#[doc = "CSIC DMA Horizontal Size Register"]
pub mod csic_dma_hsize_reg;
#[doc = "CSIC_DMA_VSIZE_REG register accessor: an alias for `Reg<CSIC_DMA_VSIZE_REG_SPEC>`"]
pub type CSIC_DMA_VSIZE_REG = crate::Reg<csic_dma_vsize_reg::CSIC_DMA_VSIZE_REG_SPEC>;
#[doc = "CSIC DMA Vertical Size Register"]
pub mod csic_dma_vsize_reg;
#[doc = "CSIC_DMA_F0_BUFA_REG register accessor: an alias for `Reg<CSIC_DMA_F0_BUFA_REG_SPEC>`"]
pub type CSIC_DMA_F0_BUFA_REG = crate::Reg<csic_dma_f0_bufa_reg::CSIC_DMA_F0_BUFA_REG_SPEC>;
#[doc = "CSIC DMA FIFO 0 Output Buffer-A Address Register"]
pub mod csic_dma_f0_bufa_reg;
#[doc = "CSIC_DMA_F0_BUFA_RESULT_REG register accessor: an alias for `Reg<CSIC_DMA_F0_BUFA_RESULT_REG_SPEC>`"]
pub type CSIC_DMA_F0_BUFA_RESULT_REG =
    crate::Reg<csic_dma_f0_bufa_result_reg::CSIC_DMA_F0_BUFA_RESULT_REG_SPEC>;
#[doc = "CSIC DMA FIFO 0 Output Buffer-A Address Result Register"]
pub mod csic_dma_f0_bufa_result_reg;
#[doc = "CSIC_DMA_F1_BUFA_REG register accessor: an alias for `Reg<CSIC_DMA_F1_BUFA_REG_SPEC>`"]
pub type CSIC_DMA_F1_BUFA_REG = crate::Reg<csic_dma_f1_bufa_reg::CSIC_DMA_F1_BUFA_REG_SPEC>;
#[doc = "CSIC DMA FIFO 1 Output Buffer-A Address Register"]
pub mod csic_dma_f1_bufa_reg;
#[doc = "CSIC_DMA_F1_BUFA_RESULT_REG register accessor: an alias for `Reg<CSIC_DMA_F1_BUFA_RESULT_REG_SPEC>`"]
pub type CSIC_DMA_F1_BUFA_RESULT_REG =
    crate::Reg<csic_dma_f1_bufa_result_reg::CSIC_DMA_F1_BUFA_RESULT_REG_SPEC>;
#[doc = "CSIC DMA FIFO 1 Output Buffer-A Address Result Register"]
pub mod csic_dma_f1_bufa_result_reg;
#[doc = "CSIC_DMA_F2_BUFA_REG register accessor: an alias for `Reg<CSIC_DMA_F2_BUFA_REG_SPEC>`"]
pub type CSIC_DMA_F2_BUFA_REG = crate::Reg<csic_dma_f2_bufa_reg::CSIC_DMA_F2_BUFA_REG_SPEC>;
#[doc = "CSIC DMA FIFO 2 Output Buffer-A Address Register"]
pub mod csic_dma_f2_bufa_reg;
#[doc = "CSIC_DMA_F2_BUFA_RESULT_REG register accessor: an alias for `Reg<CSIC_DMA_F2_BUFA_RESULT_REG_SPEC>`"]
pub type CSIC_DMA_F2_BUFA_RESULT_REG =
    crate::Reg<csic_dma_f2_bufa_result_reg::CSIC_DMA_F2_BUFA_RESULT_REG_SPEC>;
#[doc = "CSIC DMA FIFO 2 Output Buffer-A Address Result Register"]
pub mod csic_dma_f2_bufa_result_reg;
#[doc = "CSIC_DMA_BUF_LEN_REG register accessor: an alias for `Reg<CSIC_DMA_BUF_LEN_REG_SPEC>`"]
pub type CSIC_DMA_BUF_LEN_REG = crate::Reg<csic_dma_buf_len_reg::CSIC_DMA_BUF_LEN_REG_SPEC>;
#[doc = "CSIC DMA Buffer Length Register"]
pub mod csic_dma_buf_len_reg;
#[doc = "CSIC_DMA_FLIP_SIZE_REG register accessor: an alias for `Reg<CSIC_DMA_FLIP_SIZE_REG_SPEC>`"]
pub type CSIC_DMA_FLIP_SIZE_REG = crate::Reg<csic_dma_flip_size_reg::CSIC_DMA_FLIP_SIZE_REG_SPEC>;
#[doc = "CSIC DMA Flip Size Register"]
pub mod csic_dma_flip_size_reg;
#[doc = "CSIC_DMA_VI_TO_TH0_REG register accessor: an alias for `Reg<CSIC_DMA_VI_TO_TH0_REG_SPEC>`"]
pub type CSIC_DMA_VI_TO_TH0_REG = crate::Reg<csic_dma_vi_to_th0_reg::CSIC_DMA_VI_TO_TH0_REG_SPEC>;
#[doc = "CSIC DMA Video Input Timeout Threshold0 Register"]
pub mod csic_dma_vi_to_th0_reg;
#[doc = "CSIC_DMA_VI_TO_TH1_REG register accessor: an alias for `Reg<CSIC_DMA_VI_TO_TH1_REG_SPEC>`"]
pub type CSIC_DMA_VI_TO_TH1_REG = crate::Reg<csic_dma_vi_to_th1_reg::CSIC_DMA_VI_TO_TH1_REG_SPEC>;
#[doc = "CSIC DMA Video Input Timeout Threshold1 Register"]
pub mod csic_dma_vi_to_th1_reg;
#[doc = "CSIC_DMA_VI_TO_CNT_VAL_REG register accessor: an alias for `Reg<CSIC_DMA_VI_TO_CNT_VAL_REG_SPEC>`"]
pub type CSIC_DMA_VI_TO_CNT_VAL_REG =
    crate::Reg<csic_dma_vi_to_cnt_val_reg::CSIC_DMA_VI_TO_CNT_VAL_REG_SPEC>;
#[doc = "CSIC DMA Video Input Timeout Counter Value Register"]
pub mod csic_dma_vi_to_cnt_val_reg;
#[doc = "CSIC_DMA_CAP_STA_REG register accessor: an alias for `Reg<CSIC_DMA_CAP_STA_REG_SPEC>`"]
pub type CSIC_DMA_CAP_STA_REG = crate::Reg<csic_dma_cap_sta_reg::CSIC_DMA_CAP_STA_REG_SPEC>;
#[doc = "CSIC DMA Capture Status Register"]
pub mod csic_dma_cap_sta_reg;
#[doc = "CSIC_DMA_INT_EN_REG register accessor: an alias for `Reg<CSIC_DMA_INT_EN_REG_SPEC>`"]
pub type CSIC_DMA_INT_EN_REG = crate::Reg<csic_dma_int_en_reg::CSIC_DMA_INT_EN_REG_SPEC>;
#[doc = "CSIC DMA Interrupt Enable Register"]
pub mod csic_dma_int_en_reg;
#[doc = "CSIC_DMA_INT_STA_REG register accessor: an alias for `Reg<CSIC_DMA_INT_STA_REG_SPEC>`"]
pub type CSIC_DMA_INT_STA_REG = crate::Reg<csic_dma_int_sta_reg::CSIC_DMA_INT_STA_REG_SPEC>;
#[doc = "CSIC DMA Interrupt Status Register"]
pub mod csic_dma_int_sta_reg;
#[doc = "CSIC_DMA_LINE_CNT_REG register accessor: an alias for `Reg<CSIC_DMA_LINE_CNT_REG_SPEC>`"]
pub type CSIC_DMA_LINE_CNT_REG = crate::Reg<csic_dma_line_cnt_reg::CSIC_DMA_LINE_CNT_REG_SPEC>;
#[doc = "CSIC DMA LINE Counter Register"]
pub mod csic_dma_line_cnt_reg;
#[doc = "CSIC_DMA_FRM_CNT_REG register accessor: an alias for `Reg<CSIC_DMA_FRM_CNT_REG_SPEC>`"]
pub type CSIC_DMA_FRM_CNT_REG = crate::Reg<csic_dma_frm_cnt_reg::CSIC_DMA_FRM_CNT_REG_SPEC>;
#[doc = "CSIC DMA Frame Counter Register"]
pub mod csic_dma_frm_cnt_reg;
#[doc = "CSIC_DMA_FRM_CLK_CNT_REG register accessor: an alias for `Reg<CSIC_DMA_FRM_CLK_CNT_REG_SPEC>`"]
pub type CSIC_DMA_FRM_CLK_CNT_REG =
    crate::Reg<csic_dma_frm_clk_cnt_reg::CSIC_DMA_FRM_CLK_CNT_REG_SPEC>;
#[doc = "CSIC DMA Frame Clock Counter Register"]
pub mod csic_dma_frm_clk_cnt_reg;
#[doc = "CSIC_DMA_ACC_ITNL_CLK_CNT_REG register accessor: an alias for `Reg<CSIC_DMA_ACC_ITNL_CLK_CNT_REG_SPEC>`"]
pub type CSIC_DMA_ACC_ITNL_CLK_CNT_REG =
    crate::Reg<csic_dma_acc_itnl_clk_cnt_reg::CSIC_DMA_ACC_ITNL_CLK_CNT_REG_SPEC>;
#[doc = "CSIC DMA Accumulated And Internal Clock Counter Register"]
pub mod csic_dma_acc_itnl_clk_cnt_reg;
#[doc = "CSIC_DMA_FIFO_STAT_REG register accessor: an alias for `Reg<CSIC_DMA_FIFO_STAT_REG_SPEC>`"]
pub type CSIC_DMA_FIFO_STAT_REG = crate::Reg<csic_dma_fifo_stat_reg::CSIC_DMA_FIFO_STAT_REG_SPEC>;
#[doc = "CSIC DMA FIFO Statistic Register"]
pub mod csic_dma_fifo_stat_reg;
#[doc = "CSIC_DMA_FIFO_THRS_REG register accessor: an alias for `Reg<CSIC_DMA_FIFO_THRS_REG_SPEC>`"]
pub type CSIC_DMA_FIFO_THRS_REG = crate::Reg<csic_dma_fifo_thrs_reg::CSIC_DMA_FIFO_THRS_REG_SPEC>;
#[doc = "CSIC DMA FIFO Threshold Register"]
pub mod csic_dma_fifo_thrs_reg;
#[doc = "CSIC_DMA_PCLK_STAT_REG register accessor: an alias for `Reg<CSIC_DMA_PCLK_STAT_REG_SPEC>`"]
pub type CSIC_DMA_PCLK_STAT_REG = crate::Reg<csic_dma_pclk_stat_reg::CSIC_DMA_PCLK_STAT_REG_SPEC>;
#[doc = "CSIC DMA PCLK Statistic Register"]
pub mod csic_dma_pclk_stat_reg;
#[doc = "CSIC_DMA_BUF_ADDR_FIFO0_ENTRY_REG register accessor: an alias for `Reg<CSIC_DMA_BUF_ADDR_FIFO0_ENTRY_REG_SPEC>`"]
pub type CSIC_DMA_BUF_ADDR_FIFO0_ENTRY_REG =
    crate::Reg<csic_dma_buf_addr_fifo0_entry_reg::CSIC_DMA_BUF_ADDR_FIFO0_ENTRY_REG_SPEC>;
#[doc = "CSIC DMA BUF Address FIFO0 Entry Register"]
pub mod csic_dma_buf_addr_fifo0_entry_reg;
#[doc = "CSIC_DMA_BUF_ADDR_FIFO1_ENTRY_REG register accessor: an alias for `Reg<CSIC_DMA_BUF_ADDR_FIFO1_ENTRY_REG_SPEC>`"]
pub type CSIC_DMA_BUF_ADDR_FIFO1_ENTRY_REG =
    crate::Reg<csic_dma_buf_addr_fifo1_entry_reg::CSIC_DMA_BUF_ADDR_FIFO1_ENTRY_REG_SPEC>;
#[doc = "CSIC DMA BUF Address FIFO1 Entry Register"]
pub mod csic_dma_buf_addr_fifo1_entry_reg;
#[doc = "CSIC_DMA_BUF_ADDR_FIFO2_ENTRY_REG register accessor: an alias for `Reg<CSIC_DMA_BUF_ADDR_FIFO2_ENTRY_REG_SPEC>`"]
pub type CSIC_DMA_BUF_ADDR_FIFO2_ENTRY_REG =
    crate::Reg<csic_dma_buf_addr_fifo2_entry_reg::CSIC_DMA_BUF_ADDR_FIFO2_ENTRY_REG_SPEC>;
#[doc = "CSIC DMA BUF Address FIFO2 Entry Register"]
pub mod csic_dma_buf_addr_fifo2_entry_reg;
#[doc = "CSIC_DMA_BUF_TH_REG register accessor: an alias for `Reg<CSIC_DMA_BUF_TH_REG_SPEC>`"]
pub type CSIC_DMA_BUF_TH_REG = crate::Reg<csic_dma_buf_th_reg::CSIC_DMA_BUF_TH_REG_SPEC>;
#[doc = "CSIC DMA BUF Threshold Register"]
pub mod csic_dma_buf_th_reg;
#[doc = "CSIC_DMA_BUF_ADDR_FIFO_CON_REG register accessor: an alias for `Reg<CSIC_DMA_BUF_ADDR_FIFO_CON_REG_SPEC>`"]
pub type CSIC_DMA_BUF_ADDR_FIFO_CON_REG =
    crate::Reg<csic_dma_buf_addr_fifo_con_reg::CSIC_DMA_BUF_ADDR_FIFO_CON_REG_SPEC>;
#[doc = "CSIC DMA BUF Address FIFO Content Register"]
pub mod csic_dma_buf_addr_fifo_con_reg;
#[doc = "CSIC_DMA_STORED_FRM_CNT_REG register accessor: an alias for `Reg<CSIC_DMA_STORED_FRM_CNT_REG_SPEC>`"]
pub type CSIC_DMA_STORED_FRM_CNT_REG =
    crate::Reg<csic_dma_stored_frm_cnt_reg::CSIC_DMA_STORED_FRM_CNT_REG_SPEC>;
#[doc = "CSIC DMA Stored Frame Counter Register"]
pub mod csic_dma_stored_frm_cnt_reg;
#[doc = "CSIC_FEATURE_REG register accessor: an alias for `Reg<CSIC_FEATURE_REG_SPEC>`"]
pub type CSIC_FEATURE_REG = crate::Reg<csic_feature_reg::CSIC_FEATURE_REG_SPEC>;
#[doc = "CSIC DMA Feature List Register"]
pub mod csic_feature_reg;
