//! Auto-generated by `darwin-kperf-codegen`. Do not edit.

use super::{Event, EventInfo};
/// Hardware performance counter events available on M4.
#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
#[non_exhaustive]
pub enum M4Event {
    /// Mispredicted or not predicted branch Speculatively executed.
    ArmBrMisPred,
    /// Predictable branch Speculatively executed.
    ArmBrPred,
    /// Level 1 data cache access.
    ArmL1DCache,
    /// Level 1 data cache long-latency read miss.
    ArmL1DCacheLmissRd,
    /// Attributable Level 1 data cache access, read.
    ArmL1DCacheRd,
    /// Level 1 data cache refill.
    ArmL1DCacheRefill,
    /// No operation sent for execution.
    ArmStall,
    /// No operation issued due to the backend.
    ArmStallBackend,
    /// No operation issued due to the frontend.
    ArmStallFrontend,
    /// No operation sent for execution on a slot.
    ArmStallSlot,
    /// No operation sent for execution on a Slot due to the backend.
    ArmStallSlotBackend,
    /// No operation sent for execution on a Slot due to the frontend.
    ArmStallSlotFrontend,
    /// Atomic or exclusive instruction failed due to contention (for exclusives,
    /// incorrectly undercounts for exclusives when the cache line is initially
    /// found in shared state, however counts correctly for atomics).
    AtomicOrExclusiveFail,
    /// Atomic or exclusive instruction successfully completed (for exclusives,
    /// incorrectly undercounts for exclusives when the cache line is initially
    /// found in shared state, however counts correctly for atomics).
    AtomicOrExclusiveSucc,
    /// Retired indirect call instructions mispredicted.
    BranchCallIndirMispredNonspec,
    /// Retired conditional branch instructions that mispredicted.
    BranchCondMispredNonspec,
    /// Retired indirect branch instructions including calls and returns that
    /// mispredicted.
    BranchIndirMispredNonspec,
    /// Instruction architecturally executed, mispredicted branch.
    BranchMispredNonspec,
    /// Retired return instructions that mispredicted.
    BranchRetIndirMispredNonspec,
    /// Cycles while the core was active.
    CoreActiveCycle,
    /// Fetch Unit internal restarts for any reason. Does not include branch
    /// mispredicts.
    FetchRestart,
    /// `FIXED_CYCLES`.
    FixedCycles,
    /// `FIXED_INSTRUCTIONS`.
    FixedInstructions,
    /// Pipeline flush and restarts that were not due to branch mispredictions or
    /// memory order violations.
    FlushRestartOtherNonspec,
    /// All retired instructions.
    InstAll,
    /// Retired data barrier instructions.
    InstBarrier,
    /// Retired branch instructions including calls and returns.
    InstBranch,
    /// Retired subroutine call instructions.
    InstBranchCall,
    /// Retired conditional branch instructions (on M3 and prior, incorrectly only
    /// counts only B.cond instructions, where on M4 and following, adds
    /// CBZ/CBNZ/TBZ/TBNZ instructions to form the complete set of conditional
    /// branch instructions).
    InstBranchCond,
    /// Retired indirect branch instructions including indirect calls.
    InstBranchIndir,
    /// Retired subroutine return instructions.
    InstBranchRet,
    /// Retired taken branch instructions.
    InstBranchTaken,
    /// Retired non-branch and non-load/store Integer Unit instructions.
    InstIntAlu,
    /// Retired load Integer Unit instructions.
    InstIntLd,
    /// Retired store Integer Unit instructions; does not count DC ZVA (Data Cache
    /// Zero by VA).
    InstIntSt,
    /// Retired load and store instructions; does not count DC ZVA (Data Cache Zero
    /// by VA).
    InstLdst,
    /// Retired non-load/store Advanced SIMD and FP Unit instructions.
    InstSimdAlu,
    /// Retired non-load/store vector Advanced SIMD instructions.
    InstSimdAluVec,
    /// Retired load Advanced SIMD and FP Unit instructions.
    InstSimdLd,
    /// Retired store Advanced SIMD and FP Unit instructions.
    InstSimdSt,
    /// Retired non-load/store SME engine instructions.
    InstSmeEngineAlu,
    /// Retired load SME engine instructions.
    InstSmeEngineLd,
    /// Retired non-load/store SME engine instructions that were packed with another
    /// to reduce instruction bandwidth to the SME engine.
    InstSmeEnginePackingFused,
    /// Retired scalar floating-point SME engine instructions.
    InstSmeEngineScalarfp,
    /// Retired store SME engine instructions.
    InstSmeEngineSt,
    /// Cycles while an interrupt was pending because it was masked.
    InterruptPending,
    /// Loads that missed the L1 Data Cache.
    L1DCacheMissLd,
    /// Retired loads that missed in the L1 Data Cache.
    L1DCacheMissLdNonspec,
    /// Stores that missed the L1 Data Cache.
    L1DCacheMissSt,
    /// Retired stores that missed in the L1 Data Cache.
    L1DCacheMissStNonspec,
    /// Dirty cache lines written back from the L1D Cache toward the Shared L2
    /// Cache.
    L1DCacheWriteback,
    /// Load and store accesses to the L1 Data TLB.
    L1DTlbAccess,
    /// Translations filled into the L1 Data TLB.
    L1DTlbFill,
    /// Load and store accesses that missed the L1 Data TLB.
    L1DTlbMiss,
    /// Retired loads and stores that missed in the L1 Data TLB.
    L1DTlbMissNonspec,
    /// Demand fetch misses that require a new cache line fill of the L1 Instruction
    /// Cache.
    L1ICacheMissDemand,
    /// Translations filled into the L1 Instruction TLB.
    L1ITlbFill,
    /// Demand instruction fetches that missed in the L1 Instruction TLB.
    L1ITlbMissDemand,
    /// Loads and stores that missed in the L2 TLB.
    L2TlbMissData,
    /// Instruction fetches that missed in the L2 TLB.
    L2TlbMissInstruction,
    /// Core load uops blocked by SME accesses to same 4KiB page.
    LdBlockedBySmeLdst,
    /// Load uops that executed with non-temporal hint; excludes SSVE/SME loads
    /// because they utilize the Store Unit.
    LdNtUop,
    /// SME engine load uops with Normal memory type.
    LdSmeNormalUop,
    /// SME engine load uops that executed with non-temporal hint.
    LdSmeNtUop,
    /// Uops that flowed through the Load Unit.
    LdUnitUop,
    /// Cycles while a younger load uop is waiting for data after an L1 Data Cache
    /// miss, and no uop was issued by the scheduler with no critical miss,
    /// prioritized.
    LdUnitWaitingYoungL1DCacheMiss,
    /// SME engine load and store uops where all lanes are inactive due to the
    /// governing predicate; for a page-crossing load or store, the event may
    /// incorrectly count when all of the elements of the low page are predicated
    /// off, even if some of the elements on the high page are active. In Apple
    /// silicon cores, where predication is recommend primarily for data structure
    /// edge control (discarding elements 'past the end of the data structure'),
    /// this scenario should not be common.
    LdstSmePredInactive,
    /// SME engine load and store accesses that crossed a 16KiB page boundary; an
    /// access is considered cross-page if any bytes are accessed in the high
    /// portion (second page), regardless if any bytes are accessed in the low
    /// portion (first page), after predication is applied. An SME operation that
    /// only touches the low portion (first page) after predication is applied is
    /// not considered cross-page.
    LdstSmeXpgUop,
    /// Cycles while an old load or store uop is waiting for data after an L1 Data
    /// Cache miss.
    LdstUnitOldL1DCacheMiss,
    /// Cycles while an old load or store uop is waiting for data after an L1 Data
    /// Cache miss, and no uop was issued by the scheduler, prioritized.
    LdstUnitWaitingOldL1DCacheMiss,
    /// Cycles while the instruction queue to the SME engine is full, and no uop was
    /// issued by the scheduler with no critical miss, prioritized.
    LdstUnitWaitingSmeEngineInstQueueFull,
    /// Cycles while the core is waiting for the SME engine to produce memory data,
    /// and no uop was issued by the scheduler, prioritized.
    LdstUnitWaitingSmeEngineMemData,
    /// Load and store uops that crossed a 64B boundary.
    LdstX64Uop,
    /// Load and store uops that crossed a 16KiB page boundary; an SME access is
    /// considered cross-page if any bytes are accessed in the high portion (second
    /// page), regardless if any bytes are accessed in the low portion (first page),
    /// after predication is applied. An SME operation that only touches the low
    /// portion (first page) after predication is applied is not considered
    /// cross-page.
    LdstXpgUop,
    /// Cycles while the Map Unit had no uops to process and was not stalled.
    MapDispatchBubble,
    /// Cycles while the Map Unit had no uops to process due to L1 Instruction Cache
    /// and was not stalled.
    MapDispatchBubbleIc,
    /// Cycles while the Map Unit had no uops to process due to L1 Instruction TLB
    /// and was not stalled.
    MapDispatchBubbleItlb,
    /// Slots where the Map Unit had no uops to process and was not stalled.
    MapDispatchBubbleSlot,
    /// Mapped core Integer Unit uops for SME engine instructions.
    MapIntSmeUop,
    /// Mapped Integer Unit uops.
    MapIntUop,
    /// Mapped Load and Store Unit uops, including GPR to vector register converts;
    /// includes all instructions sent to the SME engine because they are processed
    /// through the Store Unit.
    MapLdstUop,
    /// Cycles while the Map Unit was stalled while recovering from a flush and
    /// restart.
    MapRecovery,
    /// Cycles while the Map Unit was blocked while rewinding due to flush and
    /// restart.
    MapRewind,
    /// Mapped Advanced SIMD and FP Unit uops.
    MapSimdUop,
    /// Cycles while the Map Unit was stalled for any reason.
    MapStall,
    /// Cycles while the Map Unit was stalled because of Dispatch back pressure.
    MapStallDispatch,
    /// Cycles while the Map Unit was stalled for any reason other than recovery.
    MapStallNonrecovery,
    /// Mapped uops.
    MapUop,
    /// Table walk memory requests on behalf of data accesses.
    MmuTableWalkData,
    /// Table walk memory requests on behalf of instruction fetches.
    MmuTableWalkInstruction,
    /// All retired uops.
    RetireUop,
    /// Cycles while the uop scheduler is empty.
    ScheduleEmpty,
    /// Cycles while the uop scheduler issued at least 1 uop to any execution unit.
    ScheduleUop,
    /// Cycles while the core is waiting for register, predicate, or flag data from
    /// the SME engine, and no uop was issued by the scheduler with no critical
    /// miss, prioritized.
    ScheduleWaitingSmeEngineRegData,
    /// Transitions into SME engine Streaming Mode (PSTATE.SM: 0 to 1).
    SmeEngineSmEnable,
    /// Simultaneous transitions into SME engine Streaming Mode and ZA Mode
    /// (PSTATE.SM: 0 to 1 and PSTATE.ZA: 0 to 1).
    SmeEngineSmZaEnable,
    /// Cycles while SME engine ZA Mode is enabled but Streaming Mode is not
    /// (PSTATE.ZA=1 and PSTATE.SM=0).
    SmeEngineZaEnabledSmDisabled,
    /// Core store uops blocked by SME accesses to same 4KiB page, and any barriers
    /// or store-release uops blocked by SME accesses.
    StBarrierBlockedBySmeLdst,
    /// Retired core store uops that triggered memory order violations with core
    /// load uops.
    StMemOrderViolLdNonspec,
    /// Store uops that executed with non-temporal hint; includes SSVE/SME loads
    /// because they utilize the Store Unit.
    StNtUop,
    /// SME engine store uops with Normal memory type.
    StSmeNormalUop,
    /// SME engine store uops that executed with non-temporal hint.
    StSmeNtUop,
    /// Uops that flowed through the Store Unit.
    StUnitUop,
}
impl M4Event {
    /// Converts a generic [`Event`] to its M4-specific variant, returning `None` if
    /// the event is unavailable on M4.
    #[must_use]
    #[inline]
    pub const fn from_event(event: Event) -> Option<Self> {
        match event {
            Event::ArmBrMisPred => Some(Self::ArmBrMisPred),
            Event::ArmBrPred => Some(Self::ArmBrPred),
            Event::ArmL1DCache => Some(Self::ArmL1DCache),
            Event::ArmL1DCacheLmissRd => Some(Self::ArmL1DCacheLmissRd),
            Event::ArmL1DCacheRd => Some(Self::ArmL1DCacheRd),
            Event::ArmL1DCacheRefill => Some(Self::ArmL1DCacheRefill),
            Event::ArmStall => Some(Self::ArmStall),
            Event::ArmStallBackend => Some(Self::ArmStallBackend),
            Event::ArmStallFrontend => Some(Self::ArmStallFrontend),
            Event::ArmStallSlot => Some(Self::ArmStallSlot),
            Event::ArmStallSlotBackend => Some(Self::ArmStallSlotBackend),
            Event::ArmStallSlotFrontend => Some(Self::ArmStallSlotFrontend),
            Event::AtomicOrExclusiveFail => Some(Self::AtomicOrExclusiveFail),
            Event::AtomicOrExclusiveSucc => Some(Self::AtomicOrExclusiveSucc),
            Event::BranchCallIndirMispredNonspec => Some(Self::BranchCallIndirMispredNonspec),
            Event::BranchCondMispredNonspec => Some(Self::BranchCondMispredNonspec),
            Event::BranchIndirMispredNonspec => Some(Self::BranchIndirMispredNonspec),
            Event::BranchMispredNonspec => Some(Self::BranchMispredNonspec),
            Event::BranchRetIndirMispredNonspec => Some(Self::BranchRetIndirMispredNonspec),
            Event::CoreActiveCycle => Some(Self::CoreActiveCycle),
            Event::FetchRestart => Some(Self::FetchRestart),
            Event::FixedCycles => Some(Self::FixedCycles),
            Event::FixedInstructions => Some(Self::FixedInstructions),
            Event::FlushRestartOtherNonspec => Some(Self::FlushRestartOtherNonspec),
            Event::InstAll => Some(Self::InstAll),
            Event::InstBarrier => Some(Self::InstBarrier),
            Event::InstBranch => Some(Self::InstBranch),
            Event::InstBranchCall => Some(Self::InstBranchCall),
            Event::InstBranchCond => Some(Self::InstBranchCond),
            Event::InstBranchIndir => Some(Self::InstBranchIndir),
            Event::InstBranchRet => Some(Self::InstBranchRet),
            Event::InstBranchTaken => Some(Self::InstBranchTaken),
            Event::InstIntAlu => Some(Self::InstIntAlu),
            Event::InstIntLd => Some(Self::InstIntLd),
            Event::InstIntSt => Some(Self::InstIntSt),
            Event::InstLdst => Some(Self::InstLdst),
            Event::InstSimdAlu => Some(Self::InstSimdAlu),
            Event::InstSimdAluVec => Some(Self::InstSimdAluVec),
            Event::InstSimdLd => Some(Self::InstSimdLd),
            Event::InstSimdSt => Some(Self::InstSimdSt),
            Event::InstSmeEngineAlu => Some(Self::InstSmeEngineAlu),
            Event::InstSmeEngineLd => Some(Self::InstSmeEngineLd),
            Event::InstSmeEnginePackingFused => Some(Self::InstSmeEnginePackingFused),
            Event::InstSmeEngineScalarfp => Some(Self::InstSmeEngineScalarfp),
            Event::InstSmeEngineSt => Some(Self::InstSmeEngineSt),
            Event::InterruptPending => Some(Self::InterruptPending),
            Event::L1DCacheMissLd => Some(Self::L1DCacheMissLd),
            Event::L1DCacheMissLdNonspec => Some(Self::L1DCacheMissLdNonspec),
            Event::L1DCacheMissSt => Some(Self::L1DCacheMissSt),
            Event::L1DCacheMissStNonspec => Some(Self::L1DCacheMissStNonspec),
            Event::L1DCacheWriteback => Some(Self::L1DCacheWriteback),
            Event::L1DTlbAccess => Some(Self::L1DTlbAccess),
            Event::L1DTlbFill => Some(Self::L1DTlbFill),
            Event::L1DTlbMiss => Some(Self::L1DTlbMiss),
            Event::L1DTlbMissNonspec => Some(Self::L1DTlbMissNonspec),
            Event::L1ICacheMissDemand => Some(Self::L1ICacheMissDemand),
            Event::L1ITlbFill => Some(Self::L1ITlbFill),
            Event::L1ITlbMissDemand => Some(Self::L1ITlbMissDemand),
            Event::L2TlbMissData => Some(Self::L2TlbMissData),
            Event::L2TlbMissInstruction => Some(Self::L2TlbMissInstruction),
            Event::LdBlockedBySmeLdst => Some(Self::LdBlockedBySmeLdst),
            Event::LdNtUop => Some(Self::LdNtUop),
            Event::LdSmeNormalUop => Some(Self::LdSmeNormalUop),
            Event::LdSmeNtUop => Some(Self::LdSmeNtUop),
            Event::LdUnitUop => Some(Self::LdUnitUop),
            Event::LdUnitWaitingYoungL1DCacheMiss => Some(Self::LdUnitWaitingYoungL1DCacheMiss),
            Event::LdstSmePredInactive => Some(Self::LdstSmePredInactive),
            Event::LdstSmeXpgUop => Some(Self::LdstSmeXpgUop),
            Event::LdstUnitOldL1DCacheMiss => Some(Self::LdstUnitOldL1DCacheMiss),
            Event::LdstUnitWaitingOldL1DCacheMiss => Some(Self::LdstUnitWaitingOldL1DCacheMiss),
            Event::LdstUnitWaitingSmeEngineInstQueueFull => {
                Some(Self::LdstUnitWaitingSmeEngineInstQueueFull)
            }
            Event::LdstUnitWaitingSmeEngineMemData => Some(Self::LdstUnitWaitingSmeEngineMemData),
            Event::LdstX64Uop => Some(Self::LdstX64Uop),
            Event::LdstXpgUop => Some(Self::LdstXpgUop),
            Event::MapDispatchBubble => Some(Self::MapDispatchBubble),
            Event::MapDispatchBubbleIc => Some(Self::MapDispatchBubbleIc),
            Event::MapDispatchBubbleItlb => Some(Self::MapDispatchBubbleItlb),
            Event::MapDispatchBubbleSlot => Some(Self::MapDispatchBubbleSlot),
            Event::MapIntSmeUop => Some(Self::MapIntSmeUop),
            Event::MapIntUop => Some(Self::MapIntUop),
            Event::MapLdstUop => Some(Self::MapLdstUop),
            Event::MapRecovery => Some(Self::MapRecovery),
            Event::MapRewind => Some(Self::MapRewind),
            Event::MapSimdUop => Some(Self::MapSimdUop),
            Event::MapStall => Some(Self::MapStall),
            Event::MapStallDispatch => Some(Self::MapStallDispatch),
            Event::MapStallNonrecovery => Some(Self::MapStallNonrecovery),
            Event::MapUop => Some(Self::MapUop),
            Event::MmuTableWalkData => Some(Self::MmuTableWalkData),
            Event::MmuTableWalkInstruction => Some(Self::MmuTableWalkInstruction),
            Event::RetireUop => Some(Self::RetireUop),
            Event::ScheduleEmpty => Some(Self::ScheduleEmpty),
            Event::ScheduleUop => Some(Self::ScheduleUop),
            Event::ScheduleWaitingSmeEngineRegData => Some(Self::ScheduleWaitingSmeEngineRegData),
            Event::SmeEngineSmEnable => Some(Self::SmeEngineSmEnable),
            Event::SmeEngineSmZaEnable => Some(Self::SmeEngineSmZaEnable),
            Event::SmeEngineZaEnabledSmDisabled => Some(Self::SmeEngineZaEnabledSmDisabled),
            Event::StBarrierBlockedBySmeLdst => Some(Self::StBarrierBlockedBySmeLdst),
            Event::StMemOrderViolLdNonspec => Some(Self::StMemOrderViolLdNonspec),
            Event::StNtUop => Some(Self::StNtUop),
            Event::StSmeNormalUop => Some(Self::StSmeNormalUop),
            Event::StSmeNtUop => Some(Self::StSmeNtUop),
            Event::StUnitUop => Some(Self::StUnitUop),
        }
    }
}
impl EventInfo for M4Event {
    #[inline]
    fn name(&self) -> &'static str {
        match self {
            Self::ArmBrMisPred => "ARM_BR_MIS_PRED",
            Self::ArmBrPred => "ARM_BR_PRED",
            Self::ArmL1DCache => "ARM_L1D_CACHE",
            Self::ArmL1DCacheLmissRd => "ARM_L1D_CACHE_LMISS_RD",
            Self::ArmL1DCacheRd => "ARM_L1D_CACHE_RD",
            Self::ArmL1DCacheRefill => "ARM_L1D_CACHE_REFILL",
            Self::ArmStall => "ARM_STALL",
            Self::ArmStallBackend => "ARM_STALL_BACKEND",
            Self::ArmStallFrontend => "ARM_STALL_FRONTEND",
            Self::ArmStallSlot => "ARM_STALL_SLOT",
            Self::ArmStallSlotBackend => "ARM_STALL_SLOT_BACKEND",
            Self::ArmStallSlotFrontend => "ARM_STALL_SLOT_FRONTEND",
            Self::AtomicOrExclusiveFail => "ATOMIC_OR_EXCLUSIVE_FAIL",
            Self::AtomicOrExclusiveSucc => "ATOMIC_OR_EXCLUSIVE_SUCC",
            Self::BranchCallIndirMispredNonspec => "BRANCH_CALL_INDIR_MISPRED_NONSPEC",
            Self::BranchCondMispredNonspec => "BRANCH_COND_MISPRED_NONSPEC",
            Self::BranchIndirMispredNonspec => "BRANCH_INDIR_MISPRED_NONSPEC",
            Self::BranchMispredNonspec => "BRANCH_MISPRED_NONSPEC",
            Self::BranchRetIndirMispredNonspec => "BRANCH_RET_INDIR_MISPRED_NONSPEC",
            Self::CoreActiveCycle => "CORE_ACTIVE_CYCLE",
            Self::FetchRestart => "FETCH_RESTART",
            Self::FixedCycles => "FIXED_CYCLES",
            Self::FixedInstructions => "FIXED_INSTRUCTIONS",
            Self::FlushRestartOtherNonspec => "FLUSH_RESTART_OTHER_NONSPEC",
            Self::InstAll => "INST_ALL",
            Self::InstBarrier => "INST_BARRIER",
            Self::InstBranch => "INST_BRANCH",
            Self::InstBranchCall => "INST_BRANCH_CALL",
            Self::InstBranchCond => "INST_BRANCH_COND",
            Self::InstBranchIndir => "INST_BRANCH_INDIR",
            Self::InstBranchRet => "INST_BRANCH_RET",
            Self::InstBranchTaken => "INST_BRANCH_TAKEN",
            Self::InstIntAlu => "INST_INT_ALU",
            Self::InstIntLd => "INST_INT_LD",
            Self::InstIntSt => "INST_INT_ST",
            Self::InstLdst => "INST_LDST",
            Self::InstSimdAlu => "INST_SIMD_ALU",
            Self::InstSimdAluVec => "INST_SIMD_ALU_VEC",
            Self::InstSimdLd => "INST_SIMD_LD",
            Self::InstSimdSt => "INST_SIMD_ST",
            Self::InstSmeEngineAlu => "INST_SME_ENGINE_ALU",
            Self::InstSmeEngineLd => "INST_SME_ENGINE_LD",
            Self::InstSmeEnginePackingFused => "INST_SME_ENGINE_PACKING_FUSED",
            Self::InstSmeEngineScalarfp => "INST_SME_ENGINE_SCALARFP",
            Self::InstSmeEngineSt => "INST_SME_ENGINE_ST",
            Self::InterruptPending => "INTERRUPT_PENDING",
            Self::L1DCacheMissLd => "L1D_CACHE_MISS_LD",
            Self::L1DCacheMissLdNonspec => "L1D_CACHE_MISS_LD_NONSPEC",
            Self::L1DCacheMissSt => "L1D_CACHE_MISS_ST",
            Self::L1DCacheMissStNonspec => "L1D_CACHE_MISS_ST_NONSPEC",
            Self::L1DCacheWriteback => "L1D_CACHE_WRITEBACK",
            Self::L1DTlbAccess => "L1D_TLB_ACCESS",
            Self::L1DTlbFill => "L1D_TLB_FILL",
            Self::L1DTlbMiss => "L1D_TLB_MISS",
            Self::L1DTlbMissNonspec => "L1D_TLB_MISS_NONSPEC",
            Self::L1ICacheMissDemand => "L1I_CACHE_MISS_DEMAND",
            Self::L1ITlbFill => "L1I_TLB_FILL",
            Self::L1ITlbMissDemand => "L1I_TLB_MISS_DEMAND",
            Self::L2TlbMissData => "L2_TLB_MISS_DATA",
            Self::L2TlbMissInstruction => "L2_TLB_MISS_INSTRUCTION",
            Self::LdBlockedBySmeLdst => "LD_BLOCKED_BY_SME_LDST",
            Self::LdNtUop => "LD_NT_UOP",
            Self::LdSmeNormalUop => "LD_SME_NORMAL_UOP",
            Self::LdSmeNtUop => "LD_SME_NT_UOP",
            Self::LdUnitUop => "LD_UNIT_UOP",
            Self::LdUnitWaitingYoungL1DCacheMiss => "LD_UNIT_WAITING_YOUNG_L1D_CACHE_MISS",
            Self::LdstSmePredInactive => "LDST_SME_PRED_INACTIVE",
            Self::LdstSmeXpgUop => "LDST_SME_XPG_UOP",
            Self::LdstUnitOldL1DCacheMiss => "LDST_UNIT_OLD_L1D_CACHE_MISS",
            Self::LdstUnitWaitingOldL1DCacheMiss => "LDST_UNIT_WAITING_OLD_L1D_CACHE_MISS",
            Self::LdstUnitWaitingSmeEngineInstQueueFull => {
                "LDST_UNIT_WAITING_SME_ENGINE_INST_QUEUE_FULL"
            }
            Self::LdstUnitWaitingSmeEngineMemData => "LDST_UNIT_WAITING_SME_ENGINE_MEM_DATA",
            Self::LdstX64Uop => "LDST_X64_UOP",
            Self::LdstXpgUop => "LDST_XPG_UOP",
            Self::MapDispatchBubble => "MAP_DISPATCH_BUBBLE",
            Self::MapDispatchBubbleIc => "MAP_DISPATCH_BUBBLE_IC",
            Self::MapDispatchBubbleItlb => "MAP_DISPATCH_BUBBLE_ITLB",
            Self::MapDispatchBubbleSlot => "MAP_DISPATCH_BUBBLE_SLOT",
            Self::MapIntSmeUop => "MAP_INT_SME_UOP",
            Self::MapIntUop => "MAP_INT_UOP",
            Self::MapLdstUop => "MAP_LDST_UOP",
            Self::MapRecovery => "MAP_RECOVERY",
            Self::MapRewind => "MAP_REWIND",
            Self::MapSimdUop => "MAP_SIMD_UOP",
            Self::MapStall => "MAP_STALL",
            Self::MapStallDispatch => "MAP_STALL_DISPATCH",
            Self::MapStallNonrecovery => "MAP_STALL_NONRECOVERY",
            Self::MapUop => "MAP_UOP",
            Self::MmuTableWalkData => "MMU_TABLE_WALK_DATA",
            Self::MmuTableWalkInstruction => "MMU_TABLE_WALK_INSTRUCTION",
            Self::RetireUop => "RETIRE_UOP",
            Self::ScheduleEmpty => "SCHEDULE_EMPTY",
            Self::ScheduleUop => "SCHEDULE_UOP_ANY",
            Self::ScheduleWaitingSmeEngineRegData => "SCHEDULE_WAITING_SME_ENGINE_REG_DATA",
            Self::SmeEngineSmEnable => "SME_ENGINE_SM_ENABLE",
            Self::SmeEngineSmZaEnable => "SME_ENGINE_SM_ZA_ENABLE",
            Self::SmeEngineZaEnabledSmDisabled => "SME_ENGINE_ZA_ENABLED_SM_DISABLED",
            Self::StBarrierBlockedBySmeLdst => "ST_BARRIER_BLOCKED_BY_SME_LDST",
            Self::StMemOrderViolLdNonspec => "ST_MEM_ORDER_VIOL_LD_NONSPEC",
            Self::StNtUop => "ST_NT_UOP",
            Self::StSmeNormalUop => "ST_SME_NORMAL_UOP",
            Self::StSmeNtUop => "ST_SME_NT_UOP",
            Self::StUnitUop => "ST_UNIT_UOP",
        }
    }

    #[inline]
    fn c_name(&self) -> &'static core::ffi::CStr {
        match self {
            Self::ArmBrMisPred => c"ARM_BR_MIS_PRED",
            Self::ArmBrPred => c"ARM_BR_PRED",
            Self::ArmL1DCache => c"ARM_L1D_CACHE",
            Self::ArmL1DCacheLmissRd => c"ARM_L1D_CACHE_LMISS_RD",
            Self::ArmL1DCacheRd => c"ARM_L1D_CACHE_RD",
            Self::ArmL1DCacheRefill => c"ARM_L1D_CACHE_REFILL",
            Self::ArmStall => c"ARM_STALL",
            Self::ArmStallBackend => c"ARM_STALL_BACKEND",
            Self::ArmStallFrontend => c"ARM_STALL_FRONTEND",
            Self::ArmStallSlot => c"ARM_STALL_SLOT",
            Self::ArmStallSlotBackend => c"ARM_STALL_SLOT_BACKEND",
            Self::ArmStallSlotFrontend => c"ARM_STALL_SLOT_FRONTEND",
            Self::AtomicOrExclusiveFail => c"ATOMIC_OR_EXCLUSIVE_FAIL",
            Self::AtomicOrExclusiveSucc => c"ATOMIC_OR_EXCLUSIVE_SUCC",
            Self::BranchCallIndirMispredNonspec => c"BRANCH_CALL_INDIR_MISPRED_NONSPEC",
            Self::BranchCondMispredNonspec => c"BRANCH_COND_MISPRED_NONSPEC",
            Self::BranchIndirMispredNonspec => c"BRANCH_INDIR_MISPRED_NONSPEC",
            Self::BranchMispredNonspec => c"BRANCH_MISPRED_NONSPEC",
            Self::BranchRetIndirMispredNonspec => c"BRANCH_RET_INDIR_MISPRED_NONSPEC",
            Self::CoreActiveCycle => c"CORE_ACTIVE_CYCLE",
            Self::FetchRestart => c"FETCH_RESTART",
            Self::FixedCycles => c"FIXED_CYCLES",
            Self::FixedInstructions => c"FIXED_INSTRUCTIONS",
            Self::FlushRestartOtherNonspec => c"FLUSH_RESTART_OTHER_NONSPEC",
            Self::InstAll => c"INST_ALL",
            Self::InstBarrier => c"INST_BARRIER",
            Self::InstBranch => c"INST_BRANCH",
            Self::InstBranchCall => c"INST_BRANCH_CALL",
            Self::InstBranchCond => c"INST_BRANCH_COND",
            Self::InstBranchIndir => c"INST_BRANCH_INDIR",
            Self::InstBranchRet => c"INST_BRANCH_RET",
            Self::InstBranchTaken => c"INST_BRANCH_TAKEN",
            Self::InstIntAlu => c"INST_INT_ALU",
            Self::InstIntLd => c"INST_INT_LD",
            Self::InstIntSt => c"INST_INT_ST",
            Self::InstLdst => c"INST_LDST",
            Self::InstSimdAlu => c"INST_SIMD_ALU",
            Self::InstSimdAluVec => c"INST_SIMD_ALU_VEC",
            Self::InstSimdLd => c"INST_SIMD_LD",
            Self::InstSimdSt => c"INST_SIMD_ST",
            Self::InstSmeEngineAlu => c"INST_SME_ENGINE_ALU",
            Self::InstSmeEngineLd => c"INST_SME_ENGINE_LD",
            Self::InstSmeEnginePackingFused => c"INST_SME_ENGINE_PACKING_FUSED",
            Self::InstSmeEngineScalarfp => c"INST_SME_ENGINE_SCALARFP",
            Self::InstSmeEngineSt => c"INST_SME_ENGINE_ST",
            Self::InterruptPending => c"INTERRUPT_PENDING",
            Self::L1DCacheMissLd => c"L1D_CACHE_MISS_LD",
            Self::L1DCacheMissLdNonspec => c"L1D_CACHE_MISS_LD_NONSPEC",
            Self::L1DCacheMissSt => c"L1D_CACHE_MISS_ST",
            Self::L1DCacheMissStNonspec => c"L1D_CACHE_MISS_ST_NONSPEC",
            Self::L1DCacheWriteback => c"L1D_CACHE_WRITEBACK",
            Self::L1DTlbAccess => c"L1D_TLB_ACCESS",
            Self::L1DTlbFill => c"L1D_TLB_FILL",
            Self::L1DTlbMiss => c"L1D_TLB_MISS",
            Self::L1DTlbMissNonspec => c"L1D_TLB_MISS_NONSPEC",
            Self::L1ICacheMissDemand => c"L1I_CACHE_MISS_DEMAND",
            Self::L1ITlbFill => c"L1I_TLB_FILL",
            Self::L1ITlbMissDemand => c"L1I_TLB_MISS_DEMAND",
            Self::L2TlbMissData => c"L2_TLB_MISS_DATA",
            Self::L2TlbMissInstruction => c"L2_TLB_MISS_INSTRUCTION",
            Self::LdBlockedBySmeLdst => c"LD_BLOCKED_BY_SME_LDST",
            Self::LdNtUop => c"LD_NT_UOP",
            Self::LdSmeNormalUop => c"LD_SME_NORMAL_UOP",
            Self::LdSmeNtUop => c"LD_SME_NT_UOP",
            Self::LdUnitUop => c"LD_UNIT_UOP",
            Self::LdUnitWaitingYoungL1DCacheMiss => c"LD_UNIT_WAITING_YOUNG_L1D_CACHE_MISS",
            Self::LdstSmePredInactive => c"LDST_SME_PRED_INACTIVE",
            Self::LdstSmeXpgUop => c"LDST_SME_XPG_UOP",
            Self::LdstUnitOldL1DCacheMiss => c"LDST_UNIT_OLD_L1D_CACHE_MISS",
            Self::LdstUnitWaitingOldL1DCacheMiss => c"LDST_UNIT_WAITING_OLD_L1D_CACHE_MISS",
            Self::LdstUnitWaitingSmeEngineInstQueueFull => {
                c"LDST_UNIT_WAITING_SME_ENGINE_INST_QUEUE_FULL"
            }
            Self::LdstUnitWaitingSmeEngineMemData => c"LDST_UNIT_WAITING_SME_ENGINE_MEM_DATA",
            Self::LdstX64Uop => c"LDST_X64_UOP",
            Self::LdstXpgUop => c"LDST_XPG_UOP",
            Self::MapDispatchBubble => c"MAP_DISPATCH_BUBBLE",
            Self::MapDispatchBubbleIc => c"MAP_DISPATCH_BUBBLE_IC",
            Self::MapDispatchBubbleItlb => c"MAP_DISPATCH_BUBBLE_ITLB",
            Self::MapDispatchBubbleSlot => c"MAP_DISPATCH_BUBBLE_SLOT",
            Self::MapIntSmeUop => c"MAP_INT_SME_UOP",
            Self::MapIntUop => c"MAP_INT_UOP",
            Self::MapLdstUop => c"MAP_LDST_UOP",
            Self::MapRecovery => c"MAP_RECOVERY",
            Self::MapRewind => c"MAP_REWIND",
            Self::MapSimdUop => c"MAP_SIMD_UOP",
            Self::MapStall => c"MAP_STALL",
            Self::MapStallDispatch => c"MAP_STALL_DISPATCH",
            Self::MapStallNonrecovery => c"MAP_STALL_NONRECOVERY",
            Self::MapUop => c"MAP_UOP",
            Self::MmuTableWalkData => c"MMU_TABLE_WALK_DATA",
            Self::MmuTableWalkInstruction => c"MMU_TABLE_WALK_INSTRUCTION",
            Self::RetireUop => c"RETIRE_UOP",
            Self::ScheduleEmpty => c"SCHEDULE_EMPTY",
            Self::ScheduleUop => c"SCHEDULE_UOP_ANY",
            Self::ScheduleWaitingSmeEngineRegData => c"SCHEDULE_WAITING_SME_ENGINE_REG_DATA",
            Self::SmeEngineSmEnable => c"SME_ENGINE_SM_ENABLE",
            Self::SmeEngineSmZaEnable => c"SME_ENGINE_SM_ZA_ENABLE",
            Self::SmeEngineZaEnabledSmDisabled => c"SME_ENGINE_ZA_ENABLED_SM_DISABLED",
            Self::StBarrierBlockedBySmeLdst => c"ST_BARRIER_BLOCKED_BY_SME_LDST",
            Self::StMemOrderViolLdNonspec => c"ST_MEM_ORDER_VIOL_LD_NONSPEC",
            Self::StNtUop => c"ST_NT_UOP",
            Self::StSmeNormalUop => c"ST_SME_NORMAL_UOP",
            Self::StSmeNtUop => c"ST_SME_NT_UOP",
            Self::StUnitUop => c"ST_UNIT_UOP",
        }
    }

    #[inline]
    fn description(&self) -> &'static str {
        match self {
            Self::ArmBrMisPred => "Mispredicted or not predicted branch Speculatively executed",
            Self::ArmBrPred => "Predictable branch Speculatively executed",
            Self::ArmL1DCache => "Level 1 data cache access",
            Self::ArmL1DCacheLmissRd => "Level 1 data cache long-latency read miss",
            Self::ArmL1DCacheRd => "Attributable Level 1 data cache access, read",
            Self::ArmL1DCacheRefill => "Level 1 data cache refill",
            Self::ArmStall => "No operation sent for execution",
            Self::ArmStallBackend => "No operation issued due to the backend",
            Self::ArmStallFrontend => "No operation issued due to the frontend",
            Self::ArmStallSlot => "No operation sent for execution on a slot",
            Self::ArmStallSlotBackend => {
                "No operation sent for execution on a Slot due to the backend"
            }
            Self::ArmStallSlotFrontend => {
                "No operation sent for execution on a Slot due to the frontend"
            }
            Self::AtomicOrExclusiveFail => {
                "Atomic or exclusive instruction failed due to contention (for exclusives, \
                 incorrectly undercounts for exclusives when the cache line is initially found in \
                 shared state, however counts correctly for atomics)"
            }
            Self::AtomicOrExclusiveSucc => {
                "Atomic or exclusive instruction successfully completed (for exclusives, \
                 incorrectly undercounts for exclusives when the cache line is initially found in \
                 shared state, however counts correctly for atomics)"
            }
            Self::BranchCallIndirMispredNonspec => {
                "Retired indirect call instructions mispredicted"
            }
            Self::BranchCondMispredNonspec => {
                "Retired conditional branch instructions that mispredicted"
            }
            Self::BranchIndirMispredNonspec => {
                "Retired indirect branch instructions including calls and returns that mispredicted"
            }
            Self::BranchMispredNonspec => {
                "Instruction architecturally executed, mispredicted branch"
            }
            Self::BranchRetIndirMispredNonspec => "Retired return instructions that mispredicted",
            Self::CoreActiveCycle => "Cycles while the core was active",
            Self::FetchRestart => {
                "Fetch Unit internal restarts for any reason. Does not include branch mispredicts"
            }
            Self::FixedCycles => "",
            Self::FixedInstructions => "",
            Self::FlushRestartOtherNonspec => {
                "Pipeline flush and restarts that were not due to branch mispredictions or memory \
                 order violations"
            }
            Self::InstAll => "All retired instructions",
            Self::InstBarrier => "Retired data barrier instructions",
            Self::InstBranch => "Retired branch instructions including calls and returns",
            Self::InstBranchCall => "Retired subroutine call instructions",
            Self::InstBranchCond => {
                "Retired conditional branch instructions (on M3 and prior, incorrectly only counts \
                 only B.cond instructions, where on M4 and following, adds CBZ/CBNZ/TBZ/TBNZ \
                 instructions to form the complete set of conditional branch instructions)"
            }
            Self::InstBranchIndir => {
                "Retired indirect branch instructions including indirect calls"
            }
            Self::InstBranchRet => "Retired subroutine return instructions",
            Self::InstBranchTaken => "Retired taken branch instructions",
            Self::InstIntAlu => "Retired non-branch and non-load/store Integer Unit instructions",
            Self::InstIntLd => "Retired load Integer Unit instructions",
            Self::InstIntSt => {
                "Retired store Integer Unit instructions; does not count DC ZVA (Data Cache Zero \
                 by VA)"
            }
            Self::InstLdst => {
                "Retired load and store instructions; does not count DC ZVA (Data Cache Zero by VA)"
            }
            Self::InstSimdAlu => "Retired non-load/store Advanced SIMD and FP Unit instructions",
            Self::InstSimdAluVec => "Retired non-load/store vector Advanced SIMD  instructions",
            Self::InstSimdLd => "Retired load Advanced SIMD and FP Unit instructions",
            Self::InstSimdSt => "Retired store Advanced SIMD and FP Unit instructions",
            Self::InstSmeEngineAlu => "Retired non-load/store SME engine instructions",
            Self::InstSmeEngineLd => "Retired load SME engine instructions",
            Self::InstSmeEnginePackingFused => {
                "Retired non-load/store SME engine instructions that were packed with another to \
                 reduce instruction bandwidth to the SME engine"
            }
            Self::InstSmeEngineScalarfp => "Retired scalar floating-point SME engine instructions",
            Self::InstSmeEngineSt => "Retired store SME engine instructions",
            Self::InterruptPending => "Cycles while an interrupt was pending because it was masked",
            Self::L1DCacheMissLd => "Loads that missed the L1 Data Cache",
            Self::L1DCacheMissLdNonspec => "Retired loads that missed in the L1 Data Cache",
            Self::L1DCacheMissSt => "Stores that missed the L1 Data Cache",
            Self::L1DCacheMissStNonspec => "Retired stores that missed in the L1 Data Cache",
            Self::L1DCacheWriteback => {
                "Dirty cache lines written back from the L1D Cache toward the Shared L2 Cache"
            }
            Self::L1DTlbAccess => "Load and store accesses to the L1 Data TLB",
            Self::L1DTlbFill => "Translations filled into the L1 Data TLB",
            Self::L1DTlbMiss => "Load and store accesses that missed the L1 Data TLB",
            Self::L1DTlbMissNonspec => "Retired loads and stores that missed in the L1 Data TLB",
            Self::L1ICacheMissDemand => {
                "Demand fetch misses that require a new cache line fill of the L1 Instruction Cache"
            }
            Self::L1ITlbFill => "Translations filled into the L1 Instruction TLB",
            Self::L1ITlbMissDemand => {
                "Demand instruction fetches that missed in the L1 Instruction TLB"
            }
            Self::L2TlbMissData => "Loads and stores that missed in the L2 TLB",
            Self::L2TlbMissInstruction => "Instruction fetches that missed in the L2 TLB",
            Self::LdBlockedBySmeLdst => "Core load uops blocked by SME accesses to same 4KiB page",
            Self::LdNtUop => {
                "Load uops that executed with non-temporal hint; excludes SSVE/SME loads because \
                 they utilize the Store Unit"
            }
            Self::LdSmeNormalUop => "SME engine load uops with Normal memory type",
            Self::LdSmeNtUop => "SME engine load uops that executed with non-temporal hint",
            Self::LdUnitUop => "Uops that flowed through the Load Unit",
            Self::LdUnitWaitingYoungL1DCacheMiss => {
                "Cycles while a younger load uop is waiting for data after an L1 Data Cache miss, \
                 and no uop was issued by the scheduler with no critical miss, prioritized"
            }
            Self::LdstSmePredInactive => {
                "SME engine load and store uops where all lanes are inactive due to the governing \
                 predicate; for a page-crossing load or store, the event may incorrectly count \
                 when all of the elements of the low page are predicated off, even if some of the \
                 elements on the high page are active. In Apple silicon cores, where predication \
                 is recommend primarily for data structure edge control (discarding elements 'past \
                 the end of the data structure'), this scenario should not be common."
            }
            Self::LdstSmeXpgUop => {
                "SME engine load and store accesses that crossed a 16KiB page boundary; an access \
                 is considered cross-page if any bytes are accessed in the high portion (second \
                 page), regardless if any bytes are accessed in the low portion (first page), \
                 after predication is applied. An SME operation that only touches the low portion \
                 (first page) after predication is applied is not considered cross-page."
            }
            Self::LdstUnitOldL1DCacheMiss => {
                "Cycles while an old load or store uop is waiting for data after an L1 Data Cache \
                 miss"
            }
            Self::LdstUnitWaitingOldL1DCacheMiss => {
                "Cycles while an old load or store uop is waiting for data after an L1 Data Cache \
                 miss, and no uop was issued by the scheduler, prioritized"
            }
            Self::LdstUnitWaitingSmeEngineInstQueueFull => {
                "Cycles while the instruction queue to the SME engine is full, and no uop was \
                 issued by the scheduler with no critical miss, prioritized"
            }
            Self::LdstUnitWaitingSmeEngineMemData => {
                "Cycles while the core is waiting for the SME engine to produce memory data, and \
                 no uop was issued by the scheduler, prioritized"
            }
            Self::LdstX64Uop => "Load and store uops that crossed a 64B boundary",
            Self::LdstXpgUop => {
                "Load and store uops that crossed a 16KiB page boundary; an SME access is \
                 considered cross-page if any bytes are accessed in the high portion (second \
                 page), regardless if any bytes are accessed in the low portion (first page), \
                 after predication is applied. An SME operation that only touches the low portion \
                 (first page) after predication is applied is not considered cross-page."
            }
            Self::MapDispatchBubble => {
                "Cycles while the Map Unit had no uops to process and was not stalled"
            }
            Self::MapDispatchBubbleIc => {
                "Cycles while the Map Unit had no uops to process due to L1 Instruction Cache and \
                 was not stalled"
            }
            Self::MapDispatchBubbleItlb => {
                "Cycles while the Map Unit had no uops to process due to L1 Instruction TLB and \
                 was not stalled"
            }
            Self::MapDispatchBubbleSlot => {
                "Slots where the Map Unit had no uops to process and was not stalled"
            }
            Self::MapIntSmeUop => "Mapped core Integer Unit uops for SME engine instructions",
            Self::MapIntUop => "Mapped Integer Unit uops",
            Self::MapLdstUop => {
                "Mapped Load and Store Unit uops, including GPR to vector register converts; \
                 includes all instructions sent to the SME engine because they are processed \
                 through the Store Unit"
            }
            Self::MapRecovery => {
                "Cycles while the Map Unit was stalled while recovering from a flush and restart"
            }
            Self::MapRewind => {
                "Cycles while the Map Unit was blocked while rewinding due to flush and restart"
            }
            Self::MapSimdUop => "Mapped Advanced SIMD and FP Unit uops",
            Self::MapStall => "Cycles while the Map Unit was stalled for any reason",
            Self::MapStallDispatch => {
                "Cycles while the Map Unit was stalled because of Dispatch back pressure"
            }
            Self::MapStallNonrecovery => {
                "Cycles while the Map Unit was stalled for any reason other than recovery"
            }
            Self::MapUop => "Mapped uops",
            Self::MmuTableWalkData => "Table walk memory requests on behalf of data accesses",
            Self::MmuTableWalkInstruction => {
                "Table walk memory requests on behalf of instruction fetches"
            }
            Self::RetireUop => "All retired uops",
            Self::ScheduleEmpty => "Cycles while the uop scheduler is empty",
            Self::ScheduleUop => {
                "Cycles while the uop scheduler issued at least 1 uop to any execution unit"
            }
            Self::ScheduleWaitingSmeEngineRegData => {
                "Cycles while the core is waiting for register, predicate, or flag data from the \
                 SME engine, and no uop was issued by the scheduler with no critical miss, \
                 prioritized"
            }
            Self::SmeEngineSmEnable => {
                "Transitions into SME engine Streaming Mode (PSTATE.SM: 0 to 1)"
            }
            Self::SmeEngineSmZaEnable => {
                "Simultaneous transitions into SME engine Streaming Mode and ZA Mode (PSTATE.SM: 0 \
                 to 1 and PSTATE.ZA: 0 to 1)"
            }
            Self::SmeEngineZaEnabledSmDisabled => {
                "Cycles while SME engine ZA Mode is enabled but Streaming Mode is not (PSTATE.ZA=1 \
                 and PSTATE.SM=0)"
            }
            Self::StBarrierBlockedBySmeLdst => {
                "Core store uops blocked by SME accesses to same 4KiB page, and any barriers or \
                 store-release uops blocked by SME accesses"
            }
            Self::StMemOrderViolLdNonspec => {
                "Retired core store uops that triggered memory order violations with core load uops"
            }
            Self::StNtUop => {
                "Store uops that executed with non-temporal hint; includes SSVE/SME loads because \
                 they utilize the Store Unit"
            }
            Self::StSmeNormalUop => "SME engine store uops with Normal memory type",
            Self::StSmeNtUop => "SME engine store uops that executed with non-temporal hint",
            Self::StUnitUop => "Uops that flowed through the Store Unit",
        }
    }

    #[inline]
    fn counters_mask(&self) -> Option<u32> {
        match self {
            Self::ArmBrMisPred => None,
            Self::ArmBrPred => None,
            Self::ArmL1DCache => None,
            Self::ArmL1DCacheLmissRd => None,
            Self::ArmL1DCacheRd => None,
            Self::ArmL1DCacheRefill => None,
            Self::ArmStall => None,
            Self::ArmStallBackend => None,
            Self::ArmStallFrontend => None,
            Self::ArmStallSlot => None,
            Self::ArmStallSlotBackend => None,
            Self::ArmStallSlotFrontend => None,
            Self::AtomicOrExclusiveFail => None,
            Self::AtomicOrExclusiveSucc => None,
            Self::BranchCallIndirMispredNonspec => Some(252u32),
            Self::BranchCondMispredNonspec => Some(252u32),
            Self::BranchIndirMispredNonspec => Some(252u32),
            Self::BranchMispredNonspec => Some(252u32),
            Self::BranchRetIndirMispredNonspec => Some(252u32),
            Self::CoreActiveCycle => None,
            Self::FetchRestart => None,
            Self::FixedCycles => Some(1u32),
            Self::FixedInstructions => Some(2u32),
            Self::FlushRestartOtherNonspec => None,
            Self::InstAll => Some(252u32),
            Self::InstBarrier => Some(252u32),
            Self::InstBranch => Some(252u32),
            Self::InstBranchCall => Some(252u32),
            Self::InstBranchCond => Some(252u32),
            Self::InstBranchIndir => Some(252u32),
            Self::InstBranchRet => Some(252u32),
            Self::InstBranchTaken => Some(252u32),
            Self::InstIntAlu => Some(128u32),
            Self::InstIntLd => Some(252u32),
            Self::InstIntSt => Some(128u32),
            Self::InstLdst => Some(128u32),
            Self::InstSimdAlu => Some(128u32),
            Self::InstSimdAluVec => Some(128u32),
            Self::InstSimdLd => Some(252u32),
            Self::InstSimdSt => Some(252u32),
            Self::InstSmeEngineAlu => Some(252u32),
            Self::InstSmeEngineLd => Some(252u32),
            Self::InstSmeEnginePackingFused => None,
            Self::InstSmeEngineScalarfp => Some(252u32),
            Self::InstSmeEngineSt => Some(252u32),
            Self::InterruptPending => None,
            Self::L1DCacheMissLd => None,
            Self::L1DCacheMissLdNonspec => Some(252u32),
            Self::L1DCacheMissSt => None,
            Self::L1DCacheMissStNonspec => Some(252u32),
            Self::L1DCacheWriteback => None,
            Self::L1DTlbAccess => None,
            Self::L1DTlbFill => None,
            Self::L1DTlbMiss => None,
            Self::L1DTlbMissNonspec => Some(252u32),
            Self::L1ICacheMissDemand => None,
            Self::L1ITlbFill => None,
            Self::L1ITlbMissDemand => None,
            Self::L2TlbMissData => None,
            Self::L2TlbMissInstruction => None,
            Self::LdBlockedBySmeLdst => None,
            Self::LdNtUop => None,
            Self::LdSmeNormalUop => None,
            Self::LdSmeNtUop => None,
            Self::LdUnitUop => None,
            Self::LdUnitWaitingYoungL1DCacheMiss => None,
            Self::LdstSmePredInactive => None,
            Self::LdstSmeXpgUop => None,
            Self::LdstUnitOldL1DCacheMiss => None,
            Self::LdstUnitWaitingOldL1DCacheMiss => None,
            Self::LdstUnitWaitingSmeEngineInstQueueFull => None,
            Self::LdstUnitWaitingSmeEngineMemData => None,
            Self::LdstX64Uop => None,
            Self::LdstXpgUop => None,
            Self::MapDispatchBubble => None,
            Self::MapDispatchBubbleIc => None,
            Self::MapDispatchBubbleItlb => None,
            Self::MapDispatchBubbleSlot => None,
            Self::MapIntSmeUop => None,
            Self::MapIntUop => None,
            Self::MapLdstUop => None,
            Self::MapRecovery => None,
            Self::MapRewind => None,
            Self::MapSimdUop => None,
            Self::MapStall => None,
            Self::MapStallDispatch => None,
            Self::MapStallNonrecovery => None,
            Self::MapUop => None,
            Self::MmuTableWalkData => None,
            Self::MmuTableWalkInstruction => None,
            Self::RetireUop => Some(252u32),
            Self::ScheduleEmpty => None,
            Self::ScheduleUop => None,
            Self::ScheduleWaitingSmeEngineRegData => None,
            Self::SmeEngineSmEnable => None,
            Self::SmeEngineSmZaEnable => None,
            Self::SmeEngineZaEnabledSmDisabled => None,
            Self::StBarrierBlockedBySmeLdst => None,
            Self::StMemOrderViolLdNonspec => Some(252u32),
            Self::StNtUop => None,
            Self::StSmeNormalUop => None,
            Self::StSmeNtUop => None,
            Self::StUnitUop => None,
        }
    }

    #[inline]
    fn number(&self) -> Option<u16> {
        match self {
            Self::ArmBrMisPred => Some(16u16),
            Self::ArmBrPred => Some(18u16),
            Self::ArmL1DCache => Some(4u16),
            Self::ArmL1DCacheLmissRd => Some(57u16),
            Self::ArmL1DCacheRd => Some(64u16),
            Self::ArmL1DCacheRefill => Some(3u16),
            Self::ArmStall => Some(60u16),
            Self::ArmStallBackend => Some(36u16),
            Self::ArmStallFrontend => Some(35u16),
            Self::ArmStallSlot => Some(63u16),
            Self::ArmStallSlotBackend => Some(61u16),
            Self::ArmStallSlotFrontend => Some(62u16),
            Self::AtomicOrExclusiveFail => Some(1460u16),
            Self::AtomicOrExclusiveSucc => Some(1459u16),
            Self::BranchCallIndirMispredNonspec => Some(2250u16),
            Self::BranchCondMispredNonspec => Some(2245u16),
            Self::BranchIndirMispredNonspec => Some(2246u16),
            Self::BranchMispredNonspec => Some(34u16),
            Self::BranchRetIndirMispredNonspec => Some(2248u16),
            Self::CoreActiveCycle => Some(17u16),
            Self::FetchRestart => Some(478u16),
            Self::FixedCycles => None,
            Self::FixedInstructions => None,
            Self::FlushRestartOtherNonspec => Some(2180u16),
            Self::InstAll => Some(8u16),
            Self::InstBarrier => Some(2204u16),
            Self::InstBranch => Some(33u16),
            Self::InstBranchCall => Some(2190u16),
            Self::InstBranchCond => Some(2196u16),
            Self::InstBranchIndir => Some(2195u16),
            Self::InstBranchRet => Some(2191u16),
            Self::InstBranchTaken => Some(2192u16),
            Self::InstIntAlu => Some(2199u16),
            Self::InstIntLd => Some(2197u16),
            Self::InstIntSt => Some(2198u16),
            Self::InstLdst => Some(2203u16),
            Self::InstSimdAlu => Some(2202u16),
            Self::InstSimdAluVec => Some(2207u16),
            Self::InstSimdLd => Some(2200u16),
            Self::InstSimdSt => Some(2201u16),
            Self::InstSmeEngineAlu => Some(2211u16),
            Self::InstSmeEngineLd => Some(2209u16),
            Self::InstSmeEnginePackingFused => Some(1321u16),
            Self::InstSmeEngineScalarfp => Some(2208u16),
            Self::InstSmeEngineSt => Some(2210u16),
            Self::InterruptPending => Some(620u16),
            Self::L1DCacheMissLd => Some(1443u16),
            Self::L1DCacheMissLdNonspec => Some(2239u16),
            Self::L1DCacheMissSt => Some(1442u16),
            Self::L1DCacheMissStNonspec => Some(2240u16),
            Self::L1DCacheWriteback => Some(1448u16),
            Self::L1DTlbAccess => Some(1440u16),
            Self::L1DTlbFill => Some(1029u16),
            Self::L1DTlbMiss => Some(1441u16),
            Self::L1DTlbMissNonspec => Some(2241u16),
            Self::L1ICacheMissDemand => Some(16390u16),
            Self::L1ITlbFill => Some(1028u16),
            Self::L1ITlbMissDemand => Some(468u16),
            Self::L2TlbMissData => Some(1035u16),
            Self::L2TlbMissInstruction => Some(1034u16),
            Self::LdBlockedBySmeLdst => Some(1324u16),
            Self::LdNtUop => Some(1510u16),
            Self::LdSmeNormalUop => Some(1397u16),
            Self::LdSmeNtUop => Some(1395u16),
            Self::LdUnitUop => Some(1446u16),
            Self::LdUnitWaitingYoungL1DCacheMiss => Some(660u16),
            Self::LdstSmePredInactive => Some(1399u16),
            Self::LdstSmeXpgUop => Some(1288u16),
            Self::LdstUnitOldL1DCacheMiss => Some(656u16),
            Self::LdstUnitWaitingOldL1DCacheMiss => Some(657u16),
            Self::LdstUnitWaitingSmeEngineInstQueueFull => Some(652u16),
            Self::LdstUnitWaitingSmeEngineMemData => Some(655u16),
            Self::LdstX64Uop => Some(1457u16),
            Self::LdstXpgUop => Some(1458u16),
            Self::MapDispatchBubble => Some(470u16),
            Self::MapDispatchBubbleIc => Some(386u16),
            Self::MapDispatchBubbleItlb => Some(387u16),
            Self::MapDispatchBubbleSlot => Some(481u16),
            Self::MapIntSmeUop => Some(645u16),
            Self::MapIntUop => Some(636u16),
            Self::MapLdstUop => Some(637u16),
            Self::MapRecovery => Some(685u16),
            Self::MapRewind => Some(629u16),
            Self::MapSimdUop => Some(638u16),
            Self::MapStall => Some(630u16),
            Self::MapStallDispatch => Some(624u16),
            Self::MapStallNonrecovery => Some(686u16),
            Self::MapUop => Some(59u16),
            Self::MmuTableWalkData => Some(1032u16),
            Self::MmuTableWalkInstruction => Some(1031u16),
            Self::RetireUop => Some(58u16),
            Self::ScheduleEmpty => Some(849u16),
            Self::ScheduleUop => Some(643u16),
            Self::ScheduleWaitingSmeEngineRegData => Some(654u16),
            Self::SmeEngineSmEnable => Some(646u16),
            Self::SmeEngineSmZaEnable => Some(647u16),
            Self::SmeEngineZaEnabledSmDisabled => Some(648u16),
            Self::StBarrierBlockedBySmeLdst => Some(1326u16),
            Self::StMemOrderViolLdNonspec => Some(2244u16),
            Self::StNtUop => Some(1509u16),
            Self::StSmeNormalUop => Some(1398u16),
            Self::StSmeNtUop => Some(1396u16),
            Self::StUnitUop => Some(1447u16),
        }
    }

    #[inline]
    fn fixed_counter(&self) -> Option<u8> {
        match self {
            Self::ArmBrMisPred => None,
            Self::ArmBrPred => None,
            Self::ArmL1DCache => None,
            Self::ArmL1DCacheLmissRd => None,
            Self::ArmL1DCacheRd => None,
            Self::ArmL1DCacheRefill => None,
            Self::ArmStall => None,
            Self::ArmStallBackend => None,
            Self::ArmStallFrontend => None,
            Self::ArmStallSlot => None,
            Self::ArmStallSlotBackend => None,
            Self::ArmStallSlotFrontend => None,
            Self::AtomicOrExclusiveFail => None,
            Self::AtomicOrExclusiveSucc => None,
            Self::BranchCallIndirMispredNonspec => None,
            Self::BranchCondMispredNonspec => None,
            Self::BranchIndirMispredNonspec => None,
            Self::BranchMispredNonspec => None,
            Self::BranchRetIndirMispredNonspec => None,
            Self::CoreActiveCycle => None,
            Self::FetchRestart => None,
            Self::FixedCycles => Some(0u8),
            Self::FixedInstructions => Some(1u8),
            Self::FlushRestartOtherNonspec => None,
            Self::InstAll => None,
            Self::InstBarrier => None,
            Self::InstBranch => None,
            Self::InstBranchCall => None,
            Self::InstBranchCond => None,
            Self::InstBranchIndir => None,
            Self::InstBranchRet => None,
            Self::InstBranchTaken => None,
            Self::InstIntAlu => None,
            Self::InstIntLd => None,
            Self::InstIntSt => None,
            Self::InstLdst => None,
            Self::InstSimdAlu => None,
            Self::InstSimdAluVec => None,
            Self::InstSimdLd => None,
            Self::InstSimdSt => None,
            Self::InstSmeEngineAlu => None,
            Self::InstSmeEngineLd => None,
            Self::InstSmeEnginePackingFused => None,
            Self::InstSmeEngineScalarfp => None,
            Self::InstSmeEngineSt => None,
            Self::InterruptPending => None,
            Self::L1DCacheMissLd => None,
            Self::L1DCacheMissLdNonspec => None,
            Self::L1DCacheMissSt => None,
            Self::L1DCacheMissStNonspec => None,
            Self::L1DCacheWriteback => None,
            Self::L1DTlbAccess => None,
            Self::L1DTlbFill => None,
            Self::L1DTlbMiss => None,
            Self::L1DTlbMissNonspec => None,
            Self::L1ICacheMissDemand => None,
            Self::L1ITlbFill => None,
            Self::L1ITlbMissDemand => None,
            Self::L2TlbMissData => None,
            Self::L2TlbMissInstruction => None,
            Self::LdBlockedBySmeLdst => None,
            Self::LdNtUop => None,
            Self::LdSmeNormalUop => None,
            Self::LdSmeNtUop => None,
            Self::LdUnitUop => None,
            Self::LdUnitWaitingYoungL1DCacheMiss => None,
            Self::LdstSmePredInactive => None,
            Self::LdstSmeXpgUop => None,
            Self::LdstUnitOldL1DCacheMiss => None,
            Self::LdstUnitWaitingOldL1DCacheMiss => None,
            Self::LdstUnitWaitingSmeEngineInstQueueFull => None,
            Self::LdstUnitWaitingSmeEngineMemData => None,
            Self::LdstX64Uop => None,
            Self::LdstXpgUop => None,
            Self::MapDispatchBubble => None,
            Self::MapDispatchBubbleIc => None,
            Self::MapDispatchBubbleItlb => None,
            Self::MapDispatchBubbleSlot => None,
            Self::MapIntSmeUop => None,
            Self::MapIntUop => None,
            Self::MapLdstUop => None,
            Self::MapRecovery => None,
            Self::MapRewind => None,
            Self::MapSimdUop => None,
            Self::MapStall => None,
            Self::MapStallDispatch => None,
            Self::MapStallNonrecovery => None,
            Self::MapUop => None,
            Self::MmuTableWalkData => None,
            Self::MmuTableWalkInstruction => None,
            Self::RetireUop => None,
            Self::ScheduleEmpty => None,
            Self::ScheduleUop => None,
            Self::ScheduleWaitingSmeEngineRegData => None,
            Self::SmeEngineSmEnable => None,
            Self::SmeEngineSmZaEnable => None,
            Self::SmeEngineZaEnabledSmDisabled => None,
            Self::StBarrierBlockedBySmeLdst => None,
            Self::StMemOrderViolLdNonspec => None,
            Self::StNtUop => None,
            Self::StSmeNormalUop => None,
            Self::StSmeNtUop => None,
            Self::StUnitUop => None,
        }
    }

    #[inline]
    fn fallback(&self) -> Option<&'static str> {
        match self {
            Self::ArmBrMisPred => None,
            Self::ArmBrPred => None,
            Self::ArmL1DCache => None,
            Self::ArmL1DCacheLmissRd => None,
            Self::ArmL1DCacheRd => None,
            Self::ArmL1DCacheRefill => None,
            Self::ArmStall => None,
            Self::ArmStallBackend => None,
            Self::ArmStallFrontend => None,
            Self::ArmStallSlot => None,
            Self::ArmStallSlotBackend => None,
            Self::ArmStallSlotFrontend => None,
            Self::AtomicOrExclusiveFail => None,
            Self::AtomicOrExclusiveSucc => None,
            Self::BranchCallIndirMispredNonspec => None,
            Self::BranchCondMispredNonspec => None,
            Self::BranchIndirMispredNonspec => None,
            Self::BranchMispredNonspec => None,
            Self::BranchRetIndirMispredNonspec => None,
            Self::CoreActiveCycle => None,
            Self::FetchRestart => None,
            Self::FixedCycles => None,
            Self::FixedInstructions => Some("INST_ALL"),
            Self::FlushRestartOtherNonspec => None,
            Self::InstAll => None,
            Self::InstBarrier => None,
            Self::InstBranch => None,
            Self::InstBranchCall => None,
            Self::InstBranchCond => None,
            Self::InstBranchIndir => None,
            Self::InstBranchRet => None,
            Self::InstBranchTaken => None,
            Self::InstIntAlu => None,
            Self::InstIntLd => None,
            Self::InstIntSt => None,
            Self::InstLdst => None,
            Self::InstSimdAlu => None,
            Self::InstSimdAluVec => None,
            Self::InstSimdLd => None,
            Self::InstSimdSt => None,
            Self::InstSmeEngineAlu => None,
            Self::InstSmeEngineLd => None,
            Self::InstSmeEnginePackingFused => None,
            Self::InstSmeEngineScalarfp => None,
            Self::InstSmeEngineSt => None,
            Self::InterruptPending => None,
            Self::L1DCacheMissLd => None,
            Self::L1DCacheMissLdNonspec => None,
            Self::L1DCacheMissSt => None,
            Self::L1DCacheMissStNonspec => None,
            Self::L1DCacheWriteback => None,
            Self::L1DTlbAccess => None,
            Self::L1DTlbFill => None,
            Self::L1DTlbMiss => None,
            Self::L1DTlbMissNonspec => None,
            Self::L1ICacheMissDemand => None,
            Self::L1ITlbFill => None,
            Self::L1ITlbMissDemand => None,
            Self::L2TlbMissData => None,
            Self::L2TlbMissInstruction => None,
            Self::LdBlockedBySmeLdst => None,
            Self::LdNtUop => None,
            Self::LdSmeNormalUop => None,
            Self::LdSmeNtUop => None,
            Self::LdUnitUop => None,
            Self::LdUnitWaitingYoungL1DCacheMiss => None,
            Self::LdstSmePredInactive => None,
            Self::LdstSmeXpgUop => None,
            Self::LdstUnitOldL1DCacheMiss => None,
            Self::LdstUnitWaitingOldL1DCacheMiss => None,
            Self::LdstUnitWaitingSmeEngineInstQueueFull => None,
            Self::LdstUnitWaitingSmeEngineMemData => None,
            Self::LdstX64Uop => None,
            Self::LdstXpgUop => None,
            Self::MapDispatchBubble => None,
            Self::MapDispatchBubbleIc => None,
            Self::MapDispatchBubbleItlb => None,
            Self::MapDispatchBubbleSlot => None,
            Self::MapIntSmeUop => None,
            Self::MapIntUop => None,
            Self::MapLdstUop => None,
            Self::MapRecovery => None,
            Self::MapRewind => None,
            Self::MapSimdUop => None,
            Self::MapStall => None,
            Self::MapStallDispatch => None,
            Self::MapStallNonrecovery => None,
            Self::MapUop => None,
            Self::MmuTableWalkData => None,
            Self::MmuTableWalkInstruction => None,
            Self::RetireUop => None,
            Self::ScheduleEmpty => None,
            Self::ScheduleUop => None,
            Self::ScheduleWaitingSmeEngineRegData => None,
            Self::SmeEngineSmEnable => None,
            Self::SmeEngineSmZaEnable => None,
            Self::SmeEngineZaEnabledSmDisabled => None,
            Self::StBarrierBlockedBySmeLdst => None,
            Self::StMemOrderViolLdNonspec => None,
            Self::StNtUop => None,
            Self::StSmeNormalUop => None,
            Self::StSmeNtUop => None,
            Self::StUnitUop => None,
        }
    }

    #[inline]
    fn aliases(&self) -> &'static [&'static str] {
        match self {
            Self::ArmBrMisPred => &[],
            Self::ArmBrPred => &[],
            Self::ArmL1DCache => &[],
            Self::ArmL1DCacheLmissRd => &[],
            Self::ArmL1DCacheRd => &[],
            Self::ArmL1DCacheRefill => &[],
            Self::ArmStall => &[],
            Self::ArmStallBackend => &[],
            Self::ArmStallFrontend => &[],
            Self::ArmStallSlot => &[],
            Self::ArmStallSlotBackend => &[],
            Self::ArmStallSlotFrontend => &[],
            Self::AtomicOrExclusiveFail => &[],
            Self::AtomicOrExclusiveSucc => &[],
            Self::BranchCallIndirMispredNonspec => &[],
            Self::BranchCondMispredNonspec => &[],
            Self::BranchIndirMispredNonspec => &[],
            Self::BranchMispredNonspec => &[],
            Self::BranchRetIndirMispredNonspec => &[],
            Self::CoreActiveCycle => &[],
            Self::FetchRestart => &[],
            Self::FixedCycles => &["Cycles"],
            Self::FixedInstructions => &["Instructions"],
            Self::FlushRestartOtherNonspec => &[],
            Self::InstAll => &[],
            Self::InstBarrier => &[],
            Self::InstBranch => &[],
            Self::InstBranchCall => &[],
            Self::InstBranchCond => &[],
            Self::InstBranchIndir => &[],
            Self::InstBranchRet => &[],
            Self::InstBranchTaken => &[],
            Self::InstIntAlu => &[],
            Self::InstIntLd => &[],
            Self::InstIntSt => &[],
            Self::InstLdst => &[],
            Self::InstSimdAlu => &[],
            Self::InstSimdAluVec => &[],
            Self::InstSimdLd => &[],
            Self::InstSimdSt => &[],
            Self::InstSmeEngineAlu => &[],
            Self::InstSmeEngineLd => &[],
            Self::InstSmeEnginePackingFused => &[],
            Self::InstSmeEngineScalarfp => &[],
            Self::InstSmeEngineSt => &[],
            Self::InterruptPending => &[],
            Self::L1DCacheMissLd => &[],
            Self::L1DCacheMissLdNonspec => &[],
            Self::L1DCacheMissSt => &[],
            Self::L1DCacheMissStNonspec => &[],
            Self::L1DCacheWriteback => &[],
            Self::L1DTlbAccess => &[],
            Self::L1DTlbFill => &[],
            Self::L1DTlbMiss => &[],
            Self::L1DTlbMissNonspec => &[],
            Self::L1ICacheMissDemand => &[],
            Self::L1ITlbFill => &[],
            Self::L1ITlbMissDemand => &[],
            Self::L2TlbMissData => &[],
            Self::L2TlbMissInstruction => &[],
            Self::LdBlockedBySmeLdst => &[],
            Self::LdNtUop => &[],
            Self::LdSmeNormalUop => &[],
            Self::LdSmeNtUop => &[],
            Self::LdUnitUop => &[],
            Self::LdUnitWaitingYoungL1DCacheMiss => &[],
            Self::LdstSmePredInactive => &[],
            Self::LdstSmeXpgUop => &[],
            Self::LdstUnitOldL1DCacheMiss => &[],
            Self::LdstUnitWaitingOldL1DCacheMiss => &[],
            Self::LdstUnitWaitingSmeEngineInstQueueFull => &[],
            Self::LdstUnitWaitingSmeEngineMemData => &[],
            Self::LdstX64Uop => &[],
            Self::LdstXpgUop => &[],
            Self::MapDispatchBubble => &[],
            Self::MapDispatchBubbleIc => &[],
            Self::MapDispatchBubbleItlb => &[],
            Self::MapDispatchBubbleSlot => &[],
            Self::MapIntSmeUop => &[],
            Self::MapIntUop => &[],
            Self::MapLdstUop => &[],
            Self::MapRecovery => &[],
            Self::MapRewind => &[],
            Self::MapSimdUop => &[],
            Self::MapStall => &[],
            Self::MapStallDispatch => &[],
            Self::MapStallNonrecovery => &[],
            Self::MapUop => &[],
            Self::MmuTableWalkData => &[],
            Self::MmuTableWalkInstruction => &[],
            Self::RetireUop => &[],
            Self::ScheduleEmpty => &[],
            Self::ScheduleUop => &[],
            Self::ScheduleWaitingSmeEngineRegData => &[],
            Self::SmeEngineSmEnable => &[],
            Self::SmeEngineSmZaEnable => &[],
            Self::SmeEngineZaEnabledSmDisabled => &[],
            Self::StBarrierBlockedBySmeLdst => &[],
            Self::StMemOrderViolLdNonspec => &[],
            Self::StNtUop => &[],
            Self::StSmeNormalUop => &[],
            Self::StSmeNtUop => &[],
            Self::StUnitUop => &[],
        }
    }
}
